mirror of https://github.com/PCSX2/pcsx2.git
648 lines
17 KiB
C
648 lines
17 KiB
C
/* CpuArch.h -- CPU specific code
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2024-06-17 : Igor Pavlov : Public domain */
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#ifndef ZIP7_INC_CPU_ARCH_H
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#define ZIP7_INC_CPU_ARCH_H
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#include "7zTypes.h"
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EXTERN_C_BEGIN
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/*
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MY_CPU_LE means that CPU is LITTLE ENDIAN.
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MY_CPU_BE means that CPU is BIG ENDIAN.
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If MY_CPU_LE and MY_CPU_BE are not defined, we don't know about ENDIANNESS of platform.
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MY_CPU_LE_UNALIGN means that CPU is LITTLE ENDIAN and CPU supports unaligned memory accesses.
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MY_CPU_64BIT means that processor can work with 64-bit registers.
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MY_CPU_64BIT can be used to select fast code branch
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MY_CPU_64BIT doesn't mean that (sizeof(void *) == 8)
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*/
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#if !defined(_M_ARM64EC)
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#if defined(_M_X64) \
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|| defined(_M_AMD64) \
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|| defined(__x86_64__) \
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|| defined(__AMD64__) \
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|| defined(__amd64__)
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#define MY_CPU_AMD64
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#ifdef __ILP32__
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#define MY_CPU_NAME "x32"
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#define MY_CPU_SIZEOF_POINTER 4
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#else
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#define MY_CPU_NAME "x64"
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#define MY_CPU_SIZEOF_POINTER 8
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#endif
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#define MY_CPU_64BIT
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#endif
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#endif
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#if defined(_M_IX86) \
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|| defined(__i386__)
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#define MY_CPU_X86
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#define MY_CPU_NAME "x86"
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/* #define MY_CPU_32BIT */
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#define MY_CPU_SIZEOF_POINTER 4
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#endif
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#if defined(_M_ARM64) \
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|| defined(_M_ARM64EC) \
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|| defined(__AARCH64EL__) \
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|| defined(__AARCH64EB__) \
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|| defined(__aarch64__)
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#define MY_CPU_ARM64
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#if defined(__ILP32__) \
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|| defined(__SIZEOF_POINTER__) && (__SIZEOF_POINTER__ == 4)
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#define MY_CPU_NAME "arm64-32"
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#define MY_CPU_SIZEOF_POINTER 4
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#elif defined(__SIZEOF_POINTER__) && (__SIZEOF_POINTER__ == 16)
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#define MY_CPU_NAME "arm64-128"
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#define MY_CPU_SIZEOF_POINTER 16
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#else
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#if defined(_M_ARM64EC)
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#define MY_CPU_NAME "arm64ec"
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#else
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#define MY_CPU_NAME "arm64"
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#endif
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#define MY_CPU_SIZEOF_POINTER 8
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#endif
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#define MY_CPU_64BIT
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#endif
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#if defined(_M_ARM) \
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|| defined(_M_ARM_NT) \
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|| defined(_M_ARMT) \
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|| defined(__arm__) \
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|| defined(__thumb__) \
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|| defined(__ARMEL__) \
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|| defined(__ARMEB__) \
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|| defined(__THUMBEL__) \
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|| defined(__THUMBEB__)
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#define MY_CPU_ARM
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#if defined(__thumb__) || defined(__THUMBEL__) || defined(_M_ARMT)
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#define MY_CPU_ARMT
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#define MY_CPU_NAME "armt"
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#else
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#define MY_CPU_ARM32
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#define MY_CPU_NAME "arm"
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#endif
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/* #define MY_CPU_32BIT */
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#define MY_CPU_SIZEOF_POINTER 4
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#endif
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#if defined(_M_IA64) \
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|| defined(__ia64__)
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#define MY_CPU_IA64
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#define MY_CPU_NAME "ia64"
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#define MY_CPU_64BIT
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#endif
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#if defined(__mips64) \
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|| defined(__mips64__) \
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|| (defined(__mips) && (__mips == 64 || __mips == 4 || __mips == 3))
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#define MY_CPU_NAME "mips64"
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#define MY_CPU_64BIT
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#elif defined(__mips__)
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#define MY_CPU_NAME "mips"
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/* #define MY_CPU_32BIT */
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#endif
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#if defined(__ppc64__) \
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|| defined(__powerpc64__) \
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|| defined(__ppc__) \
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|| defined(__powerpc__) \
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|| defined(__PPC__) \
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|| defined(_POWER)
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#define MY_CPU_PPC_OR_PPC64
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#if defined(__ppc64__) \
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|| defined(__powerpc64__) \
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|| defined(_LP64) \
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|| defined(__64BIT__)
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#ifdef __ILP32__
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#define MY_CPU_NAME "ppc64-32"
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#define MY_CPU_SIZEOF_POINTER 4
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#else
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#define MY_CPU_NAME "ppc64"
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#define MY_CPU_SIZEOF_POINTER 8
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#endif
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#define MY_CPU_64BIT
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#else
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#define MY_CPU_NAME "ppc"
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#define MY_CPU_SIZEOF_POINTER 4
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/* #define MY_CPU_32BIT */
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#endif
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#endif
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#if defined(__sparc__) \
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|| defined(__sparc)
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#define MY_CPU_SPARC
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#if defined(__LP64__) \
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|| defined(_LP64) \
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|| defined(__SIZEOF_POINTER__) && (__SIZEOF_POINTER__ == 8)
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#define MY_CPU_NAME "sparcv9"
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#define MY_CPU_SIZEOF_POINTER 8
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#define MY_CPU_64BIT
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#elif defined(__sparc_v9__) \
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|| defined(__sparcv9)
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#define MY_CPU_64BIT
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#if defined(__SIZEOF_POINTER__) && (__SIZEOF_POINTER__ == 4)
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#define MY_CPU_NAME "sparcv9-32"
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#else
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#define MY_CPU_NAME "sparcv9m"
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#endif
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#elif defined(__sparc_v8__) \
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|| defined(__sparcv8)
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#define MY_CPU_NAME "sparcv8"
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#define MY_CPU_SIZEOF_POINTER 4
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#else
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#define MY_CPU_NAME "sparc"
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#endif
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#endif
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#if defined(__riscv) \
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|| defined(__riscv__)
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#define MY_CPU_RISCV
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#if __riscv_xlen == 32
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#define MY_CPU_NAME "riscv32"
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#elif __riscv_xlen == 64
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#define MY_CPU_NAME "riscv64"
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#else
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#define MY_CPU_NAME "riscv"
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#endif
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#endif
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#if defined(__loongarch__)
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#define MY_CPU_LOONGARCH
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#if defined(__loongarch64) || defined(__loongarch_grlen) && (__loongarch_grlen == 64)
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#define MY_CPU_64BIT
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#endif
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#if defined(__loongarch64)
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#define MY_CPU_NAME "loongarch64"
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#define MY_CPU_LOONGARCH64
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#else
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#define MY_CPU_NAME "loongarch"
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#endif
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#endif
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// #undef MY_CPU_NAME
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// #undef MY_CPU_SIZEOF_POINTER
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// #define __e2k__
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// #define __SIZEOF_POINTER__ 4
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#if defined(__e2k__)
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#define MY_CPU_E2K
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#if defined(__ILP32__) || defined(__SIZEOF_POINTER__) && (__SIZEOF_POINTER__ == 4)
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#define MY_CPU_NAME "e2k-32"
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#define MY_CPU_SIZEOF_POINTER 4
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#else
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#define MY_CPU_NAME "e2k"
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#if defined(__LP64__) || defined(__SIZEOF_POINTER__) && (__SIZEOF_POINTER__ == 8)
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#define MY_CPU_SIZEOF_POINTER 8
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#endif
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#endif
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#define MY_CPU_64BIT
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#endif
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#if defined(MY_CPU_X86) || defined(MY_CPU_AMD64)
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#define MY_CPU_X86_OR_AMD64
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#endif
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#if defined(MY_CPU_ARM) || defined(MY_CPU_ARM64)
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#define MY_CPU_ARM_OR_ARM64
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#endif
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#ifdef _WIN32
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#ifdef MY_CPU_ARM
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#define MY_CPU_ARM_LE
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#endif
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#ifdef MY_CPU_ARM64
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#define MY_CPU_ARM64_LE
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#endif
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#ifdef _M_IA64
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#define MY_CPU_IA64_LE
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#endif
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#endif
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#if defined(MY_CPU_X86_OR_AMD64) \
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|| defined(MY_CPU_ARM_LE) \
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|| defined(MY_CPU_ARM64_LE) \
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|| defined(MY_CPU_IA64_LE) \
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|| defined(_LITTLE_ENDIAN) \
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|| defined(__LITTLE_ENDIAN__) \
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|| defined(__ARMEL__) \
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|| defined(__THUMBEL__) \
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|| defined(__AARCH64EL__) \
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|| defined(__MIPSEL__) \
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|| defined(__MIPSEL) \
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|| defined(_MIPSEL) \
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|| defined(__BFIN__) \
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|| (defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__))
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#define MY_CPU_LE
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#endif
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#if defined(__BIG_ENDIAN__) \
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|| defined(__ARMEB__) \
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|| defined(__THUMBEB__) \
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|| defined(__AARCH64EB__) \
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|| defined(__MIPSEB__) \
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|| defined(__MIPSEB) \
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|| defined(_MIPSEB) \
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|| defined(__m68k__) \
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|| defined(__s390__) \
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|| defined(__s390x__) \
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|| defined(__zarch__) \
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|| (defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__))
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#define MY_CPU_BE
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#endif
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#if defined(MY_CPU_LE) && defined(MY_CPU_BE)
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#error Stop_Compiling_Bad_Endian
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#endif
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#if !defined(MY_CPU_LE) && !defined(MY_CPU_BE)
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#error Stop_Compiling_CPU_ENDIAN_must_be_detected_at_compile_time
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#endif
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#if defined(MY_CPU_32BIT) && defined(MY_CPU_64BIT)
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#error Stop_Compiling_Bad_32_64_BIT
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#endif
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#ifdef __SIZEOF_POINTER__
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#ifdef MY_CPU_SIZEOF_POINTER
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#if MY_CPU_SIZEOF_POINTER != __SIZEOF_POINTER__
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#error Stop_Compiling_Bad_MY_CPU_PTR_SIZE
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#endif
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#else
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#define MY_CPU_SIZEOF_POINTER __SIZEOF_POINTER__
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#endif
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#endif
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#if defined(MY_CPU_SIZEOF_POINTER) && (MY_CPU_SIZEOF_POINTER == 4)
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#if defined (_LP64)
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#error Stop_Compiling_Bad_MY_CPU_PTR_SIZE
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#endif
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#endif
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#ifdef _MSC_VER
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#if _MSC_VER >= 1300
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#define MY_CPU_pragma_pack_push_1 __pragma(pack(push, 1))
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#define MY_CPU_pragma_pop __pragma(pack(pop))
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#else
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#define MY_CPU_pragma_pack_push_1
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#define MY_CPU_pragma_pop
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#endif
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#else
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#ifdef __xlC__
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#define MY_CPU_pragma_pack_push_1 _Pragma("pack(1)")
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#define MY_CPU_pragma_pop _Pragma("pack()")
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#else
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#define MY_CPU_pragma_pack_push_1 _Pragma("pack(push, 1)")
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#define MY_CPU_pragma_pop _Pragma("pack(pop)")
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#endif
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#endif
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#ifndef MY_CPU_NAME
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// #define MY_CPU_IS_UNKNOWN
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#ifdef MY_CPU_LE
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#define MY_CPU_NAME "LE"
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#elif defined(MY_CPU_BE)
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#define MY_CPU_NAME "BE"
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#else
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/*
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#define MY_CPU_NAME ""
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*/
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#endif
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#endif
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#ifdef __has_builtin
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#define Z7_has_builtin(x) __has_builtin(x)
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#else
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#define Z7_has_builtin(x) 0
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#endif
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#define Z7_BSWAP32_CONST(v) \
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( (((UInt32)(v) << 24) ) \
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| (((UInt32)(v) << 8) & (UInt32)0xff0000) \
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| (((UInt32)(v) >> 8) & (UInt32)0xff00 ) \
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| (((UInt32)(v) >> 24) ))
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#if defined(_MSC_VER) && (_MSC_VER >= 1300)
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#include <stdlib.h>
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/* Note: these macros will use bswap instruction (486), that is unsupported in 386 cpu */
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#pragma intrinsic(_byteswap_ushort)
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#pragma intrinsic(_byteswap_ulong)
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#pragma intrinsic(_byteswap_uint64)
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#define Z7_BSWAP16(v) _byteswap_ushort(v)
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#define Z7_BSWAP32(v) _byteswap_ulong (v)
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#define Z7_BSWAP64(v) _byteswap_uint64(v)
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#define Z7_CPU_FAST_BSWAP_SUPPORTED
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/* GCC can generate slow code that calls function for __builtin_bswap32() for:
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- GCC for RISCV, if Zbb/XTHeadBb extension is not used.
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- GCC for SPARC.
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The code from CLANG for SPARC also is not fastest.
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So we don't define Z7_CPU_FAST_BSWAP_SUPPORTED in some cases.
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*/
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#elif (!defined(MY_CPU_RISCV) || defined (__riscv_zbb) || defined(__riscv_xtheadbb)) \
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&& !defined(MY_CPU_SPARC) \
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&& ( \
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(defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3))) \
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|| (defined(__clang__) && Z7_has_builtin(__builtin_bswap16)) \
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)
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#define Z7_BSWAP16(v) __builtin_bswap16(v)
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#define Z7_BSWAP32(v) __builtin_bswap32(v)
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#define Z7_BSWAP64(v) __builtin_bswap64(v)
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#define Z7_CPU_FAST_BSWAP_SUPPORTED
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#else
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#define Z7_BSWAP16(v) ((UInt16) \
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( ((UInt32)(v) << 8) \
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| ((UInt32)(v) >> 8) \
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))
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#define Z7_BSWAP32(v) Z7_BSWAP32_CONST(v)
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#define Z7_BSWAP64(v) \
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( ( ( (UInt64)(v) ) << 8 * 7 ) \
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| ( ( (UInt64)(v) & ((UInt32)0xff << 8 * 1) ) << 8 * 5 ) \
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| ( ( (UInt64)(v) & ((UInt32)0xff << 8 * 2) ) << 8 * 3 ) \
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| ( ( (UInt64)(v) & ((UInt32)0xff << 8 * 3) ) << 8 * 1 ) \
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| ( ( (UInt64)(v) >> 8 * 1 ) & ((UInt32)0xff << 8 * 3) ) \
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| ( ( (UInt64)(v) >> 8 * 3 ) & ((UInt32)0xff << 8 * 2) ) \
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| ( ( (UInt64)(v) >> 8 * 5 ) & ((UInt32)0xff << 8 * 1) ) \
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| ( ( (UInt64)(v) >> 8 * 7 ) ) \
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)
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#endif
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#ifdef MY_CPU_LE
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#if defined(MY_CPU_X86_OR_AMD64) \
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|| defined(MY_CPU_ARM64) \
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|| defined(MY_CPU_RISCV) && defined(__riscv_misaligned_fast) \
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|| defined(MY_CPU_E2K) && defined(__iset__) && (__iset__ >= 6)
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#define MY_CPU_LE_UNALIGN
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#define MY_CPU_LE_UNALIGN_64
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#elif defined(__ARM_FEATURE_UNALIGNED)
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/* === ALIGNMENT on 32-bit arm and LDRD/STRD/LDM/STM instructions.
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Description of problems:
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problem-1 : 32-bit ARM architecture:
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multi-access (pair of 32-bit accesses) instructions (LDRD/STRD/LDM/STM)
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require 32-bit (WORD) alignment (by 32-bit ARM architecture).
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So there is "Alignment fault exception", if data is not aligned for 32-bit.
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problem-2 : 32-bit kernels and arm64 kernels:
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32-bit linux kernels provide fixup for these "paired" instruction "Alignment fault exception".
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So unaligned paired-access instructions work via exception handler in kernel in 32-bit linux.
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But some arm64 kernels do not handle these faults in 32-bit programs.
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So we have unhandled exception for such instructions.
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Probably some new arm64 kernels have fixed it, and unaligned
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paired-access instructions work in new kernels?
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problem-3 : compiler for 32-bit arm:
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Compilers use LDRD/STRD/LDM/STM for UInt64 accesses
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and for another cases where two 32-bit accesses are fused
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to one multi-access instruction.
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So UInt64 variables must be aligned for 32-bit, and each
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32-bit access must be aligned for 32-bit, if we want to
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avoid "Alignment fault" exception (handled or unhandled).
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problem-4 : performace:
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Even if unaligned access is handled by kernel, it will be slow.
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So if we allow unaligned access, we can get fast unaligned
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single-access, and slow unaligned paired-access.
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We don't allow unaligned access on 32-bit arm, because compiler
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genarates paired-access instructions that require 32-bit alignment,
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and some arm64 kernels have no handler for these instructions.
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Also unaligned paired-access instructions will be slow, if kernel handles them.
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*/
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// it must be disabled:
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// #define MY_CPU_LE_UNALIGN
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#endif
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#endif
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#ifdef MY_CPU_LE_UNALIGN
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#define GetUi16(p) (*(const UInt16 *)(const void *)(p))
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#define GetUi32(p) (*(const UInt32 *)(const void *)(p))
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#ifdef MY_CPU_LE_UNALIGN_64
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#define GetUi64(p) (*(const UInt64 *)(const void *)(p))
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#define SetUi64(p, v) { *(UInt64 *)(void *)(p) = (v); }
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#endif
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#define SetUi16(p, v) { *(UInt16 *)(void *)(p) = (v); }
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#define SetUi32(p, v) { *(UInt32 *)(void *)(p) = (v); }
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#else
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#define GetUi16(p) ( (UInt16) ( \
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((const Byte *)(p))[0] | \
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((UInt16)((const Byte *)(p))[1] << 8) ))
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#define GetUi32(p) ( \
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((const Byte *)(p))[0] | \
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((UInt32)((const Byte *)(p))[1] << 8) | \
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((UInt32)((const Byte *)(p))[2] << 16) | \
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((UInt32)((const Byte *)(p))[3] << 24))
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#define SetUi16(p, v) { Byte *_ppp_ = (Byte *)(p); UInt32 _vvv_ = (v); \
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_ppp_[0] = (Byte)_vvv_; \
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_ppp_[1] = (Byte)(_vvv_ >> 8); }
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#define SetUi32(p, v) { Byte *_ppp_ = (Byte *)(p); UInt32 _vvv_ = (v); \
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_ppp_[0] = (Byte)_vvv_; \
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_ppp_[1] = (Byte)(_vvv_ >> 8); \
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_ppp_[2] = (Byte)(_vvv_ >> 16); \
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_ppp_[3] = (Byte)(_vvv_ >> 24); }
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#endif
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#ifndef GetUi64
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#define GetUi64(p) (GetUi32(p) | ((UInt64)GetUi32(((const Byte *)(p)) + 4) << 32))
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#endif
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#ifndef SetUi64
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#define SetUi64(p, v) { Byte *_ppp2_ = (Byte *)(p); UInt64 _vvv2_ = (v); \
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SetUi32(_ppp2_ , (UInt32)_vvv2_) \
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SetUi32(_ppp2_ + 4, (UInt32)(_vvv2_ >> 32)) }
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#endif
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#if defined(MY_CPU_LE_UNALIGN) && defined(Z7_CPU_FAST_BSWAP_SUPPORTED)
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#define GetBe32(p) Z7_BSWAP32 (*(const UInt32 *)(const void *)(p))
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#define SetBe32(p, v) { (*(UInt32 *)(void *)(p)) = Z7_BSWAP32(v); }
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#if defined(MY_CPU_LE_UNALIGN_64)
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#define GetBe64(p) Z7_BSWAP64 (*(const UInt64 *)(const void *)(p))
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#endif
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#else
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#define GetBe32(p) ( \
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((UInt32)((const Byte *)(p))[0] << 24) | \
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((UInt32)((const Byte *)(p))[1] << 16) | \
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((UInt32)((const Byte *)(p))[2] << 8) | \
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((const Byte *)(p))[3] )
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#define SetBe32(p, v) { Byte *_ppp_ = (Byte *)(p); UInt32 _vvv_ = (v); \
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_ppp_[0] = (Byte)(_vvv_ >> 24); \
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_ppp_[1] = (Byte)(_vvv_ >> 16); \
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_ppp_[2] = (Byte)(_vvv_ >> 8); \
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_ppp_[3] = (Byte)_vvv_; }
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#endif
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#ifndef GetBe64
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#define GetBe64(p) (((UInt64)GetBe32(p) << 32) | GetBe32(((const Byte *)(p)) + 4))
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#endif
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#ifndef GetBe16
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|
#define GetBe16(p) ( (UInt16) ( \
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|
((UInt16)((const Byte *)(p))[0] << 8) | \
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|
((const Byte *)(p))[1] ))
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#endif
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#if defined(MY_CPU_BE)
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#define Z7_CONV_BE_TO_NATIVE_CONST32(v) (v)
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|
#define Z7_CONV_LE_TO_NATIVE_CONST32(v) Z7_BSWAP32_CONST(v)
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|
#define Z7_CONV_NATIVE_TO_BE_32(v) (v)
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#elif defined(MY_CPU_LE)
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|
#define Z7_CONV_BE_TO_NATIVE_CONST32(v) Z7_BSWAP32_CONST(v)
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|
#define Z7_CONV_LE_TO_NATIVE_CONST32(v) (v)
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|
#define Z7_CONV_NATIVE_TO_BE_32(v) Z7_BSWAP32(v)
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|
#else
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|
#error Stop_Compiling_Unknown_Endian_CONV
|
|
#endif
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|
|
#if defined(MY_CPU_BE)
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|
#define GetBe64a(p) (*(const UInt64 *)(const void *)(p))
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|
#define GetBe32a(p) (*(const UInt32 *)(const void *)(p))
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|
#define GetBe16a(p) (*(const UInt16 *)(const void *)(p))
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|
#define SetBe32a(p, v) { *(UInt32 *)(void *)(p) = (v); }
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|
#define SetBe16a(p, v) { *(UInt16 *)(void *)(p) = (v); }
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|
|
|
#define GetUi64a(p) GetUi64(p)
|
|
#define GetUi32a(p) GetUi32(p)
|
|
#define GetUi16a(p) GetUi16(p)
|
|
#define SetUi32a(p, v) SetUi32(p, v)
|
|
#define SetUi16a(p, v) SetUi16(p, v)
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|
|
|
#elif defined(MY_CPU_LE)
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|
|
|
#define GetUi64a(p) (*(const UInt64 *)(const void *)(p))
|
|
#define GetUi32a(p) (*(const UInt32 *)(const void *)(p))
|
|
#define GetUi16a(p) (*(const UInt16 *)(const void *)(p))
|
|
#define SetUi32a(p, v) { *(UInt32 *)(void *)(p) = (v); }
|
|
#define SetUi16a(p, v) { *(UInt16 *)(void *)(p) = (v); }
|
|
|
|
#define GetBe64a(p) GetBe64(p)
|
|
#define GetBe32a(p) GetBe32(p)
|
|
#define GetBe16a(p) GetBe16(p)
|
|
#define SetBe32a(p, v) SetBe32(p, v)
|
|
#define SetBe16a(p, v) SetBe16(p, v)
|
|
|
|
#else
|
|
#error Stop_Compiling_Unknown_Endian_CPU_a
|
|
#endif
|
|
|
|
|
|
#if defined(MY_CPU_X86_OR_AMD64) \
|
|
|| defined(MY_CPU_ARM_OR_ARM64) \
|
|
|| defined(MY_CPU_PPC_OR_PPC64)
|
|
#define Z7_CPU_FAST_ROTATE_SUPPORTED
|
|
#endif
|
|
|
|
|
|
#ifdef MY_CPU_X86_OR_AMD64
|
|
|
|
void Z7_FASTCALL z7_x86_cpuid(UInt32 a[4], UInt32 function);
|
|
UInt32 Z7_FASTCALL z7_x86_cpuid_GetMaxFunc(void);
|
|
#if defined(MY_CPU_AMD64)
|
|
#define Z7_IF_X86_CPUID_SUPPORTED
|
|
#else
|
|
#define Z7_IF_X86_CPUID_SUPPORTED if (z7_x86_cpuid_GetMaxFunc())
|
|
#endif
|
|
|
|
BoolInt CPU_IsSupported_AES(void);
|
|
BoolInt CPU_IsSupported_AVX(void);
|
|
BoolInt CPU_IsSupported_AVX2(void);
|
|
BoolInt CPU_IsSupported_AVX512F_AVX512VL(void);
|
|
BoolInt CPU_IsSupported_VAES_AVX2(void);
|
|
BoolInt CPU_IsSupported_CMOV(void);
|
|
BoolInt CPU_IsSupported_SSE(void);
|
|
BoolInt CPU_IsSupported_SSE2(void);
|
|
BoolInt CPU_IsSupported_SSSE3(void);
|
|
BoolInt CPU_IsSupported_SSE41(void);
|
|
BoolInt CPU_IsSupported_SHA(void);
|
|
BoolInt CPU_IsSupported_PageGB(void);
|
|
|
|
#elif defined(MY_CPU_ARM_OR_ARM64)
|
|
|
|
BoolInt CPU_IsSupported_CRC32(void);
|
|
BoolInt CPU_IsSupported_NEON(void);
|
|
|
|
#if defined(_WIN32)
|
|
BoolInt CPU_IsSupported_CRYPTO(void);
|
|
#define CPU_IsSupported_SHA1 CPU_IsSupported_CRYPTO
|
|
#define CPU_IsSupported_SHA2 CPU_IsSupported_CRYPTO
|
|
#define CPU_IsSupported_AES CPU_IsSupported_CRYPTO
|
|
#else
|
|
BoolInt CPU_IsSupported_SHA1(void);
|
|
BoolInt CPU_IsSupported_SHA2(void);
|
|
BoolInt CPU_IsSupported_AES(void);
|
|
#endif
|
|
|
|
#endif
|
|
|
|
#if defined(__APPLE__)
|
|
int z7_sysctlbyname_Get(const char *name, void *buf, size_t *bufSize);
|
|
int z7_sysctlbyname_Get_UInt32(const char *name, UInt32 *val);
|
|
#endif
|
|
|
|
EXTERN_C_END
|
|
|
|
#endif
|