mirror of https://github.com/PCSX2/pcsx2.git
261 lines
6.9 KiB
C
261 lines
6.9 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2008 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <string.h>
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#include "PsxCommon.h"
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// Dma0/1 in Mdec.c
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// Dma3 in CdRom.c
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// Dma8 in PsxSpd.c
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// Dma11/12 in PsxSio2.c
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int iopsifbusy[2] = { 0, 0 };
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void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
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const int size = (bcr >> 16) * (bcr & 0xFFFF); // Number of blocks to transfer
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/*if (chcr & 0x400) SysPrintf("SPU 2 DMA 4 linked list chain mode! chcr = %x madr = %x bcr = %x\n", chcr, madr, bcr);
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if (chcr & 0x40000000) SysPrintf("SPU 2 DMA 4 Unusual bit set on 'to' direction chcr = %x madr = %x bcr = %x\n", chcr, madr, bcr);
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if ((chcr & 0x1) == 0) SysPrintf("SPU 2 DMA 4 loading from spu2 memory chcr = %x madr = %x bcr = %x\n", chcr, madr, bcr);*/
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if(SPU2async)
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{
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
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//SysPrintf("cycles sent to SPU2 %x\n", psxRegs.cycle - psxCounters[6].sCycleT);
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psxCounters[6].sCycleT = psxRegs.cycle;
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psxCounters[6].CycleT = size * 3;
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psxNextCounter -= (psxRegs.cycle-psxNextsCounter);
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psxNextsCounter = psxRegs.cycle;
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if(psxCounters[6].CycleT < psxNextCounter) psxNextCounter = psxCounters[6].CycleT;
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}
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switch (chcr) {
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case 0x01000201: //cpu to spu transfer
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PSXDMA_LOG("*** DMA 4 - SPU mem2spu *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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//SysPrintf("DMA4 write blocks %x, size per block %x\n", (bcr >> 16), (bcr & 0xFFFF));
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SPU2writeDMA4Mem((u16 *)PSXM(madr), size*2);
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break;
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case 0x01000200: //spu to cpu transfer
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PSXDMA_LOG("*** DMA 4 - SPU spu2mem *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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//SysPrintf("DMA4 read blocks %x, size per block %x\n", (bcr >> 16), (bcr & 0xFFFF));
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SPU2readDMA4Mem((u16 *)PSXM(madr), size*2);
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psxCpu->Clear(HW_DMA4_MADR, size);
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break;
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default:
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SysPrintf("*** DMA 4 - SPU unknown *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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break;
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}
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}
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int psxDma4Interrupt() {
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HW_DMA4_CHCR &= ~0x01000000;
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psxDmaInterrupt(4);
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psxHu32(0x1070)|= 1<<9;
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return 1;
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}
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void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
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HW_DMA2_CHCR &= ~0x01000000;
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psxDmaInterrupt(2);
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}
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void psxDma6(u32 madr, u32 bcr, u32 chcr) {
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u32 *mem = (u32 *)PSXM(madr);
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PSXDMA_LOG("*** DMA 6 - OT *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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if (chcr == 0x11000002) {
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while (bcr--) {
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*mem-- = (madr - 4) & 0xffffff;
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madr -= 4;
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}
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mem++; *mem = 0xffffff;
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} else {
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// Unknown option
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PSXDMA_LOG("*** DMA 6 - OT unknown *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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}
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HW_DMA6_CHCR &= ~0x01000000;
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psxDmaInterrupt(6);
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}
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void psxDma7(u32 madr, u32 bcr, u32 chcr) {
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int size = (bcr >> 16) * (bcr & 0xFFFF);
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if(SPU2async)
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{
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
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psxCounters[6].sCycleT = psxRegs.cycle;
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psxCounters[6].CycleT = size * 3;
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psxNextCounter -= (psxRegs.cycle-psxNextsCounter);
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psxNextsCounter = psxRegs.cycle;
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if(psxCounters[6].CycleT < psxNextCounter) psxNextCounter = psxCounters[6].CycleT;
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}
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switch (chcr) {
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case 0x01000201: //cpu to spu2 transfer
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PSXDMA_LOG("*** DMA 7 - SPU2 mem2spu *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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//SysPrintf("DMA7 write blocks %x, size per block %x\n", (bcr >> 16), (bcr & 0xFFFF));
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SPU2writeDMA7Mem((u16 *)PSXM(madr), size*2);
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break;
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case 0x01000200: //spu2 to cpu transfer
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PSXDMA_LOG("*** DMA 7 - SPU2 spu2mem *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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//SysPrintf("DMA7 read blocks %x, size per block %x\n", (bcr >> 16), (bcr & 0xFFFF));
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SPU2readDMA7Mem((u16 *)PSXM(madr), size*2);
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psxCpu->Clear(HW_DMA7_MADR, size);
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break;
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default:
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SysPrintf("*** DMA 7 - SPU unknown *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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break;
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}
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}
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int psxDma7Interrupt() {
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HW_DMA7_CHCR &= ~0x01000000;
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psxDmaInterrupt2(0);
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return 1;
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}
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extern int eesifbusy[2];
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void psxDma9(u32 madr, u32 bcr, u32 chcr) {
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SIF_LOG("IOP: dmaSIF0 chcr = %lx, madr = %lx, bcr = %lx, tadr = %lx\n", chcr, madr, bcr, HW_DMA9_TADR);
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iopsifbusy[0] = 1;
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psHu32(0x1000F240) |= 0x2000;
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if (eesifbusy[0] == 1) {
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SIF0Dma();
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psHu32(0x1000F240) &= ~0x20;
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psHu32(0x1000F240) &= ~0x2000;
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}
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}
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void psxDma10(u32 madr, u32 bcr, u32 chcr) {
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SIF_LOG("IOP: dmaSIF1 chcr = %lx, madr = %lx, bcr = %lx\n", chcr, madr, bcr);
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iopsifbusy[1] = 1;
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psHu32(0x1000F240) |= 0x4000;
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if (eesifbusy[1] == 1) {
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FreezeXMMRegs(1);
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SIF1Dma();
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psHu32(0x1000F240) &= ~0x40;
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psHu32(0x1000F240) &= ~0x100;
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psHu32(0x1000F240) &= ~0x4000;
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FreezeXMMRegs(0);
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}
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}
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void psxDma8(u32 madr, u32 bcr, u32 chcr) {
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int size;
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switch (chcr & 0x01000201) {
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case 0x01000201: //cpu to dev9 transfer
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PSXDMA_LOG("*** DMA 8 - DEV9 mem2dev9 *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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size = (bcr >> 16) * (bcr & 0xFFFF); // Number of blocks to transfer
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DEV9writeDMA8Mem((u32*)PSXM(madr), size*8);
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break;
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case 0x01000200: //dev9 to cpu transfer
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PSXDMA_LOG("*** DMA 8 - DEV9 dev9mem *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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size = (bcr >> 16) * (bcr & 0xFFFF); // Number of blocks to transfer
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DEV9readDMA8Mem((u32*)PSXM(madr), size*8);
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break;
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default:
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PSXDMA_LOG("*** DMA 8 - DEV9 unknown *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
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break;
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}
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HW_DMA8_CHCR &= ~0x01000000;
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psxDmaInterrupt2(1);
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}
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void dev9Interrupt() {
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if (dev9Handler == NULL) goto irq;
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if (dev9Handler() != 1) {
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psxRegs.interrupt&= ~(1 << 20);
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return;
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}
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irq:
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psxHu32(0x1070)|= 1<<13;
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//SBUS
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hwIntcIrq(INTC_SBUS);
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psxRegs.interrupt&= ~(1 << 20);
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}
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void dev9Irq(int cycles) {
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PSX_INT(20, cycles);
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}
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void usbInterrupt() {
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if (usbHandler == NULL) goto irq;
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if (usbHandler() != 1) {
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psxRegs.interrupt&= ~(1 << 21);
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return;
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}
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irq:
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psxHu32(0x1070)|= 1<<22;
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//SBUS
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hwIntcIrq(INTC_SBUS);
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psxRegs.interrupt&= ~(1 << 21);
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}
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void usbIrq(int cycles) {
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PSX_INT(21, cycles);
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}
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void fwIrq() {
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psxHu32(0x1070)|= 1<<24;
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//SBUS
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hwIntcIrq(INTC_SBUS);
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}
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void spu2DMA4Irq() {
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SPU2interruptDMA4();
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//HW_DMA4_BCR = 0;
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HW_DMA4_CHCR &= ~0x01000000;
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psxDmaInterrupt(4);
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}
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void spu2DMA7Irq() {
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SPU2interruptDMA7();
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//HW_DMA7_BCR = 0;
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HW_DMA7_CHCR &= ~0x01000000;
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psxDmaInterrupt2(0);
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}
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void spu2Irq() {
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psxHu32(0x1070)|= 1<<9;
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//SBUS
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hwIntcIrq(INTC_SBUS);
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}
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