mirror of https://github.com/PCSX2/pcsx2.git
395 lines
13 KiB
C++
395 lines
13 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "R3000A.h"
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#include "IopGte.h"
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#include "IopMem.h"
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// Note: Branch instructions of the Interpreter are defined externally because
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// the recompiler shouldn't be using them (it isn't entirely safe, due to the
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// delay slot and event handling differences between recs and ints)
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void psxBGEZ();
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void psxBGEZAL();
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void psxBGTZ();
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void psxBLEZ();
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void psxBLTZ();
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void psxBLTZAL();
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void psxBEQ();
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void psxBNE();
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void psxJ();
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void psxJAL();
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void psxJR();
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void psxJALR();
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/*********************************************************
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* Arithmetic with immediate operand *
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* Format: OP rt, rs, immediate *
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*********************************************************/
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void psxADDI() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) + _Imm_ ; } // Rt = Rs + Im (Exception on Integer Overflow)
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void psxADDIU() { // Rt = Rs + Im
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if (!_Rt_)
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return;
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_rRt_ = _u32(_rRs_) + _Imm_ ;
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}
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void psxANDI() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) & _ImmU_; } // Rt = Rs And Im
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void psxORI() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) | _ImmU_; } // Rt = Rs Or Im
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void psxXORI() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) ^ _ImmU_; } // Rt = Rs Xor Im
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void psxSLTI() { if (!_Rt_) return; _rRt_ = _i32(_rRs_) < _Imm_ ; } // Rt = Rs < Im (Signed)
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void psxSLTIU() { if (!_Rt_) return; _rRt_ = _u32(_rRs_) < (u32)_Imm_; } // Rt = Rs < Im (Unsigned)
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/*********************************************************
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* Register arithmetic *
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* Format: OP rd, rs, rt *
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*********************************************************/
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void psxADD() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) + _u32(_rRt_); } // Rd = Rs + Rt (Exception on Integer Overflow)
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void psxADDU() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) + _u32(_rRt_); } // Rd = Rs + Rt
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void psxSUB() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) - _u32(_rRt_); } // Rd = Rs - Rt (Exception on Integer Overflow)
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void psxSUBU() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) - _u32(_rRt_); } // Rd = Rs - Rt
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void psxAND() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) & _u32(_rRt_); } // Rd = Rs And Rt
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void psxOR() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) | _u32(_rRt_); } // Rd = Rs Or Rt
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void psxXOR() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) ^ _u32(_rRt_); } // Rd = Rs Xor Rt
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void psxNOR() { if (!_Rd_) return; _rRd_ =~(_u32(_rRs_) | _u32(_rRt_)); }// Rd = Rs Nor Rt
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void psxSLT() { if (!_Rd_) return; _rRd_ = _i32(_rRs_) < _i32(_rRt_); } // Rd = Rs < Rt (Signed)
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void psxSLTU() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) < _u32(_rRt_); } // Rd = Rs < Rt (Unsigned)
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/*********************************************************
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* Register mult/div & Register trap logic *
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* Format: OP rs, rt *
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*********************************************************/
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void psxDIV() {
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if (_rRt_ == 0) {
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// Division by 0
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_rLo_ = _i32(_rRs_) < 0 ? 1 : 0xFFFFFFFFu;
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_rHi_ = _rRs_;
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} else if (_rRs_ == 0x80000000u && _rRt_ == 0xFFFFFFFFu) {
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// x86 overflow
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_rLo_ = 0x80000000u;
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_rHi_ = 0;
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} else {
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// Normal behavior
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_rLo_ = _i32(_rRs_) / _i32(_rRt_);
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_rHi_ = _i32(_rRs_) % _i32(_rRt_);
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}
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}
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void psxDIVU() {
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if (_rRt_ == 0) {
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// Division by 0
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_rLo_ = 0xFFFFFFFFu;
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_rHi_ = _rRs_;
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} else {
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// Normal behavior
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_rLo_ = _rRs_ / _rRt_;
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_rHi_ = _rRs_ % _rRt_;
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}
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}
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void psxMULT() {
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u64 res = (s64)((s64)_i32(_rRs_) * (s64)_i32(_rRt_));
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psxRegs.GPR.n.lo = (u32)(res & 0xffffffff);
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psxRegs.GPR.n.hi = (u32)((res >> 32) & 0xffffffff);
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}
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void psxMULTU() {
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u64 res = (u64)((u64)_u32(_rRs_) * (u64)_u32(_rRt_));
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psxRegs.GPR.n.lo = (u32)(res & 0xffffffff);
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psxRegs.GPR.n.hi = (u32)((res >> 32) & 0xffffffff);
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}
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/*********************************************************
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* Shift arithmetic with constant shift *
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* Format: OP rd, rt, sa *
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*********************************************************/
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void psxSLL() { if (!_Rd_) return; _rRd_ = _u32(_rRt_) << _Sa_; } // Rd = Rt << sa
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void psxSRA() { if (!_Rd_) return; _rRd_ = _i32(_rRt_) >> _Sa_; } // Rd = Rt >> sa (arithmetic)
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void psxSRL() { if (!_Rd_) return; _rRd_ = _u32(_rRt_) >> _Sa_; } // Rd = Rt >> sa (logical)
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/*********************************************************
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* Shift arithmetic with variant register shift *
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* Format: OP rd, rt, rs *
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*********************************************************/
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void psxSLLV() { if (!_Rd_) return; _rRd_ = _u32(_rRt_) << _u32(_rRs_); } // Rd = Rt << rs
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void psxSRAV() { if (!_Rd_) return; _rRd_ = _i32(_rRt_) >> _u32(_rRs_); } // Rd = Rt >> rs (arithmetic)
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void psxSRLV() { if (!_Rd_) return; _rRd_ = _u32(_rRt_) >> _u32(_rRs_); } // Rd = Rt >> rs (logical)
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/*********************************************************
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* Load higher 16 bits of the first word in GPR with imm *
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* Format: OP rt, immediate *
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*********************************************************/
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void psxLUI() { if (!_Rt_) return; _rRt_ = psxRegs.code << 16; } // Upper halfword of Rt = Im
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/*********************************************************
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* Move from HI/LO to GPR *
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* Format: OP rd *
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*********************************************************/
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void psxMFHI() { if (!_Rd_) return; _rRd_ = _rHi_; } // Rd = Hi
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void psxMFLO() { if (!_Rd_) return; _rRd_ = _rLo_; } // Rd = Lo
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/*********************************************************
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* Move to GPR to HI/LO & Register jump *
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* Format: OP rs *
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*********************************************************/
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void psxMTHI() { _rHi_ = _rRs_; } // Hi = Rs
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void psxMTLO() { _rLo_ = _rRs_; } // Lo = Rs
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/*********************************************************
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* Special purpose instructions *
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* Format: OP *
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*********************************************************/
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void psxBREAK() {
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// Break exception - psx rom doens't handles this
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psxRegs.pc -= 4;
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psxException(0x24, iopIsDelaySlot);
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}
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void psxSYSCALL() {
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psxRegs.pc -= 4;
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psxException(0x20, iopIsDelaySlot);
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}
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void psxRFE() {
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// Console.WriteLn("RFE\n");
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psxRegs.CP0.n.Status = (psxRegs.CP0.n.Status & 0xfffffff0) |
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((psxRegs.CP0.n.Status & 0x3c) >> 2);
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// Log=0;
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}
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/*********************************************************
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* Load and store for GPR *
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* Format: OP rt, offset(base) *
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*********************************************************/
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#define _oB_ (_u32(_rRs_) + _Imm_)
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void psxLB() {
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if (_Rt_) {
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_rRt_ = (s8 )iopMemRead8(_oB_);
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} else {
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iopMemRead8(_oB_);
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}
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}
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void psxLBU() {
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if (_Rt_) {
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_rRt_ = iopMemRead8(_oB_);
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} else {
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iopMemRead8(_oB_);
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}
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}
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void psxLH() {
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if (_Rt_) {
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_rRt_ = (s16)iopMemRead16(_oB_);
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} else {
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iopMemRead16(_oB_);
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}
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}
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void psxLHU() {
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if (_Rt_) {
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_rRt_ = iopMemRead16(_oB_);
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} else {
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iopMemRead16(_oB_);
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}
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}
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void psxLW() {
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if (_Rt_) {
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_rRt_ = iopMemRead32(_oB_);
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} else {
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iopMemRead32(_oB_);
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}
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}
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void psxLWL() {
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u32 shift = (_oB_ & 3) << 3;
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u32 mem = iopMemRead32(_oB_ & 0xfffffffc);
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if (!_Rt_) return;
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_rRt_ = ( _u32(_rRt_) & (0x00ffffff >> shift) ) |
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( mem << (24 - shift) );
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/*
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Mem = 1234. Reg = abcd
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0 4bcd (mem << 24) | (reg & 0x00ffffff)
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1 34cd (mem << 16) | (reg & 0x0000ffff)
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2 234d (mem << 8) | (reg & 0x000000ff)
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3 1234 (mem ) | (reg & 0x00000000)
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*/
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}
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void psxLWR() {
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u32 shift = (_oB_ & 3) << 3;
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u32 mem = iopMemRead32(_oB_ & 0xfffffffc);
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if (!_Rt_) return;
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_rRt_ = ( _u32(_rRt_) & (0xffffff00 << (24 - shift)) ) |
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( mem >> shift );
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/*
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Mem = 1234. Reg = abcd
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0 1234 (mem ) | (reg & 0x00000000)
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1 a123 (mem >> 8) | (reg & 0xff000000)
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2 ab12 (mem >> 16) | (reg & 0xffff0000)
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3 abc1 (mem >> 24) | (reg & 0xffffff00)
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*/
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}
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void psxSB() { iopMemWrite8 (_oB_, _u8 (_rRt_)); }
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void psxSH() { iopMemWrite16(_oB_, _u16(_rRt_)); }
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void psxSW() { iopMemWrite32(_oB_, _u32(_rRt_)); }
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void psxSWL() {
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u32 shift = (_oB_ & 3) << 3;
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u32 mem = iopMemRead32(_oB_ & 0xfffffffc);
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iopMemWrite32((_oB_ & 0xfffffffc), ( ( _u32(_rRt_) >> (24 - shift) ) ) |
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( mem & (0xffffff00 << shift) ));
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/*
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Mem = 1234. Reg = abcd
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0 123a (reg >> 24) | (mem & 0xffffff00)
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1 12ab (reg >> 16) | (mem & 0xffff0000)
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2 1abc (reg >> 8) | (mem & 0xff000000)
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3 abcd (reg ) | (mem & 0x00000000)
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*/
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}
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void psxSWR() {
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u32 shift = (_oB_ & 3) << 3;
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u32 mem = iopMemRead32(_oB_ & 0xfffffffc);
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iopMemWrite32((_oB_ & 0xfffffffc), ( ( _u32(_rRt_) << shift ) |
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(mem & (0x00ffffff >> (24 - shift)) ) ) );
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/*
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Mem = 1234. Reg = abcd
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0 abcd (reg ) | (mem & 0x00000000)
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1 bcd4 (reg << 8) | (mem & 0x000000ff)
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2 cd34 (reg << 16) | (mem & 0x0000ffff)
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3 d234 (reg << 24) | (mem & 0x00ffffff)
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*/
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}
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/*********************************************************
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* Moves between GPR and COPx *
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* Format: OP rt, fs *
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*********************************************************/
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void psxMFC0() { if (!_Rt_) return; _rRt_ = (int)_rFs_; }
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void psxCFC0() { if (!_Rt_) return; _rRt_ = (int)_rFs_; }
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void psxMTC0() { _rFs_ = _u32(_rRt_); }
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void psxCTC0() { _rFs_ = _u32(_rRt_); }
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void psxCTC2() { _c2dRd_ = _u32(_rRt_); };
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/*********************************************************
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* Unknown instruction (would generate an exception) *
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* Format: ? *
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*********************************************************/
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void psxNULL() {
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Console.Warning("psx: Unimplemented op %x", psxRegs.code);
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}
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void psxSPECIAL() {
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psxSPC[_Funct_]();
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}
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void psxREGIMM() {
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psxREG[_Rt_]();
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}
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void psxCOP0() {
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psxCP0[_Rs_]();
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}
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void psxCOP2() {
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psxCP2[_Funct_]();
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}
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void psxBASIC() {
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psxCP2BSC[_Rs_]();
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}
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void(*psxBSC[64])() = {
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psxSPECIAL, psxREGIMM, psxJ , psxJAL , psxBEQ , psxBNE , psxBLEZ, psxBGTZ, //7
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psxADDI , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI , //15
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psxCOP0 , psxNULL , psxCOP2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, //23
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psxNULL , psxNULL , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, //31
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psxLB , psxLH , psxLWL , psxLW , psxLBU , psxLHU , psxLWR , psxNULL, //39
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psxSB , psxSH , psxSWL , psxSW , psxNULL, psxNULL, psxSWR , psxNULL, //47
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psxNULL , psxNULL , gteLWC2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, //55
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psxNULL , psxNULL , gteSWC2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL //63
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};
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void(*psxSPC[64])() = {
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psxSLL , psxNULL , psxSRL , psxSRA , psxSLLV , psxNULL , psxSRLV, psxSRAV,
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psxJR , psxJALR , psxNULL, psxNULL, psxSYSCALL, psxBREAK, psxNULL, psxNULL,
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psxMFHI, psxMTHI , psxMFLO, psxMTLO, psxNULL , psxNULL , psxNULL, psxNULL,
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psxMULT, psxMULTU, psxDIV , psxDIVU, psxNULL , psxNULL , psxNULL, psxNULL,
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psxADD , psxADDU , psxSUB , psxSUBU, psxAND , psxOR , psxXOR , psxNOR ,
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psxNULL, psxNULL , psxSLT , psxSLTU, psxNULL , psxNULL , psxNULL, psxNULL,
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psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL,
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psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL
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};
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void(*psxREG[32])() = {
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psxBLTZ , psxBGEZ , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
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psxNULL , psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
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psxBLTZAL, psxBGEZAL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
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psxNULL , psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL
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};
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void(*psxCP0[32])() = {
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psxMFC0, psxNULL, psxCFC0, psxNULL, psxMTC0, psxNULL, psxCTC0, psxNULL,
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psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
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psxRFE , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
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psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL
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};
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void (*psxCP2[64])() = {
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psxBASIC, gteRTPS , psxNULL , psxNULL, psxNULL, psxNULL , gteNCLIP, psxNULL, // 00
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psxNULL , psxNULL , psxNULL , psxNULL, gteOP , psxNULL , psxNULL , psxNULL, // 08
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gteDPCS , gteINTPL, gteMVMVA, gteNCDS, gteCDP , psxNULL , gteNCDT , psxNULL, // 10
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psxNULL , psxNULL , psxNULL , gteNCCS, gteCC , psxNULL , gteNCS , psxNULL, // 18
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gteNCT , psxNULL , psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, // 20
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gteSQR , gteDCPL , gteDPCT , psxNULL, psxNULL, gteAVSZ3, gteAVSZ4, psxNULL, // 28
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gteRTPT , psxNULL , psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, // 30
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psxNULL , psxNULL , psxNULL , psxNULL, psxNULL, gteGPF , gteGPL , gteNCCT // 38
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};
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void(*psxCP2BSC[32])() = {
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gteMFC2, psxNULL, gteCFC2, psxNULL, gteMTC2, psxNULL, gteCTC2, psxNULL,
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psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
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psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
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psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL
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};
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