mirror of https://github.com/PCSX2/pcsx2.git
147 lines
4.0 KiB
C++
147 lines
4.0 KiB
C++
// SPDX-FileCopyrightText: 2002-2023 PCSX2 Dev Team
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// SPDX-License-Identifier: LGPL-3.0+
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#include "Common.h"
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#include "Gif.h"
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#include "Gif_Unit.h"
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#include "MTGS.h"
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#include "Vif.h"
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#include "Vif_Dma.h"
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//////////////////////////////////////////////////////////////////////////
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/////////////////////////// Quick & dirty FIFO :D ////////////////////////
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//////////////////////////////////////////////////////////////////////////
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// Notes on FIFO implementation
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//
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// The FIFO consists of four separate pages of HW register memory, each mapped to a
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// PS2 device. They are listed as follows:
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//
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// 0x4000 - 0x5000 : VIF0 (all registers map to 0x4000)
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// 0x5000 - 0x6000 : VIF1 (all registers map to 0x5000)
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// 0x6000 - 0x7000 : GS (all registers map to 0x6000)
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// 0x7000 - 0x8000 : IPU (registers map to 0x7000 and 0x7010, respectively)
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void ReadFIFO_VIF1(mem128_t* out)
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{
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if (vif1Regs.stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
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DevCon.Warning("Reading from vif1 fifo when stalled");
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ZeroQWC(out); // Clear first in case no data gets written...
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pxAssertRel(vif1Regs.stat.FQC != 0, "FQC = 0 on VIF FIFO READ!");
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if (vif1Regs.stat.FDR)
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{
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if (vif1Regs.stat.FQC > vif1.GSLastDownloadSize)
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{
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DevCon.Warning("Warning! GS Download size < FIFO count!");
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}
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if (vif1Regs.stat.FQC > 0)
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{
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MTGS::InitAndReadFIFO(reinterpret_cast<u8*>(out), 1);
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vif1.GSLastDownloadSize--;
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GUNIT_LOG("ReadFIFO_VIF1");
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if (vif1.GSLastDownloadSize <= 16)
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gifRegs.stat.OPH = false;
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vif1Regs.stat.FQC = std::min((u32)16, vif1.GSLastDownloadSize);
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}
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}
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VIF_LOG("ReadFIFO/VIF1 -> 0x%08X.%08X.%08X.%08X", out->_u32[0], out->_u32[1], out->_u32[2], out->_u32[3]);
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}
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//////////////////////////////////////////////////////////////////////////
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// WriteFIFO Pages
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//
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void WriteFIFO_VIF0(const mem128_t* value)
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{
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VIF_LOG("WriteFIFO/VIF0 <- 0x%08X.%08X.%08X.%08X", value->_u32[0], value->_u32[1], value->_u32[2], value->_u32[3]);
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vif0ch.qwc += 1;
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if (vif0.irqoffset.value != 0 && vif0.vifstalled.enabled)
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DevCon.Warning("Offset on VIF0 FIFO start!");
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[[maybe_unused]] bool ret = VIF0transfer((u32*)value, 4);
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if (vif0.cmd)
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{
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if (vif0.done && vif0ch.qwc == 0)
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vif0Regs.stat.VPS = VPS_WAITING;
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}
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else
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{
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vif0Regs.stat.VPS = VPS_IDLE;
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}
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pxAssertMsg(ret, "vif stall code not implemented");
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}
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void WriteFIFO_VIF1(const mem128_t* value)
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{
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VIF_LOG("WriteFIFO/VIF1 <- 0x%08X.%08X.%08X.%08X", value->_u32[0], value->_u32[1], value->_u32[2], value->_u32[3]);
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if (vif1Regs.stat.FDR)
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{
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DevCon.Warning("writing to fifo when fdr is set!");
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}
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if (vif1Regs.stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
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{
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DevCon.Warning("writing to vif1 fifo when stalled");
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}
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if (vif1.irqoffset.value != 0 && vif1.vifstalled.enabled)
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{
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DevCon.Warning("Offset on VIF1 FIFO start!");
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}
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[[maybe_unused]] bool ret = VIF1transfer((u32*)value, 4);
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if (vif1.cmd)
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{
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if (vif1.done && !vif1ch.qwc)
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vif1Regs.stat.VPS = VPS_WAITING;
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}
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else
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vif1Regs.stat.VPS = VPS_IDLE;
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if (gifRegs.stat.APATH == 2 && gifUnit.gifPath[1].isDone())
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{
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gifRegs.stat.APATH = 0;
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gifRegs.stat.OPH = 0;
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vif1Regs.stat.VGW = false; //Let vif continue if it's stuck on a flush
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if (gifUnit.checkPaths(1, 0, 1))
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gifUnit.Execute(false, true);
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}
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pxAssertMsg(ret, "vif stall code not implemented");
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}
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void WriteFIFO_GIF(const mem128_t* value)
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{
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GUNIT_LOG("WriteFIFO_GIF()");
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if ((!gifUnit.CanDoPath3() || gif_fifo.fifoSize > 0))
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{
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//DevCon.Warning("GIF FIFO HW Write");
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gif_fifo.write_fifo((u32*)value, 1);
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gif_fifo.read_fifo();
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}
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else
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{
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gifUnit.TransferGSPacketData(GIF_TRANS_FIFO, (u8*)value, 16);
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}
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if (gifUnit.gifPath[GIF_PATH_3].state == GIF_PATH_WAIT)
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gifUnit.gifPath[GIF_PATH_3].state = GIF_PATH_IDLE;
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if (gifRegs.stat.APATH == 3)
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{
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gifRegs.stat.APATH = 0;
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gifRegs.stat.OPH = 0;
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if (gifUnit.gifPath[GIF_PATH_3].state == GIF_PATH_IDLE || gifUnit.gifPath[GIF_PATH_3].state == GIF_PATH_WAIT)
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{
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if (gifUnit.checkPaths(1, 1, 0))
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gifUnit.Execute(false, true);
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}
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}
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}
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