mirror of https://github.com/PCSX2/pcsx2.git
1086 lines
34 KiB
C++
1086 lines
34 KiB
C++
// SPDX-FileCopyrightText: 2002-2023 PCSX2 Dev Team
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// SPDX-License-Identifier: LGPL-3.0+
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#include <time.h>
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#include <cmath>
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#include "Common.h"
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#include "R3000A.h"
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#include "Counters.h"
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#include "IopCounters.h"
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#include "GS.h"
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#include "GS/GS.h"
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#include "MTGS.h"
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#include "PerformanceMetrics.h"
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#include "Patch.h"
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#include "ps2/HwInternal.h"
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#include "SIO/Sio.h"
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#include "SPU2/spu2.h"
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#include "Recording/InputRecording.h"
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#include "VMManager.h"
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#include "VUmicro.h"
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extern u8 psxhblankgate;
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static const uint EECNT_FUTURE_TARGET = 0x10000000;
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static int gates = 0;
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uint g_FrameCount = 0;
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// Counter 4 takes care of scanlines - hSync/hBlanks
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// Counter 5 takes care of vSync/vBlanks
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Counter counters[4];
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SyncCounter hsyncCounter;
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SyncCounter vsyncCounter;
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u32 nextsCounter; // records the cpuRegs.cycle value of the last call to rcntUpdate()
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s32 nextCounter; // delta from nextsCounter, in cycles, until the next rcntUpdate()
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// Forward declarations needed because C/C++ both are wimpy single-pass compilers.
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static void rcntStartGate(bool mode, u32 sCycle);
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static void rcntEndGate(bool mode, u32 sCycle);
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static void rcntWcount(int index, u32 value);
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static void rcntWmode(int index, u32 value);
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static void rcntWtarget(int index, u32 value);
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static void rcntWhold(int index, u32 value);
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// For Analog/Double Strike and Interlace modes
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static bool IsInterlacedVideoMode()
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{
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return (gsVideoMode == GS_VideoMode::PAL || gsVideoMode == GS_VideoMode::NTSC || gsVideoMode == GS_VideoMode::DVD_NTSC || gsVideoMode == GS_VideoMode::DVD_PAL || gsVideoMode == GS_VideoMode::HDTV_1080I);
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}
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static bool IsProgressiveVideoMode()
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{
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// The FIELD register only flips if the CMOD field in SMODE1 is set to anything but 0 and Front Porch bottom bit in SYNCV is set.
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// Also see "isReallyInterlaced()" in GSState.cpp
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return !(*(u32*)PS2GS_BASE(GS_SYNCV) & 0x1) || !(*(u32*)PS2GS_BASE(GS_SMODE1) & 0x6000);
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}
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void rcntReset(int index)
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{
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counters[index].count = 0;
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counters[index].sCycleT = cpuRegs.cycle;
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}
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// Updates the state of the nextCounter value (if needed) to serve
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// any pending events for the given counter.
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// Call this method after any modifications to the state of a counter.
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static __fi void _rcntSet(int cntidx)
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{
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s32 c;
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pxAssume(cntidx <= 4); // rcntSet isn't valid for h/vsync counters.
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const Counter& counter = counters[cntidx];
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// Stopped or special hsync gate?
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if (!counter.mode.IsCounting || (counter.mode.ClockSource == 0x3))
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return;
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if (!counter.mode.TargetInterrupt && !counter.mode.OverflowInterrupt)
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return;
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// check for special cases where the overflow or target has just passed
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// (we probably missed it because we're doing/checking other things)
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if (counter.count > 0x10000 || counter.count > counter.target)
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{
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nextCounter = 4;
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return;
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}
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// nextCounter is relative to the cpuRegs.cycle when rcntUpdate() was last called.
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// However, the current _rcntSet could be called at any cycle count, so we need to take
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// that into account. Adding the difference from that cycle count to the current one
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// will do the trick!
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c = ((0x10000 - counter.count) * counter.rate) - (cpuRegs.cycle - counter.sCycleT);
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c += cpuRegs.cycle - nextsCounter; // adjust for time passed since last rcntUpdate();
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if (c < nextCounter)
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{
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nextCounter = c;
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cpuSetNextEvent(nextsCounter, nextCounter); // Need to update on counter resets/target changes
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}
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// Ignore target diff if target is currently disabled.
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// (the overflow is all we care about since it goes first, and then the
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// target will be turned on afterward, and handled in the next event test).
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if (counter.target & EECNT_FUTURE_TARGET)
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{
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return;
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}
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else
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{
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c = ((counter.target - counter.count) * counter.rate) - (cpuRegs.cycle - counter.sCycleT);
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c += cpuRegs.cycle - nextsCounter; // adjust for time passed since last rcntUpdate();
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if (c < nextCounter)
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{
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nextCounter = c;
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cpuSetNextEvent(nextsCounter, nextCounter); // Need to update on counter resets/target changes
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}
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}
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}
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static __fi void cpuRcntSet()
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{
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int i;
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// Default to next VBlank
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nextsCounter = cpuRegs.cycle;
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nextCounter = vsyncCounter.CycleT - (cpuRegs.cycle - vsyncCounter.sCycle);
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// Also check next HSync
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s32 nextHsync = hsyncCounter.CycleT - (cpuRegs.cycle - hsyncCounter.sCycle);
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if (nextHsync < nextCounter)
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nextCounter = nextHsync;
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for (i = 0; i < 4; i++)
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_rcntSet(i);
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// sanity check!
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if (nextCounter < 0)
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nextCounter = 0;
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cpuSetNextEvent(nextsCounter, nextCounter); // Need to update on counter resets/target changes
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}
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struct vSyncTimingInfo
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{
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double Framerate; // frames per second (8 bit fixed)
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GS_VideoMode VideoMode; // used to detect change (interlaced/progressive)
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u32 Render; // time from vblank end to vblank start (cycles)
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u32 Blank; // time from vblank start to vblank end (cycles)
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u32 GSBlank; // GS CSR is swapped roughly 3.5 hblank's after vblank start
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u32 hSyncError; // rounding error after the duration of a rendered frame (cycles)
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u32 hRender; // time from hblank end to hblank start (cycles)
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u32 hBlank; // time from hblank start to hblank end (cycles)
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u32 hScanlinesPerFrame; // number of scanlines per frame (525/625 for NTSC/PAL)
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};
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static vSyncTimingInfo vSyncInfo;
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void rcntInit()
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{
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int i;
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g_FrameCount = 0;
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std::memset(counters, 0, sizeof(counters));
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for (i = 0; i < 4; i++)
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{
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counters[i].rate = 2;
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counters[i].target = 0xffff;
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}
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counters[0].interrupt = 9;
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counters[1].interrupt = 10;
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counters[2].interrupt = 11;
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counters[3].interrupt = 12;
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std::memset(&vSyncInfo, 0, sizeof(vSyncInfo));
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gsVideoMode = GS_VideoMode::Uninitialized;
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gsIsInterlaced = VMManager::Internal::IsFastBootInProgress();
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hsyncCounter.Mode = MODE_HRENDER;
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hsyncCounter.sCycle = cpuRegs.cycle;
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vsyncCounter.CycleT = vSyncInfo.hRender;
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vsyncCounter.Mode = MODE_VRENDER;
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vsyncCounter.CycleT = vSyncInfo.Render;
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vsyncCounter.sCycle = cpuRegs.cycle;
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for (i = 0; i < 4; i++)
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rcntReset(i);
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cpuRcntSet();
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}
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static void vSyncInfoCalc(vSyncTimingInfo* info, double framesPerSecond, u32 scansPerFrame)
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{
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constexpr double clock = static_cast<double>(PS2CLK);
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const u64 Frame = clock * 10000ULL / framesPerSecond;
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const u64 Scanline = Frame / scansPerFrame;
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// There are two renders and blanks per frame. This matches the PS2 test results.
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// The PAL and NTSC VBlank periods respectively lasts for approximately 22 and 26 scanlines.
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// An older test suggests that these periods are actually the periods that VBlank is off, but
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// Legendz Gekitou! Saga Battle runs very slowly if the VBlank period is inverted.
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// Some of the more timing sensitive games and their symptoms when things aren't right:
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// Dynasty Warriors 3 Xtreme Legends - fake save corruption when loading save
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// Jak II - random speedups
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// Shadow of Rome - FMV audio issues
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const bool ntsc_hblank = gsVideoMode != GS_VideoMode::PAL && gsVideoMode != GS_VideoMode::DVD_PAL;
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const u64 HalfFrame = Frame / 2;
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const float extra_scanlines = static_cast<float>(IsProgressiveVideoMode()) * (ntsc_hblank ? 0.5f : 1.5f);
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const u64 Blank = Scanline * ((ntsc_hblank ? 22.5f : 24.5f) + extra_scanlines);
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const u64 Render = HalfFrame - Blank;
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const u64 GSBlank = Scanline * ((ntsc_hblank ? 3.5 : 3) + extra_scanlines); // GS VBlank/CSR Swap happens roughly 3.5(NTSC) and 3(PAL) Scanlines after VBlank Start
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// Important! The hRender/hBlank timers should be 50/50 for best results.
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// (this appears to be what the real EE's timing crystal does anyway)
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u64 hBlank = Scanline / 2;
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u64 hRender = Scanline - hBlank;
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if (!IsInterlacedVideoMode())
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{
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hBlank /= 2;
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hRender /= 2;
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}
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//TODO: Carry fixed-point math all the way through the entire vsync and hsync counting processes, and continually apply rounding
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//as needed for each scheduled v/hsync related event. Much better to handle than this messed state.
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info->Framerate = framesPerSecond;
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info->GSBlank = (u32)(GSBlank / 10000);
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info->Render = (u32)(Render / 10000);
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info->Blank = (u32)(Blank / 10000);
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info->hRender = (u32)(hRender / 10000);
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info->hBlank = (u32)(hBlank / 10000);
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info->hScanlinesPerFrame = scansPerFrame;
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if ((Render % 10000) >= 5000)
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info->Render++;
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if ((Blank % 10000) >= 5000)
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info->Blank++;
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if ((hRender % 10000) >= 5000)
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info->hRender++;
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if ((hBlank % 10000) >= 5000)
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info->hBlank++;
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// Calculate accumulative hSync rounding error per half-frame:
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if (IsInterlacedVideoMode()) // gets off the chart in that mode
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{
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u32 hSyncCycles = ((info->hRender + info->hBlank) * scansPerFrame) / 2;
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u32 vSyncCycles = (info->Render + info->Blank);
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info->hSyncError = vSyncCycles - hSyncCycles;
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//Console.Warning("%d",info->hSyncError);
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}
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else
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info->hSyncError = 0;
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// Note: In NTSC modes there is some small rounding error in the vsync too,
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// however it would take thousands of frames for it to amount to anything and
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// is thus not worth the effort at this time.
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}
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const char* ReportVideoMode()
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{
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switch (gsVideoMode)
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{
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case GS_VideoMode::PAL: return "PAL";
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case GS_VideoMode::NTSC: return "NTSC";
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case GS_VideoMode::DVD_NTSC: return "DVD NTSC";
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case GS_VideoMode::DVD_PAL: return "DVD PAL";
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case GS_VideoMode::VESA: return "VESA";
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case GS_VideoMode::SDTV_480P: return "SDTV 480p";
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case GS_VideoMode::SDTV_576P: return "SDTV 576p";
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case GS_VideoMode::HDTV_720P: return "HDTV 720p";
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case GS_VideoMode::HDTV_1080I: return "HDTV 1080i";
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case GS_VideoMode::HDTV_1080P: return "HDTV 1080p";
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default: return "Unknown";
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}
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}
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const char* ReportInterlaceMode()
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{
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const u64& smode2 = *(u64*)PS2GS_BASE(GS_SMODE2);
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return !IsProgressiveVideoMode() ? ((smode2 & 2) ? "Interlaced (Frame)" : "Interlaced (Field)") : "Progressive";
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}
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double GetVerticalFrequency()
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{
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// Note about NTSC/PAL "double strike" modes:
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// NTSC and PAL can be configured in such a way to produce a non-interlaced signal.
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// This involves modifying the signal slightly by either adding or subtracting a line (526/524 instead of 525)
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// which has the function of causing the odd and even fields to strike the same lines.
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// Doing this modifies the vertical refresh rate slightly. Beatmania is sensitive to this and
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// not accounting for it will cause the audio and video to become desynced.
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//
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// In the case of the GS, I believe it adds a halfline to the vertical back porch but more research is needed.
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// For now I'm just going to subtract off the config setting.
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//
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// According to the GS:
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// NTSC (interlaced): 59.94
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// NTSC (non-interlaced): 59.82
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// PAL (interlaced): 50.00
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// PAL (non-interlaced): 49.76
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//
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// More Information:
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// https://web.archive.org/web/20201031235528/https://wiki.nesdev.com/w/index.php/NTSC_video
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// https://web.archive.org/web/20201102100937/http://forums.nesdev.com/viewtopic.php?t=7909
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// https://web.archive.org/web/20120629231826fw_/http://ntsc-tv.com/index.html
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// https://web.archive.org/web/20200831051302/https://www.hdretrovision.com/240p/
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switch (gsVideoMode)
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{
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case GS_VideoMode::Uninitialized: // SetGsCrt hasn't executed yet, give some temporary values.
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return 60.00;
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case GS_VideoMode::PAL:
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case GS_VideoMode::DVD_PAL:
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return (IsProgressiveVideoMode() == false) ? EmuConfig.GS.FrameratePAL : EmuConfig.GS.FrameratePAL - 0.24f;
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case GS_VideoMode::NTSC:
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case GS_VideoMode::DVD_NTSC:
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return (IsProgressiveVideoMode() == false) ? EmuConfig.GS.FramerateNTSC : EmuConfig.GS.FramerateNTSC - 0.11f;
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case GS_VideoMode::SDTV_480P:
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return 59.94;
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case GS_VideoMode::HDTV_1080P:
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case GS_VideoMode::HDTV_1080I:
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case GS_VideoMode::HDTV_720P:
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case GS_VideoMode::SDTV_576P:
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case GS_VideoMode::VESA:
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return 60.00;
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default:
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// Pass NTSC vertical frequency value when unknown video mode is detected.
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return FRAMERATE_NTSC * 2;
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}
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}
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void UpdateVSyncRate(bool force)
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{
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// Notice: (and I probably repeat this elsewhere, but it's worth repeating)
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// The PS2's vsync timer is an *independent* crystal that is fixed to either 59.94 (NTSC)
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// or 50.0 (PAL) Hz. It has *nothing* to do with real TV timings or the real vsync of
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// the GS's output circuit. It is the same regardless if the GS is outputting interlace
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// or progressive scan content.
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const double vertical_frequency = GetVerticalFrequency();
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const double frames_per_second = vertical_frequency / 2.0;
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if (vSyncInfo.Framerate != frames_per_second || vSyncInfo.VideoMode != gsVideoMode || force)
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{
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u32 total_scanlines = 0;
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bool custom = false;
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switch (gsVideoMode)
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{
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case GS_VideoMode::Uninitialized: // SYSCALL instruction hasn't executed yet, give some temporary values.
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if (gsIsInterlaced)
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total_scanlines = SCANLINES_TOTAL_NTSC_I;
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else
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total_scanlines = SCANLINES_TOTAL_NTSC_NI;
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break;
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case GS_VideoMode::PAL:
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case GS_VideoMode::DVD_PAL:
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custom = (EmuConfig.GS.FrameratePAL != Pcsx2Config::GSOptions::DEFAULT_FRAME_RATE_PAL);
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if (gsIsInterlaced)
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total_scanlines = SCANLINES_TOTAL_PAL_I;
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else
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total_scanlines = SCANLINES_TOTAL_PAL_NI;
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break;
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case GS_VideoMode::NTSC:
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case GS_VideoMode::DVD_NTSC:
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custom = (EmuConfig.GS.FramerateNTSC != Pcsx2Config::GSOptions::DEFAULT_FRAME_RATE_NTSC);
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if (gsIsInterlaced)
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total_scanlines = SCANLINES_TOTAL_NTSC_I;
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else
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total_scanlines = SCANLINES_TOTAL_NTSC_NI;
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break;
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case GS_VideoMode::SDTV_480P:
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case GS_VideoMode::SDTV_576P:
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case GS_VideoMode::HDTV_720P:
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case GS_VideoMode::VESA:
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total_scanlines = SCANLINES_TOTAL_NTSC_I;
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break;
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case GS_VideoMode::HDTV_1080P:
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case GS_VideoMode::HDTV_1080I:
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total_scanlines = SCANLINES_TOTAL_1080;
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break;
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case GS_VideoMode::Unknown:
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default:
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if (gsIsInterlaced)
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total_scanlines = SCANLINES_TOTAL_NTSC_I;
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else
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total_scanlines = SCANLINES_TOTAL_NTSC_NI;
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Console.Error("PCSX2-Counters: Unknown video mode detected");
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pxAssertMsg(false, "Unknown video mode detected via SetGsCrt");
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}
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const bool video_mode_initialized = gsVideoMode != GS_VideoMode::Uninitialized;
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// NBA Jam 2004 PAL will fail to display 3D on the menu if this value isn't correct on reset.
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if (video_mode_initialized && vSyncInfo.VideoMode != gsVideoMode)
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CSRreg.FIELD = 1;
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vSyncInfo.VideoMode = gsVideoMode;
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vSyncInfoCalc(&vSyncInfo, frames_per_second, total_scanlines);
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if (video_mode_initialized)
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Console.WriteLn(Color_Green, "(UpdateVSyncRate) Mode Changed to %s.", ReportVideoMode());
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if (custom && video_mode_initialized)
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Console.WriteLn(Color_StrongGreen, " ... with user configured refresh rate: %.02f Hz", vertical_frequency);
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hsyncCounter.CycleT = (hsyncCounter.Mode == MODE_HBLANK) ? vSyncInfo.hBlank : vSyncInfo.hRender;
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vsyncCounter.CycleT = (vsyncCounter.Mode == MODE_GSBLANK) ?
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vSyncInfo.GSBlank :
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((vsyncCounter.Mode == MODE_VSYNC) ? vSyncInfo.Blank : vSyncInfo.Render);
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cpuRcntSet();
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VMManager::Internal::FrameRateChanged();
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}
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}
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// FMV switch stuff
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extern uint eecount_on_last_vdec;
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extern bool FMVstarted;
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extern bool EnableFMV;
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static bool s_last_fmv_state = false;
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static __fi void DoFMVSwitch()
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{
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bool new_fmv_state = s_last_fmv_state;
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if (EnableFMV)
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{
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DevCon.WriteLn("FMV started");
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new_fmv_state = true;
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EnableFMV = false;
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}
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else if (FMVstarted)
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{
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const int diff = cpuRegs.cycle - eecount_on_last_vdec;
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if (diff > 60000000)
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{
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DevCon.WriteLn("FMV ended");
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new_fmv_state = false;
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FMVstarted = false;
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|
}
|
|
}
|
|
|
|
if (new_fmv_state == s_last_fmv_state)
|
|
return;
|
|
|
|
s_last_fmv_state = new_fmv_state;
|
|
|
|
switch (EmuConfig.GS.FMVAspectRatioSwitch)
|
|
{
|
|
case FMVAspectRatioSwitchType::Off:
|
|
break;
|
|
case FMVAspectRatioSwitchType::RAuto4_3_3_2:
|
|
EmuConfig.CurrentAspectRatio = new_fmv_state ? AspectRatioType::RAuto4_3_3_2 : EmuConfig.GS.AspectRatio;
|
|
break;
|
|
case FMVAspectRatioSwitchType::R4_3:
|
|
EmuConfig.CurrentAspectRatio = new_fmv_state ? AspectRatioType::R4_3 : EmuConfig.GS.AspectRatio;
|
|
break;
|
|
case FMVAspectRatioSwitchType::R16_9:
|
|
EmuConfig.CurrentAspectRatio = new_fmv_state ? AspectRatioType::R16_9 : EmuConfig.GS.AspectRatio;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (EmuConfig.Gamefixes.SoftwareRendererFMVHack && EmuConfig.GS.UseHardwareRenderer())
|
|
{
|
|
DevCon.Warning("FMV Switch");
|
|
// we don't use the sw toggle here, because it'll change back to auto if set to sw
|
|
MTGS::SetSoftwareRendering(new_fmv_state, new_fmv_state ? GSInterlaceMode::AdaptiveTFF : EmuConfig.GS.InterlaceMode, false);
|
|
}
|
|
}
|
|
|
|
static __fi void VSyncStart(u32 sCycle)
|
|
{
|
|
// End-of-frame tasks.
|
|
DoFMVSwitch();
|
|
VMManager::Internal::VSyncOnCPUThread();
|
|
|
|
// Don't bother throttling if we're going to pause.
|
|
if (!VMManager::Internal::IsExecutionInterrupted())
|
|
VMManager::Internal::Throttle();
|
|
|
|
gsPostVsyncStart(); // MUST be after framelimit; doing so before causes funk with frame times!
|
|
|
|
// Poll input after MTGS frame push, just in case it has to stall to catch up.
|
|
VMManager::Internal::PollInputOnCPUThread();
|
|
|
|
if (EmuConfig.Trace.Enabled && EmuConfig.Trace.EE.m_EnableAll)
|
|
SysTrace.EE.Counters.Write(" ================ EE COUNTER VSYNC START (frame: %d) ================", g_FrameCount);
|
|
|
|
hwIntcIrq(INTC_VBLANK_S);
|
|
psxVBlankStart();
|
|
|
|
// Memcard auto ejection - Uses a tick system timed off of real time, decrementing one tick per frame.
|
|
AutoEject::CountDownTicks();
|
|
// Memcard IO detection - Uses a tick system to determine when memcards are no longer being written.
|
|
MemcardBusy::Decrement();
|
|
|
|
if (gates)
|
|
rcntStartGate(true, sCycle); // Counters Start Gate code
|
|
|
|
// INTC - VB Blank Start Hack --
|
|
// Hack fix! This corrects a freezeup in Granda 2 where it decides to spin
|
|
// on the INTC_STAT register after the exception handler has already cleared
|
|
// it. But be warned! Set the value to larger than 4 and it breaks Dark
|
|
// Cloud and other games. -_-
|
|
|
|
// How it works: Normally the INTC raises exceptions immediately at the end of the
|
|
// current branch test. But in the case of Grandia 2, the game's code is spinning
|
|
// on the INTC status, and the exception handler (for some reason?) clears the INTC
|
|
// before returning *and* returns to a location other than EPC. So the game never
|
|
// gets to the point where it sees the INTC Irq set true.
|
|
|
|
// (I haven't investigated why Dark Cloud freezes on larger values)
|
|
// (all testing done using the recompiler -- dunno how the ints respond yet)
|
|
|
|
//cpuRegs.eCycle[30] = 2;
|
|
|
|
// Update 08/2021: The only game I know to require this kind of thing as of 1.7.0 is Penny Racers/Gadget Racers (which has a patch to avoid the problem and others)
|
|
// These games have a tight loop checking INTC_STAT waiting for the VBLANK Start, however the game also has a VBLANK Hander which clears it.
|
|
// Therefore, there needs to be some delay in order for it to see the interrupt flag before the interrupt is acknowledged, likely helped on real hardware by the pipelines.
|
|
// Without the patch and fixing this, the games have other issues, so I'm not going to rush to fix it.
|
|
// Refraction
|
|
|
|
// Bail out before the next frame starts if we're paused, or the CPU has changed.
|
|
// Need to re-check this, because we might've paused during the sleep time.
|
|
if (VMManager::Internal::IsExecutionInterrupted())
|
|
Cpu->ExitExecution();
|
|
}
|
|
|
|
static __fi void GSVSync()
|
|
{
|
|
// CSR is swapped and GS vBlank IRQ is triggered roughly 3.5 hblanks after VSync Start
|
|
|
|
if (IsProgressiveVideoMode())
|
|
CSRreg.SetField();
|
|
else
|
|
CSRreg.SwapField();
|
|
|
|
if (!CSRreg.VSINT)
|
|
{
|
|
CSRreg.VSINT = true;
|
|
if (!GSIMR.VSMSK)
|
|
gsIrq();
|
|
}
|
|
}
|
|
|
|
static __fi void VSyncEnd(u32 sCycle)
|
|
{
|
|
if (EmuConfig.Trace.Enabled && EmuConfig.Trace.EE.m_EnableAll)
|
|
SysTrace.EE.Counters.Write(" ================ EE COUNTER VSYNC END (frame: %d) ================", g_FrameCount);
|
|
|
|
g_FrameCount++;
|
|
|
|
hwIntcIrq(INTC_VBLANK_E); // HW Irq
|
|
psxVBlankEnd(); // psxCounters vBlank End
|
|
if (gates)
|
|
rcntEndGate(true, sCycle); // Counters End Gate Code
|
|
|
|
// FolderMemoryCard needs information on how much time has passed since the last write
|
|
// Call it every 60 frames
|
|
if (!(g_FrameCount % 60))
|
|
sioNextFrame();
|
|
|
|
// This doesn't seem to be needed here. Games only seem to break with regard to the
|
|
// vsyncstart irq.
|
|
//cpuRegs.eCycle[30] = 2;
|
|
}
|
|
|
|
//#define VSYNC_DEBUG // Uncomment this to enable some vSync Timer debugging features.
|
|
#ifdef VSYNC_DEBUG
|
|
static u32 hsc = 0;
|
|
static int vblankinc = 0;
|
|
#endif
|
|
|
|
__fi void rcntUpdate_hScanline()
|
|
{
|
|
if (!cpuTestCycle(hsyncCounter.sCycle, hsyncCounter.CycleT))
|
|
return;
|
|
|
|
//iopEventAction = 1;
|
|
if (hsyncCounter.Mode == MODE_HBLANK)
|
|
{ //HBLANK Start
|
|
// Setup the hRender's start and end cycle information:
|
|
hsyncCounter.sCycle += vSyncInfo.hBlank; // start (absolute cycle value)
|
|
hsyncCounter.CycleT = vSyncInfo.hRender; // endpoint (delta from start value)
|
|
hsyncCounter.Mode = MODE_HRENDER;
|
|
|
|
rcntStartGate(false, hsyncCounter.sCycle);
|
|
psxCheckStartGate16(0);
|
|
}
|
|
else
|
|
{ //HBLANK END / HRENDER Begin
|
|
if (!CSRreg.HSINT)
|
|
{
|
|
CSRreg.HSINT = true;
|
|
if (!GSIMR.HSMSK)
|
|
gsIrq();
|
|
}
|
|
|
|
// set up the hblank's start and end cycle information:
|
|
hsyncCounter.sCycle += vSyncInfo.hRender; // start (absolute cycle value)
|
|
hsyncCounter.CycleT = vSyncInfo.hBlank; // endpoint (delta from start value)
|
|
hsyncCounter.Mode = MODE_HBLANK;
|
|
|
|
if (gates)
|
|
rcntEndGate(false, hsyncCounter.sCycle);
|
|
if (psxhblankgate)
|
|
psxCheckEndGate16(0);
|
|
|
|
#ifdef VSYNC_DEBUG
|
|
hsc++;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
__fi void rcntUpdate_vSync()
|
|
{
|
|
if (!cpuTestCycle(vsyncCounter.sCycle, vsyncCounter.CycleT))
|
|
return;
|
|
|
|
if (vsyncCounter.Mode == MODE_VSYNC)
|
|
{
|
|
vsyncCounter.sCycle += vSyncInfo.Blank;
|
|
vsyncCounter.CycleT = vSyncInfo.Render;
|
|
vsyncCounter.Mode = MODE_VRENDER;
|
|
|
|
VSyncEnd(vsyncCounter.sCycle);
|
|
}
|
|
else if (vsyncCounter.Mode == MODE_GSBLANK) // GS CSR Swap and interrupt
|
|
{
|
|
GSVSync();
|
|
|
|
vsyncCounter.Mode = MODE_VSYNC;
|
|
// Don't set the start cycle, makes it easier to calculate the correct Vsync End time
|
|
vsyncCounter.CycleT = vSyncInfo.Blank;
|
|
}
|
|
else // VSYNC end / VRENDER begin
|
|
{
|
|
vsyncCounter.sCycle += vSyncInfo.Render;
|
|
vsyncCounter.CycleT = vSyncInfo.GSBlank;
|
|
vsyncCounter.Mode = MODE_GSBLANK;
|
|
|
|
// Accumulate hsync rounding errors:
|
|
hsyncCounter.sCycle += vSyncInfo.hSyncError;
|
|
|
|
VSyncStart(vsyncCounter.sCycle);
|
|
|
|
#ifdef VSYNC_DEBUG
|
|
vblankinc++;
|
|
if (vblankinc > 1)
|
|
{
|
|
if (hsc != vSyncInfo.hScanlinesPerFrame)
|
|
Console.WriteLn(" ** vSync > Abnormal Scanline Count: %d", hsc);
|
|
hsc = 0;
|
|
vblankinc = 0;
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
|
|
static __fi void _cpuTestTarget(int i)
|
|
{
|
|
if (counters[i].count < counters[i].target)
|
|
return;
|
|
|
|
if (counters[i].mode.TargetInterrupt)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] TARGET reached - mode=%x, count=%x, target=%x", i, counters[i].mode, counters[i].count, counters[i].target);
|
|
if (!counters[i].mode.TargetReached)
|
|
{
|
|
counters[i].mode.TargetReached = 1;
|
|
hwIntcIrq(counters[i].interrupt);
|
|
}
|
|
}
|
|
|
|
if (counters[i].mode.ZeroReturn)
|
|
counters[i].count -= counters[i].target; // Reset on target
|
|
else
|
|
counters[i].target |= EECNT_FUTURE_TARGET; // OR with future target to prevent a retrigger
|
|
}
|
|
|
|
static __fi void _cpuTestOverflow(int i)
|
|
{
|
|
if (counters[i].count <= 0xffff)
|
|
return;
|
|
|
|
if (counters[i].mode.OverflowInterrupt)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] OVERFLOW - mode=%x, count=%x", i, counters[i].mode, counters[i].count);
|
|
if (!counters[i].mode.OverflowReached)
|
|
{
|
|
counters[i].mode.OverflowReached = 1;
|
|
hwIntcIrq(counters[i].interrupt);
|
|
}
|
|
}
|
|
|
|
// wrap counter back around zero, and enable the future target:
|
|
counters[i].count -= 0x10000;
|
|
counters[i].target &= 0xffff;
|
|
}
|
|
|
|
|
|
// forceinline note: this method is called from two locations, but one
|
|
// of them is the interpreter, which doesn't count. ;) So might as
|
|
// well forceinline it!
|
|
__fi void rcntUpdate()
|
|
{
|
|
rcntUpdate_vSync();
|
|
// HBlank after as VSync can do error compensation
|
|
rcntUpdate_hScanline();
|
|
|
|
// Update counters so that we can perform overflow and target tests.
|
|
|
|
for (int i = 0; i <= 3; i++)
|
|
{
|
|
// We want to count gated counters (except the hblank which exclude below, and are
|
|
// counted by the hblank timer instead)
|
|
|
|
//if ( gates & (1<<i) ) continue;
|
|
|
|
if (!counters[i].mode.IsCounting)
|
|
continue;
|
|
|
|
if (counters[i].mode.ClockSource != 0x3) // don't count hblank sources
|
|
{
|
|
const u32 change = (cpuRegs.cycle - counters[i].sCycleT) / counters[i].rate;
|
|
counters[i].count += change;
|
|
counters[i].sCycleT += change * counters[i].rate;
|
|
|
|
// Check Counter Targets and Overflows:
|
|
// Check Overflow first, in case the target is 0
|
|
_cpuTestOverflow(i);
|
|
_cpuTestTarget(i);
|
|
}
|
|
else
|
|
counters[i].sCycleT = cpuRegs.cycle;
|
|
}
|
|
|
|
cpuRcntSet();
|
|
}
|
|
|
|
static __fi void _rcntSetGate(int index)
|
|
{
|
|
if (counters[index].mode.EnableGate)
|
|
{
|
|
// If the Gate Source is hblank and the clock selection is also hblank
|
|
// then the gate is disabled and the counter acts as a normal hblank source.
|
|
|
|
if (!(counters[index].mode.GateSource == 0 && counters[index].mode.ClockSource == 3))
|
|
{
|
|
EECNT_LOG("EE Counter[%d] Using Gate! Source=%s, Mode=%d.",
|
|
index, counters[index].mode.GateSource ? "vblank" : "hblank", counters[index].mode.GateMode);
|
|
|
|
gates |= (1 << index);
|
|
counters[index].mode.IsCounting = 0;
|
|
rcntReset(index);
|
|
return;
|
|
}
|
|
else
|
|
EECNT_LOG("EE Counter[%d] GATE DISABLED because of hblank source.", index);
|
|
}
|
|
|
|
gates &= ~(1 << index);
|
|
}
|
|
|
|
// mode - 0 means hblank source, 8 means vblank source.
|
|
static __fi void rcntStartGate(bool isVblank, u32 sCycle)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i <= 3; i++)
|
|
{
|
|
//if ((mode == 0) && ((counters[i].mode & 0x83) == 0x83))
|
|
if (!isVblank && counters[i].mode.IsCounting && (counters[i].mode.ClockSource == 3))
|
|
{
|
|
// Update counters using the hblank as the clock. This keeps the hblank source
|
|
// nicely in sync with the counters and serves as an optimization also, since these
|
|
// counter won't receive special rcntUpdate scheduling.
|
|
|
|
// Note: Target and overflow tests must be done here since they won't be done
|
|
// currectly by rcntUpdate (since it's not being scheduled for these counters)
|
|
|
|
counters[i].count += HBLANK_COUNTER_SPEED;
|
|
_cpuTestOverflow(i);
|
|
_cpuTestTarget(i);
|
|
}
|
|
|
|
if (!(gates & (1 << i)))
|
|
continue;
|
|
if ((!!counters[i].mode.GateSource) != isVblank)
|
|
continue;
|
|
|
|
switch (counters[i].mode.GateMode)
|
|
{
|
|
case 0x0: //Count When Signal is low (off)
|
|
|
|
// Just set the start cycle (sCycleT) -- counting will be done as needed
|
|
// for events (overflows, targets, mode changes, and the gate off below)
|
|
|
|
counters[i].count = rcntRcount(i);
|
|
counters[i].mode.IsCounting = 0;
|
|
counters[i].sCycleT = sCycle;
|
|
EECNT_LOG("EE Counter[%d] %s StartGate Type0, count = %x", i,
|
|
isVblank ? "vblank" : "hblank", counters[i].count);
|
|
break;
|
|
|
|
case 0x2: // reset and start counting on vsync end
|
|
// this is the vsync start so do nothing.
|
|
break;
|
|
|
|
case 0x1: //Reset and start counting on Vsync start
|
|
case 0x3: //Reset and start counting on Vsync start and end
|
|
counters[i].mode.IsCounting = 1;
|
|
counters[i].count = 0;
|
|
counters[i].target &= 0xffff;
|
|
counters[i].sCycleT = sCycle;
|
|
EECNT_LOG("EE Counter[%d] %s StartGate Type%d, count = %x", i,
|
|
isVblank ? "vblank" : "hblank", counters[i].mode.GateMode, counters[i].count);
|
|
break;
|
|
}
|
|
}
|
|
|
|
// No need to update actual counts here. Counts are calculated as needed by reads to
|
|
// rcntRcount(). And so long as sCycleT is set properly, any targets or overflows
|
|
// will be scheduled and handled.
|
|
|
|
// Note: No need to set counters here. They'll get set when control returns to
|
|
// rcntUpdate, since we're being called from there anyway.
|
|
}
|
|
|
|
// mode - 0 means hblank signal, 8 means vblank signal.
|
|
static __fi void rcntEndGate(bool isVblank, u32 sCycle)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i <= 3; i++)
|
|
{ //Gates for counters
|
|
if (!(gates & (1 << i)))
|
|
continue;
|
|
if ((!!counters[i].mode.GateSource) != isVblank)
|
|
continue;
|
|
|
|
switch (counters[i].mode.GateMode)
|
|
{
|
|
case 0x0: //Count When Signal is low (off)
|
|
|
|
// Set the count here. Since the timer is being turned off it's
|
|
// important to record its count at this point (it won't be counted by
|
|
// calls to rcntUpdate).
|
|
counters[i].mode.IsCounting = 1;
|
|
counters[i].sCycleT = cpuRegs.cycle;
|
|
|
|
EECNT_LOG("EE Counter[%d] %s EndGate Type0, count = %x", i,
|
|
isVblank ? "vblank" : "hblank", counters[i].count);
|
|
break;
|
|
|
|
case 0x1: // Reset and start counting on Vsync start
|
|
// this is the vsync end so do nothing
|
|
break;
|
|
|
|
case 0x2: //Reset and start counting on Vsync end
|
|
case 0x3: //Reset and start counting on Vsync start and end
|
|
counters[i].mode.IsCounting = 1;
|
|
counters[i].count = 0;
|
|
counters[i].target &= 0xffff;
|
|
counters[i].sCycleT = sCycle;
|
|
EECNT_LOG("EE Counter[%d] %s EndGate Type%d, count = %x", i,
|
|
isVblank ? "vblank" : "hblank", counters[i].mode.GateMode, counters[i].count);
|
|
break;
|
|
}
|
|
}
|
|
// Note: No need to set counters here. They'll get set when control returns to
|
|
// rcntUpdate, since we're being called from there anyway.
|
|
}
|
|
|
|
static __fi void rcntWmode(int index, u32 value)
|
|
{
|
|
if (counters[index].mode.IsCounting)
|
|
{
|
|
if (counters[index].mode.ClockSource != 0x3)
|
|
{
|
|
const u32 change = (cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate;
|
|
counters[index].count += change;
|
|
counters[index].sCycleT += change * counters[index].rate;
|
|
}
|
|
}
|
|
else
|
|
counters[index].sCycleT = cpuRegs.cycle;
|
|
|
|
// Clear OverflowReached and TargetReached flags (0xc00 mask), but *only* if they are set to 1 in the
|
|
// given value. (yes, the bits are cleared when written with '1's).
|
|
|
|
counters[index].modeval &= ~(value & 0xc00);
|
|
counters[index].modeval = (counters[index].modeval & 0xc00) | (value & 0x3ff);
|
|
EECNT_LOG("EE Counter[%d] writeMode = %x passed value=%x", index, counters[index].modeval, value);
|
|
|
|
switch (counters[index].mode.ClockSource) { //Clock rate divisers *2, they use BUSCLK speed not PS2CLK
|
|
case 0: counters[index].rate = 2; break;
|
|
case 1: counters[index].rate = 32; break;
|
|
case 2: counters[index].rate = 512; break;
|
|
case 3: counters[index].rate = vSyncInfo.hBlank+vSyncInfo.hRender; break;
|
|
}
|
|
|
|
_rcntSetGate(index);
|
|
_rcntSet(index);
|
|
}
|
|
|
|
static __fi void rcntWcount(int index, u32 value)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] writeCount = %x, oldcount=%x, target=%x", index, value, counters[index].count, counters[index].target);
|
|
|
|
// re-calculate the start cycle of the counter based on elapsed time since the last counter update:
|
|
if (counters[index].mode.IsCounting)
|
|
{
|
|
if (counters[index].mode.ClockSource != 0x3)
|
|
{
|
|
const u32 change = (cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate;
|
|
counters[index].sCycleT += change * counters[index].rate;
|
|
}
|
|
}
|
|
else
|
|
counters[index].sCycleT = cpuRegs.cycle;
|
|
|
|
counters[index].count = value & 0xffff;
|
|
|
|
// reset the target, and make sure we don't get a premature target.
|
|
counters[index].target &= 0xffff;
|
|
|
|
if (counters[index].count > counters[index].target)
|
|
counters[index].target |= EECNT_FUTURE_TARGET;
|
|
|
|
_rcntSet(index);
|
|
}
|
|
|
|
static __fi void rcntWtarget(int index, u32 value)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] writeTarget = %x", index, value);
|
|
|
|
counters[index].target = value & 0xffff;
|
|
|
|
// guard against premature (instant) targeting.
|
|
// If the target is behind the current count, set it up so that the counter must
|
|
// overflow first before the target fires:
|
|
|
|
if (counters[index].mode.IsCounting)
|
|
{
|
|
if (counters[index].mode.ClockSource != 0x3)
|
|
{
|
|
const u32 change = (cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate;
|
|
counters[index].count += change;
|
|
counters[index].sCycleT += change * counters[index].rate;
|
|
}
|
|
}
|
|
|
|
if (counters[index].target <= counters[index].count)
|
|
counters[index].target |= EECNT_FUTURE_TARGET;
|
|
|
|
_rcntSet(index);
|
|
}
|
|
|
|
static __fi void rcntWhold(int index, u32 value)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] Hold Write = %x", index, value);
|
|
counters[index].hold = value;
|
|
}
|
|
|
|
__fi u32 rcntRcount(int index)
|
|
{
|
|
u32 ret;
|
|
|
|
// only count if the counter is turned on (0x80) and is not an hsync gate (!0x03)
|
|
if (counters[index].mode.IsCounting && (counters[index].mode.ClockSource != 0x3))
|
|
ret = counters[index].count + ((cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate);
|
|
else
|
|
ret = counters[index].count;
|
|
|
|
// Spams the Console.
|
|
EECNT_LOG("EE Counter[%d] readCount32 = %x", index, ret);
|
|
return ret;
|
|
}
|
|
|
|
template <uint page>
|
|
__fi u16 rcntRead32(u32 mem)
|
|
{
|
|
// Important DevNote:
|
|
// Yes this uses a u16 return value on purpose! The upper bits 16 of the counter registers
|
|
// are all fixed to 0, so we always truncate everything in these two pages using a u16
|
|
// return value! --air
|
|
|
|
switch( mem ) {
|
|
case(RCNT0_COUNT): return (u16)rcntRcount(0);
|
|
case(RCNT0_MODE): return (u16)counters[0].modeval;
|
|
case(RCNT0_TARGET): return (u16)counters[0].target;
|
|
case(RCNT0_HOLD): return (u16)counters[0].hold;
|
|
|
|
case(RCNT1_COUNT): return (u16)rcntRcount(1);
|
|
case(RCNT1_MODE): return (u16)counters[1].modeval;
|
|
case(RCNT1_TARGET): return (u16)counters[1].target;
|
|
case(RCNT1_HOLD): return (u16)counters[1].hold;
|
|
|
|
case(RCNT2_COUNT): return (u16)rcntRcount(2);
|
|
case(RCNT2_MODE): return (u16)counters[2].modeval;
|
|
case(RCNT2_TARGET): return (u16)counters[2].target;
|
|
|
|
case(RCNT3_COUNT): return (u16)rcntRcount(3);
|
|
case(RCNT3_MODE): return (u16)counters[3].modeval;
|
|
case(RCNT3_TARGET): return (u16)counters[3].target;
|
|
}
|
|
|
|
return psHu16(mem);
|
|
}
|
|
|
|
template <uint page>
|
|
__fi bool rcntWrite32(u32 mem, mem32_t& value)
|
|
{
|
|
pxAssume(mem >= RCNT0_COUNT && mem < 0x10002000);
|
|
|
|
// [TODO] : counters should actually just use the EE's hw register space for storing
|
|
// count, mode, target, and hold. This will allow for a simplified handler for register
|
|
// reads.
|
|
|
|
switch( mem ) {
|
|
case(RCNT0_COUNT): return rcntWcount(0, value), false;
|
|
case(RCNT0_MODE): return rcntWmode(0, value), false;
|
|
case(RCNT0_TARGET): return rcntWtarget(0, value), false;
|
|
case(RCNT0_HOLD): return rcntWhold(0, value), false;
|
|
|
|
case(RCNT1_COUNT): return rcntWcount(1, value), false;
|
|
case(RCNT1_MODE): return rcntWmode(1, value), false;
|
|
case(RCNT1_TARGET): return rcntWtarget(1, value), false;
|
|
case(RCNT1_HOLD): return rcntWhold(1, value), false;
|
|
|
|
case(RCNT2_COUNT): return rcntWcount(2, value), false;
|
|
case(RCNT2_MODE): return rcntWmode(2, value), false;
|
|
case(RCNT2_TARGET): return rcntWtarget(2, value), false;
|
|
|
|
case(RCNT3_COUNT): return rcntWcount(3, value), false;
|
|
case(RCNT3_MODE): return rcntWmode(3, value), false;
|
|
case(RCNT3_TARGET): return rcntWtarget(3, value), false;
|
|
}
|
|
|
|
// unhandled .. do memory writeback.
|
|
return true;
|
|
}
|
|
|
|
template u16 rcntRead32<0x00>(u32 mem);
|
|
template u16 rcntRead32<0x01>(u32 mem);
|
|
|
|
template bool rcntWrite32<0x00>(u32 mem, mem32_t& value);
|
|
template bool rcntWrite32<0x01>(u32 mem, mem32_t& value);
|
|
|
|
bool SaveStateBase::rcntFreeze()
|
|
{
|
|
Freeze(counters);
|
|
Freeze(hsyncCounter);
|
|
Freeze(vsyncCounter);
|
|
Freeze(nextCounter);
|
|
Freeze(nextsCounter);
|
|
Freeze(vSyncInfo);
|
|
Freeze(gsVideoMode);
|
|
Freeze(gsIsInterlaced);
|
|
Freeze(gates);
|
|
|
|
if (IsLoading())
|
|
cpuRcntSet();
|
|
|
|
return IsOkay();
|
|
}
|