mirror of https://github.com/PCSX2/pcsx2.git
555 lines
12 KiB
C
555 lines
12 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#include "VU0.h"
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#ifdef __WIN32__
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#pragma warning(disable:4244)
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#pragma warning(disable:4761)
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#endif
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/*********************************************************
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* Load and store for GPR *
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* Format: OP rt, offset(base) *
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*********************************************************/
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#ifndef LOADSTORE_RECOMPILE
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REC_FUNC(LB);
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REC_FUNC(LBU);
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REC_FUNC(LH);
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REC_FUNC(LHU);
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REC_FUNC(LW);
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REC_FUNC(LWU);
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REC_FUNC(LWL);
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REC_FUNC(LWR);
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REC_FUNC(LD);
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REC_FUNC(LDR);
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REC_FUNC(LDL);
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REC_FUNC(LQ);
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REC_FUNC(SB);
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REC_FUNC(SH);
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REC_FUNC(SW);
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REC_FUNC(SWL);
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REC_FUNC(SWR);
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REC_FUNC(SD);
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REC_FUNC(SDL);
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REC_FUNC(SDR);
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REC_FUNC(SQ);
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REC_FUNC(LWC1);
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REC_FUNC(SWC1);
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REC_FUNC(LQC2);
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REC_FUNC(SQC2);
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#else
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REC_FUNC(LWC1);
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REC_FUNC(SWC1);
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REC_FUNC(LQC2);
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REC_FUNC(SQC2);
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u64 retValue;
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u64 dummyValue[ 4 ];
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////////////////////////////////////////////////////
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void recLB( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 ) {
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ADD32ItoR( EDI, _Imm_ );
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}
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if ( _Rt_ ) {
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MOV32ItoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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} else {
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MOV32ItoR( ESI, &dummyValue );
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}
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CALLFunc( (u32)memRead8RS );
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}
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////////////////////////////////////////////////////
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void recLBU( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EDI, _Imm_ );
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}
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if ( _Rt_ ) {
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MOV32ItoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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} else {
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MOV32ItoR( ESI, &dummyValue );
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}
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iFlushCall();
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CALLFunc( (u32)memRead8RU );
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}
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////////////////////////////////////////////////////
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void recLH( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EDI, _Imm_ );
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}
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if ( _Rt_ ) {
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MOV32ItoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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} else {
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MOV32ItoR( ESI, &dummyValue );
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}
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iFlushCall();
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CALLFunc( (u32)memRead16RS );
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}
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////////////////////////////////////////////////////
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void recLHU( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 ) {
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ADD32ItoR( EDI, _Imm_ );
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}
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if ( _Rt_ ) {
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MOV32ItoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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} else {
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MOV32ItoR( ESI, &dummyValue );
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}
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CALLFunc( (u32)memRead16RU );
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}
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void tests() {
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SysPrintf("Err\n");
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}
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////////////////////////////////////////////////////
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void recLW( void ) {
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int rsreg;
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int rtreg;
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int t0reg;
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int t1reg;
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int t2reg;
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#if 0
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//def ENABLE_REGCACHING
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_freeX86regs();
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_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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t0reg = _allocTempX86reg(-1);
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t1reg = _allocTempX86reg(-1);
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t2reg = _allocTempX86reg(-1);
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MOV32RtoR(t0reg, rsreg);
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if (_Imm_ != 0) {
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ADD32ItoR(t0reg, _Imm_);
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}
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MOV32RtoR(t2reg, t0reg);
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SHR32ItoR(t0reg, 12);
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MOV64MtoR(t1reg, (u32)&memLUTR);
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MOV64RmStoR(t1reg, t1reg, t0reg, 3);
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CMP64ItoR(t1reg, 0x10);
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j8Ptr[0] = JL8(0);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_WRITE);
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AND32ItoR(t2reg, 0xfff);
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LogX86();
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MOV64RmStoR(rtreg, t1reg, t2reg, 0);
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_clearNeededX86regs();
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_freeX86regs();
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// j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 ) {
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ADD32ItoR( EDI, _Imm_ );
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}
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if ( _Rt_ ) {
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MOV32ItoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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} else {
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MOV32ItoR( ESI, &dummyValue );
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}
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CALLFunc( (u32)memRead32RS );
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// x86SetJ8(j8Ptr[1]);
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#else
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 ) {
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ADD32ItoR( EDI, _Imm_ );
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}
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if ( _Rt_ ) {
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MOV32ItoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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} else {
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MOV32ItoR( ESI, &dummyValue );
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}
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CALLFunc( (u32)memRead32RS );
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#endif
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}
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////////////////////////////////////////////////////
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void recLWU( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EDI, _Imm_ );
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}
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if ( _Rt_ ) {
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MOV32ItoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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} else {
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MOV32ItoR( ESI, &dummyValue );
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}
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CALLFunc( (u32)memRead32RU );
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}
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////////////////////////////////////////////////////
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void recLWL( void )
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{
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iFlushCall();
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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CALLFunc( (u32)LWL );
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}
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////////////////////////////////////////////////////
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void recLWR( void ) {
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iFlushCall();
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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CALLFunc( (u32)LWR );
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}
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////////////////////////////////////////////////////
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void recLD( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EDI, _Imm_ );
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}
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if ( _Rt_ )
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{
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MOV32ItoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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}
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else
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{
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MOV32ItoR( ESI, &dummyValue );
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}
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CALLFunc( (u32)memRead64 );
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}
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////////////////////////////////////////////////////
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void recLDL( void ) {
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iFlushCall();
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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CALLFunc( (u32)LDL );
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}
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////////////////////////////////////////////////////
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void recLDR( void ) {
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iFlushCall();
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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CALLFunc( (u32)LDR );
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}
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////////////////////////////////////////////////////
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void recLQ( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EDI, _Imm_);
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}
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AND32ItoR( EDI, ~0xf );
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if ( _Rt_ ) {
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MOV32ItoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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} else {
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MOV32ItoR( ESI, &dummyValue );
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}
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CALLFunc( (u32)memRead128 );
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}
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////////////////////////////////////////////////////
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void recSB( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EDI, _Imm_);
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}
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MOV32MtoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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CALLFunc( (u32)memWrite8 );
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}
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////////////////////////////////////////////////////
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void recSH( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EDI, _Imm_ );
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}
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MOV32MtoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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CALLFunc( (u32)memWrite16 );
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}
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////////////////////////////////////////////////////
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void recSW( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EDI, _Imm_ );
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}
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MOV32MtoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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CALLFunc( (u32)memWrite32 );
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}
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////////////////////////////////////////////////////
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void recSWL( void ) {
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iFlushCall();
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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CALLFunc( (u32)SWL );
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}
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////////////////////////////////////////////////////
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void recSWR( void ) {
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iFlushCall();
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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CALLFunc( (u32)SWR );
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}
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////////////////////////////////////////////////////
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void recSD( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EDI, _Imm_ );
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}
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MOV64MtoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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CALLFunc( (u32)memWrite64 );
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}
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////////////////////////////////////////////////////
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void recSDL( void ) {
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iFlushCall();
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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CALLFunc( (u32)SDL );
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}
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////////////////////////////////////////////////////
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void recSDR( void ) {
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iFlushCall();
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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CALLFunc( (u32)SDR );
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}
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////////////////////////////////////////////////////
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void recSQ( void ) {
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iFlushCall();
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MOV32MtoR( EDI, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EDI, _Imm_ );
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}
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AND32ItoR( EDI, ~0xf );
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MOV32ItoR( ESI, &cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ] );
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CALLFunc( (u32)memWrite128 );
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}
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/*********************************************************
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* Load and store for COP1 *
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* Format: OP rt, offset(base) *
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*********************************************************/
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/*
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////////////////////////////////////////////////////
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void recLWC1( void )
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{
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if ( Config.Regcaching )
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{
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GRec_Instruction( GREC_INST_MOVIMM32, &cpuRegs.code, cpuRegs.code );
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GRec_Instruction( GREC_INST_MOVIMM32, &cpuRegs.pc, pc );
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GRec_Instruction( GREC_INST_CALL, LWC1, NULL, 0, GREC_TRUE );
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}
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else
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{
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if ( Config.Regcaching )
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{
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GRecReleaseAll( );
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}
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MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EAX, _Imm_ );
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}
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PUSH32I( (u32)&fpuRegs.fpr[ _Rt_ ].UL );
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PUSH32R( EAX );
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iFlushCall();
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CALLFunc( (u32)memRead32 );
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ADD32ItoR( ESP, 8 );
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}
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}
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////////////////////////////////////////////////////
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void recSWC1( void )
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{
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if ( Config.Regcaching )
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{
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GRec_Instruction( GREC_INST_MOVIMM32, &cpuRegs.code, cpuRegs.code );
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GRec_Instruction( GREC_INST_MOVIMM32, &cpuRegs.pc, pc );
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GRec_Instruction( GREC_INST_CALL, SWC1, NULL, 0, GREC_TRUE );
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}
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else
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{
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if ( Config.Regcaching )
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{
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GRecReleaseAll( );
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}
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MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EAX, _Imm_ );
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}
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PUSH32M( (u32)&fpuRegs.fpr[ _Rt_ ].UL );
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PUSH32R( EAX );
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iFlushCall();
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CALLFunc( (u32)memWrite32 );
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ADD32ItoR( ESP, 8 );
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}
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}
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////////////////////////////////////////////////////
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#define _Ft_ _Rt_
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#define _Fs_ _Rd_
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#define _Fd_ _Sa_
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void recLQC2( void )
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{
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if ( Config.Regcaching && ConfigNewRec )
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{
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GRecAssert( GREC_FALSE, "LQC2 not implemented" );
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}
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else
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{
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if ( Config.Regcaching )
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{
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GRecReleaseAll( );
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}
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MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EAX, _Imm_);
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}
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if ( _Rt_ )
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{
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PUSH32I( (u32)&VU0.VF[_Ft_].UD[0] );
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}
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else
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{
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PUSH32I( (u32)&dummyValue );
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}
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PUSH32R( EAX );
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iFlushCall();
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CALLFunc( (u32)memRead128 );
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ADD32ItoR( ESP, 8 );
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}
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}
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////////////////////////////////////////////////////
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void recSQC2( void )
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{
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if ( Config.Regcaching )
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{
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GRecAssert( GREC_FALSE, "SQC2 not implemented" );
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}
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else
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{
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if ( Config.Regcaching )
|
|
{
|
|
GRecReleaseAll( );
|
|
}
|
|
|
|
MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
if ( _Imm_ != 0 )
|
|
{
|
|
ADD32ItoR( EAX, _Imm_ );
|
|
}
|
|
|
|
PUSH32I( (u32)&VU0.VF[_Ft_].UD[0] );
|
|
PUSH32R( EAX );
|
|
iFlushCall();
|
|
CALLFunc( (u32)memWrite128 );
|
|
ADD32ItoR( ESP, 8 );
|
|
}
|
|
}
|
|
*/
|
|
#endif
|