mirror of https://github.com/PCSX2/pcsx2.git
543 lines
13 KiB
C
543 lines
13 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#ifdef __WIN32__
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#pragma warning(disable:4244)
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#pragma warning(disable:4761)
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#endif
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/*********************************************************
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* Register arithmetic *
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* Format: OP rd, rs, rt *
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*********************************************************/
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#ifndef ARITHMETIC_RECOMPILE
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REC_FUNC(ADD);
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REC_FUNC(ADDU);
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REC_FUNC(DADD);
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REC_FUNC(DADDU);
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REC_FUNC(SUB);
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REC_FUNC(SUBU);
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REC_FUNC(DSUB);
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REC_FUNC(DSUBU);
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REC_FUNC(AND);
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REC_FUNC(OR);
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REC_FUNC(XOR);
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REC_FUNC(NOR);
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REC_FUNC(SLT);
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REC_FUNC(SLTU);
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#else
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////////////////////////////////////////////////////
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void recADD( void ) {
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int rdreg;
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int rsreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rs_) {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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ADD32RtoR(rdreg, rtreg);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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} else
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if (_Rd_ == _Rt_) {
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_addNeededGPRtoX86reg(_Rs_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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ADD32RtoR(rdreg, rsreg);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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} else {
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_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV32RtoR(rdreg, rsreg);
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ADD32RtoR(rdreg, rtreg);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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}
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_clearNeededX86regs();
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#else
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MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if (_Rt_ != 0) {
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ADD32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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}
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CDQ( );
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MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
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#endif
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}
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////////////////////////////////////////////////////
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void recADDU( void )
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{
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recADD( );
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}
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////////////////////////////////////////////////////
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void recDADD( void ) {
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int rdreg;
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int rsreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rs_) {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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ADD64RtoR(rdreg, rtreg);
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} else
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if (_Rd_ == _Rt_) {
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_addNeededGPRtoX86reg(_Rs_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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ADD64RtoR(rdreg, rsreg);
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} else {
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_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rsreg);
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ADD64RtoR(rdreg, rtreg);
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}
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_clearNeededX86regs();
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#else
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MOV64MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Rt_ != 0 ) {
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ADD64MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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}
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MOV64RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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#endif
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}
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////////////////////////////////////////////////////
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void recDADDU( void )
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{
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recDADD( );
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}
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////////////////////////////////////////////////////
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void recSUB( void ) {
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int rdreg;
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int rsreg;
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int rtreg;
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int t0reg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rs_) {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SUB32RtoR(rdreg, rtreg);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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} else
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if (_Rd_ == _Rt_) {
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_addNeededGPRtoX86reg(_Rs_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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t0reg = _allocTempX86reg(-1);
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MOV32RtoR(t0reg, rsreg);
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SUB32RtoR(t0reg, rdreg);
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MOV32RtoR(rdreg, t0reg);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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_freeX86reg(t0reg);
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} else {
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_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV32RtoR(rdreg, rsreg);
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SUB32RtoR(rdreg, rtreg);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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}
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_clearNeededX86regs();
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#else
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MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Rt_ != 0 )
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{
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SUB32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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}
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CDQ( );
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MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
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#endif
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}
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////////////////////////////////////////////////////
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void recSUBU( void )
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{
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recSUB( );
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}
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////////////////////////////////////////////////////
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void recDSUB( void ) {
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int rdreg;
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int rsreg;
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int rtreg;
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int t0reg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rs_) {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SUB64RtoR(rdreg, rtreg);
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} else
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if (_Rd_ == _Rt_) {
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_addNeededGPRtoX86reg(_Rs_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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t0reg = _allocTempX86reg(-1);
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MOV64RtoR(t0reg, rsreg);
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SUB64RtoR(t0reg, rdreg);
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MOV64RtoR(rdreg, t0reg);
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_freeX86reg(t0reg);
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} else {
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_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rsreg);
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SUB64RtoR(rdreg, rtreg);
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}
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_clearNeededX86regs();
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#else
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MOV64MtoR( RAX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Rt_ != 0 ) {
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SUB64MtoR( RAX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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}
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MOV64RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], RAX );
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#endif
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}
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////////////////////////////////////////////////////
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void recDSUBU( void )
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{
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recDSUB( );
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}
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////////////////////////////////////////////////////
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void recAND( void ) {
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int rdreg;
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int rsreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rs_) {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_READ | MODE_WRITE);
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AND64RtoR(rdreg, rtreg);
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} else
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if (_Rd_ == _Rt_) {
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_addNeededGPRtoX86reg(_Rs_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_READ | MODE_WRITE);
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AND64RtoR(rdreg, rsreg);
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} else {
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_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rsreg);
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AND64RtoR(rdreg, rtreg);
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}
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_clearNeededX86regs();
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#else
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if (_Rt_ == _Rd_) { // Rd&= Rs
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MOV64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
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AND64RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], RAX);
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} else if (_Rs_ == _Rd_) { // Rd&= Rt
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MOV64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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AND64RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], RAX);
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} else { // Rd = Rs & Rt
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MOV64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
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AND64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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MOV64RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], RAX);
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}
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#endif
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}
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////////////////////////////////////////////////////
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void recOR( void ) {
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int rdreg;
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int rsreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rs_) {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_READ | MODE_WRITE);
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OR64RtoR(rdreg, rtreg);
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} else
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if (_Rd_ == _Rt_) {
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_addNeededGPRtoX86reg(_Rs_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_READ | MODE_WRITE);
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OR64RtoR(rdreg, rsreg);
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} else {
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_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rsreg);
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OR64RtoR(rdreg, rtreg);
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}
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_clearNeededX86regs();
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#else
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if ( ( _Rs_ == 0 ) && ( _Rt_ == 0 ) ) {
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XOR64RtoR(RAX, RAX);
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MOV64RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[0], RAX );
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} else if ( _Rs_ == 0 )
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{
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MOV64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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MOV64RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], RAX);
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}
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else if ( _Rt_ == 0 )
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{
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MOV64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
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MOV64RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], RAX);
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}
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else
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{
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MOV64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
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OR64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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MOV64RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], RAX);
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}
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#endif
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}
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////////////////////////////////////////////////////
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void recXOR( void ) {
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int rdreg;
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int rsreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rs_) {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_READ | MODE_WRITE);
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XOR64RtoR(rdreg, rtreg);
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} else
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if (_Rd_ == _Rt_) {
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_addNeededGPRtoX86reg(_Rs_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_READ | MODE_WRITE);
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XOR64RtoR(rdreg, rsreg);
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} else {
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_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rsreg);
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XOR64RtoR(rdreg, rtreg);
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}
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_clearNeededX86regs();
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#else
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MOV64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
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XOR64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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MOV64RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], RAX);
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#endif
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}
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////////////////////////////////////////////////////
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void recNOR( void ) {
|
|
int rdreg;
|
|
int rsreg;
|
|
int rtreg;
|
|
|
|
if (!_Rd_) return;
|
|
|
|
#ifdef ENABLE_REGCACHING
|
|
|
|
if (_Rd_ == _Rs_) {
|
|
_addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_READ | MODE_WRITE);
|
|
|
|
OR64RtoR(rdreg, rtreg);
|
|
NOT64R(rdreg);
|
|
} else
|
|
if (_Rd_ == _Rt_) {
|
|
_addNeededGPRtoX86reg(_Rs_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_READ | MODE_WRITE);
|
|
|
|
OR64RtoR(rdreg, rsreg);
|
|
NOT64R(rdreg);
|
|
} else {
|
|
_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
|
|
|
|
MOV64RtoR(rdreg, rsreg);
|
|
OR64RtoR(rdreg, rtreg);
|
|
NOT64R(rdreg);
|
|
}
|
|
|
|
_clearNeededX86regs();
|
|
|
|
#else
|
|
|
|
MOV64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
|
|
OR64MtoR(RAX, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
|
|
NOT64R(RAX);
|
|
MOV64RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], RAX);
|
|
|
|
#endif
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recSLT( void ) {
|
|
if (!_Rd_) return;
|
|
|
|
#ifdef ENABLE_REGCACHING
|
|
_freeX86regs();
|
|
#endif
|
|
MOV64MtoR(EAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
|
|
CMP64MtoR(EAX, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
|
|
SETL8R (EAX);
|
|
AND64ItoR(EAX, 0xff);
|
|
MOV64RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], EAX);
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recSLTU( void ) {
|
|
if (!_Rd_) return;
|
|
|
|
#ifdef ENABLE_REGCACHING
|
|
_freeX86regs();
|
|
#endif
|
|
MOV64MtoR(EAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
|
|
CMP64MtoR(EAX, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
|
|
SBB64RtoR(EAX, EAX);
|
|
NEG64R (EAX);
|
|
MOV64RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], RAX);
|
|
}
|
|
|
|
#endif
|