mirror of https://github.com/PCSX2/pcsx2.git
284 lines
4.4 KiB
C
284 lines
4.4 KiB
C
/*
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* Copyright (C) 2007-2009 Gabest
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* http://www.gabest.org
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*
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* This Program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This Program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Make; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA USA.
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* http://www.gnu.org/copyleft/gpl.html
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*
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*/
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#pragma once
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#pragma pack(push, 1)
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#include "GS.h"
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enum
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{
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GPU_POLYGON = 1,
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GPU_LINE = 2,
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GPU_SPRITE = 3,
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};
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REG32_(GPUReg, STATUS)
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uint32 TX:4;
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uint32 TY:1;
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uint32 ABR:2;
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uint32 TP:2;
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uint32 DTD:1;
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uint32 DFE:1;
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uint32 MD:1;
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uint32 ME:1;
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uint32 _PAD0:3;
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uint32 WIDTH1:1;
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uint32 WIDTH0:2;
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uint32 HEIGHT:1;
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uint32 ISPAL:1;
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uint32 ISRGB24:1;
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uint32 ISINTER:1;
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uint32 DEN:1;
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uint32 _PAD1:2;
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uint32 IDLE:1;
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uint32 IMG:1;
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uint32 COM:1;
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uint32 DMA:2;
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uint32 LCF:1;
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/*
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uint32 TX:4;
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uint32 TY:1;
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uint32 ABR:2;
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uint32 TP:2;
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uint32 DTD:1;
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uint32 DFE:1;
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uint32 PBW:1;
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uint32 PBC:1;
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uint32 _PAD0:3;
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uint32 HRES2:1;
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uint32 HRES1:2;
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uint32 VRES:1;
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uint32 ISPAL:1;
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uint32 ISRGB24:1;
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uint32 ISINTER:1;
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uint32 ISSTOP:1;
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uint32 _PAD1:1;
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uint32 DMARDY:1;
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uint32 IDIDLE:1;
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uint32 DATARDY:1;
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uint32 ISEMPTY:1;
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uint32 TMODE:2;
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uint32 ODE:1;
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*/
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REG_END
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REG32_(GPUReg, PACKET)
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uint32 _PAD:24;
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uint32 OPTION:5;
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uint32 TYPE:3;
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REG_END
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REG32_(GPUReg, PRIM)
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uint32 VTX:24;
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uint32 TGE:1;
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uint32 ABE:1;
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uint32 TME:1;
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uint32 _PAD2:1;
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uint32 IIP:1;
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uint32 TYPE:3;
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REG_END
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REG32_(GPUReg, POLYGON)
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uint32 _PAD:24;
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uint32 TGE:1;
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uint32 ABE:1;
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uint32 TME:1;
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uint32 VTX:1;
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uint32 IIP:1;
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uint32 TYPE:3;
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REG_END
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REG32_(GPUReg, LINE)
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uint32 _PAD:24;
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uint32 ZERO1:1;
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uint32 ABE:1;
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uint32 ZERO2:1;
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uint32 PLL:1;
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uint32 IIP:1;
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uint32 TYPE:3;
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REG_END
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REG32_(GPUReg, SPRITE)
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uint32 _PAD:24;
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uint32 ZERO:1;
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uint32 ABE:1;
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uint32 TME:1;
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uint32 SIZE:2;
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uint32 TYPE:3;
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REG_END
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REG32_(GPUReg, RESET)
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uint32 _PAD:32;
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REG_END
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REG32_(GPUReg, DEN)
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uint32 DEN:1;
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uint32 _PAD:31;
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REG_END
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REG32_(GPUReg, DMA)
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uint32 DMA:2;
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uint32 _PAD:30;
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REG_END
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REG32_(GPUReg, DAREA)
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uint32 X:10;
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uint32 Y:9;
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uint32 _PAD:13;
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REG_END
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REG32_(GPUReg, DHRANGE)
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uint32 X1:12;
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uint32 X2:12;
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uint32 _PAD:8;
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REG_END
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REG32_(GPUReg, DVRANGE)
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uint32 Y1:10;
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uint32 Y2:11;
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uint32 _PAD:11;
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REG_END
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REG32_(GPUReg, DMODE)
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uint32 WIDTH0:2;
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uint32 HEIGHT:1;
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uint32 ISPAL:1;
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uint32 ISRGB24:1;
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uint32 ISINTER:1;
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uint32 WIDTH1:1;
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uint32 REVERSE:1;
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uint32 _PAD:24;
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REG_END
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REG32_(GPUReg, GPUINFO)
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uint32 PARAM:24;
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uint32 _PAD:8;
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REG_END
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REG32_(GPUReg, MODE)
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uint32 TX:4;
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uint32 TY:1;
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uint32 ABR:2;
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uint32 TP:2;
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uint32 DTD:1;
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uint32 DFE:1;
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uint32 _PAD:21;
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REG_END
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REG32_(GPUReg, MASK)
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uint32 MD:1;
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uint32 ME:1;
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uint32 _PAD:30;
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REG_END
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REG32_(GPUReg, DRAREA)
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uint32 X:10;
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uint32 Y:10;
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uint32 _PAD:12;
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REG_END
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REG32_(GPUReg, DROFF)
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int32 X:11;
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int32 Y:11;
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int32 _PAD:10;
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REG_END
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REG32_(GPUReg, RGB)
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uint32 R:8;
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uint32 G:8;
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uint32 B:8;
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uint32 _PAD:8;
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REG_END
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REG32_(GPUReg, XY)
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int32 X:11;
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int32 _PAD1:5;
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int32 Y:11;
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int32 _PAD2:5;
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REG_END
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REG32_(GPUReg, UV)
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uint32 U:8;
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uint32 V:8;
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uint32 _PAD:16;
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REG_END
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REG32_(GPUReg, TWIN)
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uint32 TWW:5;
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uint32 TWH:5;
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uint32 TWX:5;
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uint32 TWY:5;
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uint32 _PAD:12;
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REG_END
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REG32_(GPUReg, CLUT)
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uint32 _PAD1:16;
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uint32 X:6;
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uint32 Y:9;
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uint32 _PAD2:1;
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REG_END
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REG32_SET(GPUReg)
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GPURegSTATUS STATUS;
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GPURegPACKET PACKET;
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GPURegPRIM PRIM;
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GPURegPOLYGON POLYGON;
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GPURegLINE LINE;
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GPURegSPRITE SPRITE;
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GPURegRESET RESET;
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GPURegDEN DEN;
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GPURegDMA DMA;
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GPURegDAREA DAREA;
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GPURegDHRANGE DHRANGE;
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GPURegDVRANGE DVRANGE;
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GPURegDMODE DMODE;
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GPURegGPUINFO GPUINFO;
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GPURegMODE MODE;
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GPURegMASK MASK;
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GPURegDRAREA DRAREA;
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GPURegDROFF DROFF;
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GPURegRGB RGB;
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GPURegXY XY;
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GPURegUV UV;
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GPURegTWIN TWIN;
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GPURegCLUT CLUT;
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REG_SET_END
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enum class GPURendererType : int8
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{
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D3D9_SW,
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D3D11_SW,
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NULL_Renderer,
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};
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struct GPUFreezeData
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{
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uint32 version; // == 1
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uint32 status;
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uint32 control[256];
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uint16 vram[1024 * 1024];
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};
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#pragma pack(pop)
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