mirror of https://github.com/PCSX2/pcsx2.git
352 lines
9.5 KiB
C++
352 lines
9.5 KiB
C++
/* Cpudetection lib
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* Copyright (C) 2002-2021 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "common/MemcpyFast.h"
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#include "common/General.h"
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#include "common/emitter/cpudetect_internal.h"
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#include "common/emitter/internal.h"
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#include "common/emitter/x86_intrin.h"
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#include <atomic>
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// CPU information support
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#if defined(_WIN32)
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#define cpuid __cpuid
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#define cpuidex __cpuidex
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#else
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#include <cpuid.h>
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static __inline__ __attribute__((always_inline)) void cpuidex(int CPUInfo[], const int InfoType, const int count)
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{
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__cpuid_count(InfoType, count, CPUInfo[0], CPUInfo[1], CPUInfo[2], CPUInfo[3]);
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}
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static __inline__ __attribute__((always_inline)) void cpuid(int CPUInfo[], const int InfoType)
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{
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__cpuid(InfoType, CPUInfo[0], CPUInfo[1], CPUInfo[2], CPUInfo[3]);
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}
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#endif
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using namespace x86Emitter;
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alignas(16) x86capabilities x86caps;
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#ifdef _MSC_VER
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// We disable optimizations for this function, because we need x86capabilities for AVX
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// detection, but if we keep opts on, it'll use AVX instructions for inlining memzero.
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#pragma optimize("", off)
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#endif
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x86capabilities::x86capabilities()
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: isIdentified(false)
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, VendorID(x86Vendor_Unknown)
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, FamilyID(0)
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, Model(0)
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, TypeID(0)
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, StepID(0)
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, Flags(0)
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, Flags2(0)
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, EFlags(0)
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, EFlags2(0)
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, SEFlag(0)
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, AllCapabilities(0)
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, PhysicalCores(0)
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, LogicalCores(0)
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{
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memzero(VendorName);
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memzero(FamilyName);
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}
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#ifdef _MSC_VER
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#pragma optimize("", on)
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#endif
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// Warning! We've had problems with the MXCSR detection code causing stack corruption in
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// MSVC PGO builds. The problem was fixed when I moved the MXCSR code to this function, and
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// moved the recSSE[] array to a global static (it was local to cpudetectInit). Commented
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// here in case the nutty crash ever re-surfaces. >_<
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// Note: recSSE was deleted
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void x86capabilities::SIMD_EstablishMXCSRmask()
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{
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if (!hasStreamingSIMDExtensions)
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return;
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MXCSR_Mask.bitmask = 0xFFBF; // MMX/SSE default
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if (hasStreamingSIMD2Extensions)
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{
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// This is generally safe assumption, but FXSAVE is the "correct" way to
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// detect MXCSR masking features of the cpu, so we use it's result below
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// and override this.
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MXCSR_Mask.bitmask = 0xFFFF; // SSE2 features added
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}
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alignas(16) u8 targetFXSAVE[512];
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// Work for recent enough GCC/CLANG/MSVC 2012
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_fxsave(&targetFXSAVE);
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u32 result;
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memcpy(&result, &targetFXSAVE[28], 4); // bytes 28->32 are the MXCSR_Mask.
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if (result != 0)
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MXCSR_Mask.bitmask = result;
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}
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// Counts the number of cpu cycles executed over the requested number of PerformanceCounter
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// ticks. Returns that exact count.
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// For best results you should pick a period of time long enough to get a reading that won't
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// be prone to rounding error; but short enough that it'll be highly unlikely to be interrupted
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// by the operating system task switches.
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s64 x86capabilities::_CPUSpeedHz(u64 time) const
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{
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u64 timeStart, timeStop;
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s64 startCycle, endCycle;
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if (!hasTimeStampCounter)
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return 0;
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SingleCoreAffinity affinity_lock;
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// Align the cpu execution to a cpuTick boundary.
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do
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{
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timeStart = GetCPUTicks();
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startCycle = __rdtsc();
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} while (GetCPUTicks() == timeStart);
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do
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{
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timeStop = GetCPUTicks();
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endCycle = __rdtsc();
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} while ((timeStop - timeStart) < time);
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s64 cycleCount = endCycle - startCycle;
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s64 timeCount = timeStop - timeStart;
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s64 overrun = timeCount - time;
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if (!overrun)
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return cycleCount;
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// interference could cause us to overshoot the target time, compensate:
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double cyclesPerTick = (double)cycleCount / (double)timeCount;
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double newCycleCount = (double)cycleCount - (cyclesPerTick * overrun);
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return (s64)newCycleCount;
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}
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const char* x86capabilities::GetTypeName() const
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{
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switch (TypeID)
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{
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case 0:
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return "Standard OEM";
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case 1:
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return "Overdrive";
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case 2:
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return "Dual";
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case 3:
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return "Reserved";
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default:
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return "Unknown";
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}
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}
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void x86capabilities::CountCores()
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{
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Identify();
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s32 regs[4];
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u32 cmds;
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cpuid(regs, 0x80000000);
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cmds = regs[0];
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// detect multicore for AMD cpu
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if ((cmds >= 0x80000008) && (VendorID == x86Vendor_AMD))
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{
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// AMD note: they don't support hyperthreading, but they like to flag this true
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// anyway. Let's force-unflag it until we come up with a better solution.
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// (note: seems to affect some Phenom II's only? -- Athlon X2's and PhenomI's do
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// not seem to do this) --air
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hasMultiThreading = 0;
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}
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// This will assign values into LogicalCores and PhysicalCores
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CountLogicalCores();
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}
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static const char* tbl_x86vendors[] =
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{
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"GenuineIntel",
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"AuthenticAMD",
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"Unknown ",
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};
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// Performs all _cpuid-related activity. This fills *most* of the x86caps structure, except for
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// the cpuSpeed and the mxcsr masks. Those must be completed manually.
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void x86capabilities::Identify()
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{
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if (isIdentified)
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return;
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isIdentified = true;
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s32 regs[4];
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u32 cmds;
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memzero(VendorName);
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cpuid(regs, 0);
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cmds = regs[0];
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memcpy(&VendorName[0], ®s[1], 4);
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memcpy(&VendorName[4], ®s[3], 4);
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memcpy(&VendorName[8], ®s[2], 4);
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// Determine Vendor Specifics!
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// It's really not recommended that we base much (if anything) on CPU vendor names,
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// however it's currently necessary in order to gain a (pseudo)reliable count of cores
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// and threads used by the CPU (AMD and Intel can't agree on how to make this info available).
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int vid;
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for (vid = 0; vid < x86Vendor_Unknown; ++vid)
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{
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if (memcmp(VendorName, tbl_x86vendors[vid], 12) == 0)
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break;
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}
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VendorID = static_cast<x86VendorType>(vid);
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if (cmds >= 0x00000001)
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{
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cpuid(regs, 0x00000001);
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StepID = regs[0] & 0xf;
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Model = (regs[0] >> 4) & 0xf;
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FamilyID = (regs[0] >> 8) & 0xf;
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TypeID = (regs[0] >> 12) & 0x3;
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//u32 x86_64_8BITBRANDID = regs[1] & 0xff;
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Flags = regs[3];
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Flags2 = regs[2];
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}
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if (cmds >= 0x00000007)
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{
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// Note: ECX must be 0 for AVX2 detection.
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cpuidex(regs, 0x00000007, 0);
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SEFlag = regs[1];
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}
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cpuid(regs, 0x80000000);
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cmds = regs[0];
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if (cmds >= 0x80000001)
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{
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cpuid(regs, 0x80000001);
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//u32 x86_64_12BITBRANDID = regs[1] & 0xfff;
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EFlags2 = regs[2];
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EFlags = regs[3];
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}
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memzero(FamilyName);
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cpuid((int*)FamilyName, 0x80000002);
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cpuid((int*)(FamilyName + 16), 0x80000003);
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cpuid((int*)(FamilyName + 32), 0x80000004);
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hasFloatingPointUnit = (Flags >> 0) & 1;
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hasVirtual8086ModeEnhancements = (Flags >> 1) & 1;
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hasDebuggingExtensions = (Flags >> 2) & 1;
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hasPageSizeExtensions = (Flags >> 3) & 1;
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hasTimeStampCounter = (Flags >> 4) & 1;
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hasModelSpecificRegisters = (Flags >> 5) & 1;
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hasPhysicalAddressExtension = (Flags >> 6) & 1;
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hasMachineCheckArchitecture = (Flags >> 7) & 1;
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hasCOMPXCHG8BInstruction = (Flags >> 8) & 1;
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hasAdvancedProgrammableInterruptController = (Flags >> 9) & 1;
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hasSEPFastSystemCall = (Flags >> 11) & 1;
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hasMemoryTypeRangeRegisters = (Flags >> 12) & 1;
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hasPTEGlobalFlag = (Flags >> 13) & 1;
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hasMachineCheckArchitecture = (Flags >> 14) & 1;
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hasConditionalMoveAndCompareInstructions = (Flags >> 15) & 1;
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hasFGPageAttributeTable = (Flags >> 16) & 1;
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has36bitPageSizeExtension = (Flags >> 17) & 1;
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hasProcessorSerialNumber = (Flags >> 18) & 1;
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hasCFLUSHInstruction = (Flags >> 19) & 1;
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hasDebugStore = (Flags >> 21) & 1;
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hasACPIThermalMonitorAndClockControl = (Flags >> 22) & 1;
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hasFastStreamingSIMDExtensionsSaveRestore = (Flags >> 24) & 1;
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hasStreamingSIMDExtensions = (Flags >> 25) & 1; //sse
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hasStreamingSIMD2Extensions = (Flags >> 26) & 1; //sse2
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hasSelfSnoop = (Flags >> 27) & 1;
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hasMultiThreading = (Flags >> 28) & 1;
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hasThermalMonitor = (Flags >> 29) & 1;
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hasIntel64BitArchitecture = (Flags >> 30) & 1;
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// -------------------------------------------------
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// --> SSE3 / SSSE3 / SSE4.1 / SSE 4.2 detection <--
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// -------------------------------------------------
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hasStreamingSIMD3Extensions = (Flags2 >> 0) & 1; //sse3
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hasSupplementalStreamingSIMD3Extensions = (Flags2 >> 9) & 1; //ssse3
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hasStreamingSIMD4Extensions = (Flags2 >> 19) & 1; //sse4.1
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hasStreamingSIMD4Extensions2 = (Flags2 >> 20) & 1; //sse4.2
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if ((Flags2 >> 27) & 1) // OSXSAVE
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{
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// Note: In theory, we should use xgetbv to check OS support
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// but all OSes we officially run under support it
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// and its intrinsic requires extra compiler flags
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hasAVX = (Flags2 >> 28) & 1; //avx
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hasFMA = (Flags2 >> 12) & 1; //fma
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hasAVX2 = (SEFlag >> 5) & 1; //avx2
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}
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hasBMI1 = (SEFlag >> 3) & 1;
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hasBMI2 = (SEFlag >> 8) & 1;
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// Ones only for AMDs:
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hasAMD64BitArchitecture = (EFlags >> 29) & 1; //64bit cpu
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hasStreamingSIMD4ExtensionsA = (EFlags2 >> 6) & 1; //INSERTQ / EXTRQ / MOVNT
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isIdentified = true;
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}
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u32 x86capabilities::CalculateMHz() const
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{
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InitCPUTicks();
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u64 span = GetTickFrequency();
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if ((span % 1000) < 400) // helps minimize rounding errors
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return (u32)(_CPUSpeedHz(span / 1000) / 1000);
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else
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return (u32)(_CPUSpeedHz(span / 500) / 2000);
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}
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u32 x86capabilities::CachedMHz()
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{
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static std::atomic<u32> cached{0};
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u32 local = cached.load(std::memory_order_relaxed);
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if (unlikely(local == 0))
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{
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x86capabilities caps;
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caps.Identify();
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local = caps.CalculateMHz();
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cached.store(local, std::memory_order_relaxed);
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}
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return local;
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}
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