mirror of https://github.com/PCSX2/pcsx2.git
402 lines
14 KiB
C++
402 lines
14 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "Vif.h"
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#include "Vif_Dma.h"
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#include "newVif.h"
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#include "GS.h"
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#include "Gif.h"
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#include "MTVU.h"
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#include "Gif_Unit.h"
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__aligned16 vifStruct vif0, vif1;
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void vif0Reset()
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{
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/* Reset the whole VIF, meaning the internal pcsx2 vars and all the registers */
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memzero(vif0);
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memzero(vif0Regs);
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resetNewVif(0);
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}
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void vif1Reset()
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{
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/* Reset the whole VIF, meaning the internal pcsx2 vars, and all the registers */
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memzero(vif1);
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memzero(vif1Regs);
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resetNewVif(1);
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}
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void SaveStateBase::vif0Freeze()
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{
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FreezeTag("VIF0dma");
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Freeze(g_vif0Cycles);
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Freeze(vif0);
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Freeze(nVif[0].bSize);
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FreezeMem(nVif[0].buffer, nVif[0].bSize);
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}
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void SaveStateBase::vif1Freeze()
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{
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FreezeTag("VIF1dma");
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Freeze(g_vif1Cycles);
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Freeze(vif1);
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Freeze(nVif[1].bSize);
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FreezeMem(nVif[1].buffer, nVif[1].bSize);
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}
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//------------------------------------------------------------------
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// Vif0/Vif1 Write32
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//------------------------------------------------------------------
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extern bool _chainVIF0();
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extern bool _VIF0chain();
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__fi void vif0FBRST(u32 value) {
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VIF_LOG("VIF0_FBRST write32 0x%8.8x", value);
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if (value & 0x1) // Reset Vif.
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{
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//Console.WriteLn("Vif0 Reset %x", vif0Regs.stat._u32);
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u128 SaveCol;
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u128 SaveRow;
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// if(vif0ch.chcr.STR == true) DevCon.Warning("FBRST While Vif0 active");
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//Must Preserve Row/Col registers! (Downhill Domination for testing)
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SaveCol._u64[0] = vif0.MaskCol._u64[0];
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SaveCol._u64[1] = vif0.MaskCol._u64[1];
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SaveRow._u64[0] = vif0.MaskRow._u64[0];
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SaveRow._u64[1] = vif0.MaskRow._u64[1];
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memzero(vif0);
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vif0.MaskCol._u64[0] = SaveCol._u64[0];
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vif0.MaskCol._u64[1] = SaveCol._u64[1];
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vif0.MaskRow._u64[0] = SaveRow._u64[0];
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vif0.MaskRow._u64[1] = SaveRow._u64[1];
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vif0ch.qwc = 0; //?
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cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
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psHu64(VIF0_FIFO) = 0;
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psHu64(VIF0_FIFO + 8) = 0;
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vif0.vifstalled.enabled = false;
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vif0.irqoffset.enabled = false;
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vif0.inprogress = 0;
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vif0.cmd = 0;
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vif0.done = true;
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vif0ch.chcr.STR = false;
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vif0Regs.err.reset();
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vif0Regs.stat.clear_flags(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
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}
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/* Fixme: Forcebreaks are pretty unknown for operation, presumption is it just stops it what its doing
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usually accompanied by a reset, but if we find a broken game which falls here, we need to see it! (Refraction) */
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if (value & 0x2) // Forcebreak Vif,
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{
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/* I guess we should stop the VIF dma here, but not 100% sure (linuz) */
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cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
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vif0Regs.stat.VFS = true;
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vif0Regs.stat.VPS = VPS_IDLE;
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Console.WriteLn("vif0 force break");
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}
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if (value & 0x4) // Stop Vif.
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{
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// Not completely sure about this, can't remember what game, used this, but 'draining' the VIF helped it, instead of
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// just stoppin the VIF (linuz).
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vif0Regs.stat.VSS = true;
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vif0Regs.stat.VPS = VPS_IDLE;
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vif0.vifstalled.enabled = VifStallEnable(vif0ch);
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vif0.vifstalled.value = VIF_IRQ_STALL;
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}
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if (value & 0x8) // Cancel Vif Stall.
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{
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bool cancel = false;
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/* Cancel stall, first check if there is a stall to cancel, and then clear VIF0_STAT VSS|VFS|VIS|INT|ER0|ER1 bits */
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if (vif0Regs.stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
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cancel = true;
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vif0Regs.stat.clear_flags(VIF0_STAT_VSS | VIF0_STAT_VFS | VIF0_STAT_VIS |
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VIF0_STAT_INT | VIF0_STAT_ER0 | VIF0_STAT_ER1);
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if (cancel)
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{
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if (vif0.vifstalled.enabled && vif0.vifstalled.value == VIF_IRQ_STALL)
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{
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g_vif0Cycles = 0;
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// loop necessary for spiderman
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//vif0ch.chcr.STR = true;
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if(vif0ch.chcr.STR) CPU_INT(DMAC_VIF0, 0); // Gets the timing right - Flatout
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}
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}
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}
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}
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__fi void vif1FBRST(u32 value) {
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VIF_LOG("VIF1_FBRST write32 0x%8.8x", value);
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if (FBRST(value).RST) // Reset Vif.
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{
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u128 SaveCol;
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u128 SaveRow;
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//if(vif1ch.chcr.STR == true) DevCon.Warning("FBRST While Vif1 active");
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//Must Preserve Row/Col registers! (Downhill Domination for testing) - Really shouldnt be part of the vifstruct.
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SaveCol._u64[0] = vif1.MaskCol._u64[0];
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SaveCol._u64[1] = vif1.MaskCol._u64[1];
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SaveRow._u64[0] = vif1.MaskRow._u64[0];
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SaveRow._u64[1] = vif1.MaskRow._u64[1];
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memzero(vif1);
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vif1.MaskCol._u64[0] = SaveCol._u64[0];
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vif1.MaskCol._u64[1] = SaveCol._u64[1];
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vif1.MaskRow._u64[0] = SaveRow._u64[0];
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vif1.MaskRow._u64[1] = SaveRow._u64[1];
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cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
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///vif1ch.qwc -= std::min((int)vif1ch.qwc, 16); //not sure if the dma should stop, FFWDing could be tricky
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vif1ch.qwc = 0;
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psHu64(VIF1_FIFO) = 0;
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psHu64(VIF1_FIFO + 8) = 0;
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vif1.done = true;
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vif1ch.chcr.STR = false;
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//HACK!! Dynasty Warriors 5 Empires has some sort of wierd packet alignment thing going off, meaning
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//the packet ends before the DirectHL in progress has finished. Not sure what causes that, but the GIF
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//Unit is still waiting for more data, so we have to "pretend" it is finished when the game issues a reset
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//which it does without causing any pauses.
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//In most cases, this will never ever happen, so doing the following won't matter.
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if(!gifUnit.gifPath[GIF_PATH_2].isDone())
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{
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DevCon.Warning("VIF1 FBRST While GIF Path2 is waiting for data!");
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gifUnit.gifPath[GIF_PATH_2].state = GIF_PATH_IDLE;
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gifUnit.gifPath[GIF_PATH_2].curSize = gifUnit.gifPath[GIF_PATH_2].curOffset;
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if( gifRegs.stat.APATH == 2)
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{
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gifRegs.stat.APATH = 0;
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gifRegs.stat.OPH = 0;
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vif1Regs.stat.VGW = false; //Let vif continue if it's stuck on a flush
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if(gifUnit.checkPaths(1,0,1)) gifUnit.Execute(false, true);
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}
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}
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#if USE_OLD_GIF == 1 // ...
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if(vif1Regs.mskpath3 == 1 && GSTransferStatus.PTH3 == STOPPED_MODE && gifch.chcr.STR == true) {
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DevCon.Warning("VIF Path3 Resume on FBRST MSK = %x", vif1Regs.mskpath3);
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gifInterrupt();
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vif1Regs.mskpath3 = false;
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gifRegs.stat.M3P = false;
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}
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#endif
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GUNIT_WARN(Color_Red, "VIF FBRST Reset MSK = %x", vif1Regs.mskpath3);
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vif1Regs.mskpath3 = false;
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gifRegs.stat.M3P = 0;
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vif1Regs.err.reset();
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vif1.inprogress = 0;
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vif1.cmd = 0;
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vif1.vifstalled.enabled = false;
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vif1.irqoffset.enabled = false;
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vif1Regs.stat.FQC = 0;
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vif1Regs.stat.clear_flags(VIF1_STAT_FDR | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS);
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}
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/* Fixme: Forcebreaks are pretty unknown for operation, presumption is it just stops it what its doing
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usually accompanied by a reset, but if we find a broken game which falls here, we need to see it! (Refraction) */
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if (FBRST(value).FBK) // Forcebreak Vif.
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{
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/* I guess we should stop the VIF dma here, but not 100% sure (linuz) */
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vif1Regs.stat.VFS = true;
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vif1Regs.stat.VPS = VPS_IDLE;
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cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
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vif1.vifstalled.enabled = VifStallEnable(vif1ch);
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vif1.vifstalled.value = VIF_IRQ_STALL;
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Console.WriteLn("vif1 force break");
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}
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if (FBRST(value).STP) // Stop Vif.
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{
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// Not completely sure about this, can't remember what game used this, but 'draining' the VIF helped it, instead of
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// just stoppin the VIF (linuz).
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vif1Regs.stat.VSS = true;
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vif1Regs.stat.VPS = VPS_IDLE;
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cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
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vif1.vifstalled.enabled = VifStallEnable(vif1ch);
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vif1.vifstalled.value = VIF_IRQ_STALL;
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}
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if (FBRST(value).STC) // Cancel Vif Stall.
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{
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bool cancel = false;
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/* Cancel stall, first check if there is a stall to cancel, and then clear VIF1_STAT VSS|VFS|VIS|INT|ER0|ER1 bits */
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if (vif1Regs.stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
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{
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cancel = true;
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}
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vif1Regs.stat.clear_flags(VIF1_STAT_VSS | VIF1_STAT_VFS | VIF1_STAT_VIS |
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VIF1_STAT_INT | VIF1_STAT_ER0 | VIF1_STAT_ER1);
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if (cancel)
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{
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if (vif1.vifstalled.enabled && vif1.vifstalled.value == VIF_IRQ_STALL)
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{
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g_vif1Cycles = 0;
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// loop necessary for spiderman
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switch(dmacRegs.ctrl.MFD)
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{
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case MFD_VIF1:
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//Console.WriteLn("MFIFO Stall");
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//MFIFO active and not empty
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if(vif1ch.chcr.STR == true) CPU_INT(DMAC_MFIFO_VIF, 0);
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break;
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case NO_MFD:
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case MFD_RESERVED:
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case MFD_GIF: // Wonder if this should be with VIF?
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// Gets the timing right - Flatout
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if(vif1ch.chcr.STR == true) CPU_INT(DMAC_VIF1, 0);
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break;
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}
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//vif1ch.chcr.STR = true;
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}
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}
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}
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}
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__fi void vif1STAT(u32 value) {
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VIF_LOG("VIF1_STAT write32 0x%8.8x", value);
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/* Only FDR bit is writable, so mask the rest */
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if ((vif1Regs.stat.FDR) ^ ((tVIF_STAT&)value).FDR) {
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// different so can't be stalled
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if (vif1Regs.stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS)) {
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DevCon.WriteLn("changing dir when vif1 fifo stalled done = %x qwc = %x", vif1.done, vif1ch.qwc);
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}
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//Hack!! Hotwheels seems to leave 1QW in the fifo and expect the DMA to be ready for a reverse FIFO
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//There's no important data in there so for it to work, we will just end it.
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//Hotwheels had this in the "direction when stalled" area, however Sled Storm seems to keep an eye on the dma
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//position, as we clear it and set it to the end well before the interrupt, the game assumes it's finished,
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//then proceeds to reverse the dma before we have even done it ourselves. So lets just make sure VIF is ready :)
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vif1ch.chcr.STR = false;
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cpuRegs.interrupt &= ~((1 << DMAC_VIF1) | (1 << DMAC_MFIFO_VIF));
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//This is actually more important for our handling, else the DMA for reverse fifo doesnt start properly.
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}
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vif1Regs.stat.FDR = VIF_STAT(value).FDR;
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if (vif1Regs.stat.FDR) // Vif transferring to memory.
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{
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// Hack but it checks this is true before transfer? (fatal frame)
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// Update Refraction: Use of this function has been investigated and understood.
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// Before this ever happens, a DIRECT/HL command takes place sending the transfer info to the GS
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// One of the registers told about this is TRXREG which tells us how much data is going to transfer (th x tw) in words
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// As far as the GS is concerned, the transfer starts as soon as TRXDIR is accessed, which is why fatal frame
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// was expecting data, the GS should already be sending it over (buffering in the FIFO)
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vif1Regs.stat.FQC = std::min((u32)16, vif1.GSLastDownloadSize);
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//Console.Warning("Reversing VIF Transfer for %x QWC", vif1.GSLastDownloadSize);
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}
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else // Memory transferring to Vif.
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{
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//Sometimes the value from the GS is bigger than vif wanted, so it just sets it back and cancels it.
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//Other times it can read it off ;)
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vif1Regs.stat.FQC = 0;
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}
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}
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#define caseVif(x) (idx ? VIF1_##x : VIF0_##x)
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_vifT __fi u32 vifRead32(u32 mem) {
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vifStruct& vif = MTVU_VifX;
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bool wait = idx && THREAD_VU1;
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switch (mem) {
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case caseVif(ROW0): if (wait) vu1Thread.WaitVU(); return vif.MaskRow._u32[0];
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case caseVif(ROW1): if (wait) vu1Thread.WaitVU(); return vif.MaskRow._u32[1];
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case caseVif(ROW2): if (wait) vu1Thread.WaitVU(); return vif.MaskRow._u32[2];
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case caseVif(ROW3): if (wait) vu1Thread.WaitVU(); return vif.MaskRow._u32[3];
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case caseVif(COL0): if (wait) vu1Thread.WaitVU(); return vif.MaskCol._u32[0];
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case caseVif(COL1): if (wait) vu1Thread.WaitVU(); return vif.MaskCol._u32[1];
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case caseVif(COL2): if (wait) vu1Thread.WaitVU(); return vif.MaskCol._u32[2];
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case caseVif(COL3): if (wait) vu1Thread.WaitVU(); return vif.MaskCol._u32[3];
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}
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return psHu32(mem);
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}
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// returns FALSE if no writeback is needed (or writeback is handled internally)
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// returns TRUE if the caller should writeback the value to the eeHw register map.
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_vifT __fi bool vifWrite32(u32 mem, u32 value) {
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vifStruct& vif = GetVifX;
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switch (mem) {
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case caseVif(MARK):
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VIF_LOG("VIF%d_MARK write32 0x%8.8x", idx, value);
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vifXRegs.stat.MRK = false;
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//vifXRegs.mark = value;
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break;
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case caseVif(FBRST):
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if (!idx) vif0FBRST(value);
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else vif1FBRST(value);
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return false;
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case caseVif(STAT):
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if (idx) { // Only Vif1 does this stuff?
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vif1STAT(value);
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}
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return false;
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case caseVif(ERR):
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case caseVif(MODE):
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// standard register writes -- handled by caller.
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break;
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case caseVif(ROW0): vif.MaskRow._u32[0] = value; if (idx && THREAD_VU1) vu1Thread.WriteRow(vif); return false;
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case caseVif(ROW1): vif.MaskRow._u32[1] = value; if (idx && THREAD_VU1) vu1Thread.WriteRow(vif); return false;
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case caseVif(ROW2): vif.MaskRow._u32[2] = value; if (idx && THREAD_VU1) vu1Thread.WriteRow(vif); return false;
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case caseVif(ROW3): vif.MaskRow._u32[3] = value; if (idx && THREAD_VU1) vu1Thread.WriteRow(vif); return false;
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case caseVif(COL0): vif.MaskCol._u32[0] = value; if (idx && THREAD_VU1) vu1Thread.WriteCol(vif); return false;
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case caseVif(COL1): vif.MaskCol._u32[1] = value; if (idx && THREAD_VU1) vu1Thread.WriteCol(vif); return false;
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case caseVif(COL2): vif.MaskCol._u32[2] = value; if (idx && THREAD_VU1) vu1Thread.WriteCol(vif); return false;
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case caseVif(COL3): vif.MaskCol._u32[3] = value; if (idx && THREAD_VU1) vu1Thread.WriteCol(vif); return false;
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}
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// fall-through case: issue standard writeback behavior.
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return true;
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}
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template u32 vifRead32<0>(u32 mem);
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template u32 vifRead32<1>(u32 mem);
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template bool vifWrite32<0>(u32 mem, u32 value);
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template bool vifWrite32<1>(u32 mem, u32 value);
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