mirror of https://github.com/PCSX2/pcsx2.git
639 lines
14 KiB
C
639 lines
14 KiB
C
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __HW_H__
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#define __HW_H__
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extern u8 *psH; // hw mem
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extern void CPU_INT( u32 n, s32 ecycle );
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//////////////////////////////////////////////////////////////////////////
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// Hardware FIFOs (128 bit access only!)
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//
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// VIF0 -- 0x10004000 -- PS2MEM_HW[0x4000]
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// VIF1 -- 0x10005000 -- PS2MEM_HW[0x5000]
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// GIF -- 0x10006000 -- PS2MEM_HW[0x6000]
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// IPUout -- 0x10007000 -- PS2MEM_HW[0x7000]
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// IPUin -- 0x10007010 -- PS2MEM_HW[0x7010]
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void __fastcall ReadFIFO_page_4(u32 mem, mem128_t *out);
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void __fastcall ReadFIFO_page_5(u32 mem, mem128_t *out);
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void __fastcall ReadFIFO_page_6(u32 mem, mem128_t *out);
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void __fastcall ReadFIFO_page_7(u32 mem, mem128_t *out);
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void __fastcall WriteFIFO_page_4(u32 mem, const mem128_t *value);
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void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value);
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void __fastcall WriteFIFO_page_6(u32 mem, const mem128_t *value);
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void __fastcall WriteFIFO_page_7(u32 mem, const mem128_t *value);
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//
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// --- DMA ---
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//
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union tDMA_CHCR {
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struct {
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u32 DIR : 1;
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u32 reserved1 : 1;
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u32 MOD : 2;
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u32 ASP : 2;
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u32 TTE : 1;
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u32 TIE : 1;
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u32 STR : 1;
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u32 reserved2 : 7;
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u32 TAG : 16;
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};
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u32 _u32;
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};
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union tDMA_SADR {
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struct {
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u32 ADDR : 14;
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u32 reserved2 : 18;
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};
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u32 _u32;
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};
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struct DMACh {
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tDMA_CHCR chcr;
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u32 null0[3];
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u32 madr;
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u32 null1[3];
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u16 qwc; u16 pad;
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u32 null2[3];
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u32 tadr;
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u32 null3[3];
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u32 asr0;
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u32 null4[3];
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u32 asr1;
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u32 null5[11];
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u32 sadr;
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};
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// HW defines
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enum EERegisterAddresses
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{
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RCNT0_COUNT = 0x10000000,
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RCNT0_MODE = 0x10000010,
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RCNT0_TARGET = 0x10000020,
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RCNT0_HOLD = 0x10000030,
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RCNT1_COUNT = 0x10000800,
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RCNT1_MODE = 0x10000810,
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RCNT1_TARGET = 0x10000820,
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RCNT1_HOLD = 0x10000830,
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RCNT2_COUNT = 0x10001000,
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RCNT2_MODE = 0x10001010,
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RCNT2_TARGET = 0x10001020,
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RCNT3_COUNT = 0x10001800,
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RCNT3_MODE = 0x10001810,
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RCNT3_TARGET = 0x10001820,
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IPU_CMD = 0x10002000,
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IPU_CTRL = 0x10002010,
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IPU_BP = 0x10002020,
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IPU_TOP = 0x10002030,
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GIF_CTRL = 0x10003000,
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GIF_MODE = 0x10003010,
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GIF_STAT = 0x10003020,
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GIF_TAG0 = 0x10003040,
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GIF_TAG1 = 0x10003050,
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GIF_TAG2 = 0x10003060,
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GIF_TAG3 = 0x10003070,
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GIF_CNT = 0x10003080,
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GIF_P3CNT = 0x10003090,
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GIF_P3TAG = 0x100030A0,
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// Vif Memory Locations
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VIF0_STAT = 0x10003800,
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VIF0_FBRST = 0x10003810,
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VIF0_ERR = 0x10003820,
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VIF0_MARK = 0x10003830,
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VIF0_CYCLE = 0x10003840,
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VIF0_MODE = 0x10003850,
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VIF0_NUM = 0x10003860,
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VIF0_MASK = 0x10003870,
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VIF0_CODE = 0x10003880,
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VIF0_ITOPS = 0x10003890,
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VIF0_ITOP = 0x100038d0,
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VIF0_TOP = 0x100038e0,
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VIF0_R0 = 0x10003900,
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VIF0_R1 = 0x10003910,
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VIF0_R2 = 0x10003920,
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VIF0_R3 = 0x10003930,
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VIF0_C0 = 0x10003940,
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VIF0_C1 = 0x10003950,
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VIF0_C2 = 0x10003960,
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VIF0_C3 = 0x10003970,
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VIF1_STAT = 0x10003c00,
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VIF1_FBRST = 0x10003c10,
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VIF1_ERR = 0x10003c20,
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VIF1_MARK = 0x10003c30,
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VIF1_CYCLE = 0x10003c40,
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VIF1_MODE = 0x10003c50,
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VIF1_NUM = 0x10003c60,
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VIF1_MASK = 0x10003c70,
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VIF1_CODE = 0x10003c80,
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VIF1_ITOPS = 0x10003c90,
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VIF1_BASE = 0x10003ca0,
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VIF1_OFST = 0x10003cb0,
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VIF1_TOPS = 0x10003cc0,
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VIF1_ITOP = 0x10003cd0,
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VIF1_TOP = 0x10003ce0,
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VIF1_R0 = 0x10003d00,
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VIF1_R1 = 0x10003d10,
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VIF1_R2 = 0x10003d20,
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VIF1_R3 = 0x10003d30,
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VIF1_C0 = 0x10003d40,
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VIF1_C1 = 0x10003d50,
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VIF1_C2 = 0x10003d60,
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VIF1_C3 = 0x10003d70,
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VIF0_FIFO = 0x10004000,
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VIF1_FIFO = 0x10005000,
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GIF_FIFO = 0x10006000,
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IPUout_FIFO = 0x10007000,
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IPUin_FIFO = 0x10007010,
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//VIF0
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D0_CHCR = 0x10008000,
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D0_MADR = 0x10008010,
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D0_QWC = 0x10008020,
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//VIF1
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D1_CHCR = 0x10009000,
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D1_MADR = 0x10009010,
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D1_QWC = 0x10009020,
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D1_TADR = 0x10009030,
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D1_ASR0 = 0x10009040,
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D1_ASR1 = 0x10009050,
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D1_SADR = 0x10009080,
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//GS
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D2_CHCR = 0x1000A000,
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D2_MADR = 0x1000A010,
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D2_QWC = 0x1000A020,
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D2_TADR = 0x1000A030,
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D2_ASR0 = 0x1000A040,
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D2_ASR1 = 0x1000A050,
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D2_SADR = 0x1000A080,
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//fromIPU
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D3_CHCR = 0x1000B000,
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D3_MADR = 0x1000B010,
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D3_QWC = 0x1000B020,
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D3_TADR = 0x1000B030,
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D3_SADR = 0x1000B080,
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//toIPU
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D4_CHCR = 0x1000B400,
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D4_MADR = 0x1000B410,
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D4_QWC = 0x1000B420,
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D4_TADR = 0x1000B430,
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D4_SADR = 0x1000B480,
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//SIF0
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D5_CHCR = 0x1000C000,
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D5_MADR = 0x1000C010,
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D5_QWC = 0x1000C020,
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//SIF1
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D6_CHCR = 0x1000C400,
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D6_MADR = 0x1000C410,
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D6_QWC = 0x1000C420,
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D6_TADR = 0x1000C430,
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//SIF2
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D7_CHCR = 0x1000C800,
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D7_MADR = 0x1000C810,
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D7_QWC = 0x1000C820,
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//fromSPR
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D8_CHCR = 0x1000D000,
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D8_MADR = 0x1000D010,
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D8_QWC = 0x1000D020,
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D8_SADR = 0x1000D080,
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SPR1_CHCR = 0x1000D400,
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DMAC_CTRL = 0x1000E000,
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DMAC_STAT = 0x1000E010,
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DMAC_PCR = 0x1000E020,
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DMAC_SQWC = 0x1000E030,
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DMAC_RBSR = 0x1000E040,
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DMAC_RBOR = 0x1000E050,
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DMAC_STADR = 0x1000E060,
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INTC_STAT = 0x1000F000,
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INTC_MASK = 0x1000F010,
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SIO_LCR = 0x1000F100,
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SIO_LSR = 0x1000F110,
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SIO_IER = 0x1000F120,
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SIO_ISR = 0x1000F130,//
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SIO_FCR = 0x1000F140,
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SIO_BGR = 0x1000F150,
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SIO_TXFIFO = 0x1000F180,
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SIO_RXFIFO = 0x1000F1C0,
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SBUS_F200 = 0x1000F200, //MSCOM
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SBUS_F210 = 0x1000F210, //SMCOM
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SBUS_F220 = 0x1000F220, //MSFLG
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SBUS_F230 = 0x1000F230, //SMFLG
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SBUS_F240 = 0x1000F240,
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SBUS_F250 = 0x1000F250,
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SBUS_F260 = 0x1000F260,
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MCH_RICM = 0x1000F430,
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MCH_DRD = 0x1000F440,
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DMAC_ENABLER = 0x1000F520,
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DMAC_ENABLEW = 0x1000F590
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};
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enum GSRegisterAddresses
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{
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GS_PMODE = 0x12000000,
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GS_SMODE1 = 0x12000010,
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GS_SMODE2 = 0x12000020,
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GS_SRFSH = 0x12000030,
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GS_SYNCH1 = 0x12000040,
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GS_SYNCH2 = 0x12000050,
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GS_SYNCV = 0x12000060,
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GS_DISPFB1 = 0x12000070,
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GS_DISPLAY1 = 0x12000080,
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GS_DISPFB2 = 0x12000090,
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GS_DISPLAY2 = 0x120000A0,
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GS_EXTBUF = 0x120000B0,
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GS_EXTDATA = 0x120000C0,
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GS_EXTWRITE = 0x120000D0,
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GS_BGCOLOR = 0x120000E0,
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GS_CSR = 0x12001000,
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GS_IMR = 0x12001010,
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GS_BUSDIR = 0x12001040,
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GS_SIGLBLID = 0x12001080
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};
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//#define SBFLG_IOPALIVE 0x10000
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//#define SBFLG_IOPSYNC 0x40000
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enum INTCIrqs
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{
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INTC_GS = 0,
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INTC_SBUS,
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INTC_VBLANK_S,
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INTC_VBLANK_E,
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INTC_VIF0,
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INTC_VIF1,
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INTC_VU0,
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INTC_VU1,
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INTC_IPU,
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INTC_TIM0,
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INTC_TIM1,
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INTC_TIM2,
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INTC_TIM3,
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INTC_SFIFO,
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INTVU0_WD
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};
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enum dmac_conditions
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{
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DMAC_STAT_SIS = (1<<13), // stall condition
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DMAC_STAT_MEIS = (1<<14), // mfifo empty
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DMAC_STAT_BEIS = (1<<15), // bus error
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DMAC_STAT_SIM = (1<<29), // stall mask
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DMAC_STAT_MEIM = (1<<30) // mfifo mask
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};
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enum DMACIrqs
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{
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DMAC_VIF0 = 0,
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DMAC_VIF1,
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DMAC_GIF,
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DMAC_FROM_IPU,
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DMAC_TO_IPU,
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DMAC_SIF0,
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DMAC_SIF1,
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DMAC_SIF2,
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DMAC_FROM_SPR,
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DMAC_TO_SPR,
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// We're setting error conditions through hwDmacIrq, so these correspond to the conditions above.
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DMAC_STALL_SIS = 13, // SIS
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DMAC_MFIFO_EMPTY = 14, // MEIS
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DMAC_BUS_ERROR = 15 // BEIS
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};
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//DMA interrupts & masks
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enum DMAInter
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{
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BEISintr = 0x00008000,
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VIF0intr = 0x00010001,
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VIF1intr = 0x00020002,
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GIFintr = 0x00040004,
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IPU0intr = 0x00080008,
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IPU1intr = 0x00100010,
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SIF0intr = 0x00200020,
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SIF1intr =0x00400040,
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SIF2intr = 0x00800080,
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SPR0intr = 0x01000100,
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SPR1intr = 0x02000200,
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SISintr = 0x20002000,
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MEISintr = 0x40004000
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};
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union tDMAC_CTRL {
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struct {
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u32 DMAE : 1;
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u32 RELE : 1;
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u32 MFD : 2;
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u32 STS : 2;
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u32 STD : 2;
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u32 RCYC : 3;
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u32 reserved1 : 21;
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};
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u32 _u32;
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};
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union tDMAC_STAT {
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struct {
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u32 CIS : 10;
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u32 reserved1 : 3;
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u32 SIS : 1;
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u32 MEIS : 1;
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u32 BEIS : 1;
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u32 CIM : 10;
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u32 reserved2 : 3;
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u32 SIM : 1;
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u32 MEIM : 1;
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u32 reserved3 : 1;
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};
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u32 _u32;
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set(u32 flags) { _u32 |= flags; }
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void clear(u32 flags) { _u32 &= ~flags; }
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};
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union tDMAC_PCR {
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struct {
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u32 CPC : 10;
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u32 reserved1 : 6;
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u32 CDE : 10;
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u32 reserved2 : 5;
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u32 PCE : 1;
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};
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u32 _u32;
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};
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union tDMAC_SQWC {
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struct {
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u32 SQWC : 8;
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u32 reserved1 : 8;
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u32 TQWC : 8;
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u32 reserved2 : 8;
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};
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u32 _u32;
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};
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union tDMAC_RBSR {
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struct {
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u32 RMSK : 31;
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u32 reserved1 : 1;
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};
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u32 _u32;
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};
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union tDMAC_RBOR {
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struct {
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u32 ADDR : 31;
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u32 reserved1 : 1;
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};
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u32 _u32;
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};
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union tDMAC_STADR {
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struct {
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u32 ADDR : 31;
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u32 reserved1 : 1;
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};
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u32 _u32;
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};
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struct DMACregisters
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{
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tDMAC_CTRL ctrl;
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u32 padding[3];
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tDMAC_STAT stat;
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u32 padding1[3];
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tDMAC_PCR pcr;
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u32 padding2[3];
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tDMAC_SQWC sqwc;
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u32 padding3[3];
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tDMAC_RBSR rbsr;
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u32 padding4[3];
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tDMAC_RBOR rbor;
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u32 padding5[3];
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tDMAC_STADR stadr;
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};
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// Currently guesswork.
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union tINTC_STAT {
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struct {
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u32 interrupts : 10;
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u32 placeholder : 22;
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};
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u32 _u32;
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set(u32 flags) { _u32 |= flags; }
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void clear(u32 flags) { _u32 &= ~flags; }
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};
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union tINTC_MASK {
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struct {
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u32 int_mask : 10;
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u32 placeholder:22;
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};
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u32 _u32;
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};
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struct INTCregisters
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{
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tINTC_STAT stat;
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u32 padding[3];
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tINTC_MASK mask;
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};
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#define dmacRegs ((DMACregisters*)(PS2MEM_HW+0xE000))
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#define intcRegs ((INTCregisters*)(PS2MEM_HW+0xF000))
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#ifdef PCSX2_VIRTUAL_MEM
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#define dmaGetAddrBase(addr) (((addr) & 0x80000000) ? (void*)&PS2MEM_SCRATCH[(addr) & 0x3ff0] : (void*)(PS2MEM_BASE+TRANSFORM_ADDR(addr)))
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#ifdef _WIN32
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extern PSMEMORYMAP* memLUT;
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#endif
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// VM-version of dmaGetAddr -- Left in for references purposes for now (air)
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static __forceinline u8* dmaGetAddr(u32 mem)
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{
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u8* p, *pbase;
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mem &= ~0xf;
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if( (mem&0xffff0000) == 0x50000000 ) {// reserved scratch pad mem
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Console.WriteLn("dmaGetAddr: reserved scratch pad mem");
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return NULL;//(u8*)&PS2MEM_SCRATCH[(mem) & 0x3ff0];
|
|
}
|
|
|
|
p = (u8*)dmaGetAddrBase(mem);
|
|
|
|
#ifdef _WIN32
|
|
// do manual LUT since IPU/SPR seems to use addrs 0x3000xxxx quite often
|
|
// linux doesn't suffer from this because it has better vm support
|
|
if( memLUT[ (p-PS2MEM_BASE)>>12 ].aPFNs == NULL ) {
|
|
Console.WriteLn("dmaGetAddr: memLUT PFN warning");
|
|
return NULL;//p;
|
|
}
|
|
|
|
pbase = (u8*)memLUT[ (p-PS2MEM_BASE)>>12 ].aVFNs[0];
|
|
if( pbase != NULL ) p = pbase + ((u32)p&0xfff);
|
|
#endif
|
|
|
|
return p;
|
|
}
|
|
|
|
#else
|
|
|
|
// Note: Dma addresses are guaranteed to be aligned to 16 bytes (128 bits)
|
|
static __forceinline void *dmaGetAddr(u32 addr) {
|
|
u8 *ptr;
|
|
|
|
// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
|
|
|
|
// Need to check the physical address as well as just the "SPR" flag, as VTLB doesnt seem to handle it
|
|
if ((addr & 0x80000000) || (addr & 0x70000000) == 0x70000000) return (void*)&psS[addr & 0x3ff0];
|
|
|
|
ptr = (u8*)vtlb_GetPhyPtr(addr&0x1FFFFFF0);
|
|
if (ptr == NULL) {
|
|
Console.Error( "*PCSX2*: DMA error: %8.8x", addr);
|
|
return NULL;
|
|
}
|
|
return ptr;
|
|
}
|
|
|
|
#endif
|
|
|
|
static __forceinline u32 *_dmaGetAddr(DMACh *dma, u32 addr, u32 num)
|
|
{
|
|
u32 *ptr = (u32*)dmaGetAddr(addr);
|
|
if (ptr == NULL)
|
|
{
|
|
// DMA Error
|
|
dmacRegs->stat.BEIS = 1; // BUS Error
|
|
|
|
// DMA End
|
|
dmacRegs->stat.set(1 << num);
|
|
dma->chcr.STR = 0;
|
|
}
|
|
|
|
return ptr;
|
|
}
|
|
|
|
void hwInit();
|
|
void hwReset();
|
|
void hwShutdown();
|
|
|
|
// hw read functions
|
|
extern mem8_t hwRead8 (u32 mem);
|
|
extern mem16_t hwRead16(u32 mem);
|
|
|
|
extern mem32_t __fastcall hwRead32_page_00(u32 mem);
|
|
extern mem32_t __fastcall hwRead32_page_01(u32 mem);
|
|
extern mem32_t __fastcall hwRead32_page_02(u32 mem);
|
|
extern mem32_t __fastcall hwRead32_page_0F(u32 mem);
|
|
extern mem32_t __fastcall hwRead32_page_0F_INTC_HACK(u32 mem);
|
|
extern mem32_t __fastcall hwRead32_generic(u32 mem);
|
|
|
|
extern void __fastcall hwRead64_page_00(u32 mem, mem64_t* result );
|
|
extern void __fastcall hwRead64_page_01(u32 mem, mem64_t* result );
|
|
extern void __fastcall hwRead64_page_02(u32 mem, mem64_t* result );
|
|
extern void __fastcall hwRead64_generic_INTC_HACK(u32 mem, mem64_t *out);
|
|
extern void __fastcall hwRead64_generic(u32 mem, mem64_t* result );
|
|
|
|
extern void __fastcall hwRead128_page_00(u32 mem, mem128_t* result );
|
|
extern void __fastcall hwRead128_page_01(u32 mem, mem128_t* result );
|
|
extern void __fastcall hwRead128_page_02(u32 mem, mem128_t* result );
|
|
extern void __fastcall hwRead128_generic(u32 mem, mem128_t *out);
|
|
|
|
// hw write functions
|
|
extern void hwWrite8 (u32 mem, u8 value);
|
|
extern void hwWrite16(u32 mem, u16 value);
|
|
|
|
extern void __fastcall hwWrite32_page_00( u32 mem, mem32_t value );
|
|
extern void __fastcall hwWrite32_page_01( u32 mem, mem32_t value );
|
|
extern void __fastcall hwWrite32_page_02( u32 mem, mem32_t value );
|
|
extern void __fastcall hwWrite32_page_03( u32 mem, mem32_t value );
|
|
extern void __fastcall hwWrite32_page_0B( u32 mem, mem32_t value );
|
|
extern void __fastcall hwWrite32_page_0E( u32 mem, mem32_t value );
|
|
extern void __fastcall hwWrite32_page_0F( u32 mem, mem32_t value );
|
|
extern void __fastcall hwWrite32_generic( u32 mem, mem32_t value );
|
|
|
|
extern void __fastcall hwWrite64_page_00( u32 mem, const mem64_t* srcval );
|
|
extern void __fastcall hwWrite64_page_01( u32 mem, const mem64_t* srcval );
|
|
extern void __fastcall hwWrite64_page_02( u32 mem, const mem64_t* srcval );
|
|
extern void __fastcall hwWrite64_page_03( u32 mem, const mem64_t* srcval );
|
|
extern void __fastcall hwWrite64_page_0E( u32 mem, const mem64_t* srcval );
|
|
extern void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval );
|
|
|
|
extern void __fastcall hwWrite128_generic(u32 mem, const mem128_t *srcval);
|
|
|
|
void hwIntcIrq(int n);
|
|
void hwDmacIrq(int n);
|
|
|
|
//bool hwMFIFORead(u32 addr, u8 *data, u32 size);
|
|
bool hwMFIFOWrite(u32 addr, u8 *data, u32 size);
|
|
|
|
bool hwDmacSrcChainWithStack(DMACh *dma, int id);
|
|
bool hwDmacSrcChain(DMACh *dma, int id);
|
|
|
|
int hwConstRead8 (u32 x86reg, u32 mem, u32 sign);
|
|
int hwConstRead16(u32 x86reg, u32 mem, u32 sign);
|
|
int hwConstRead32(u32 x86reg, u32 mem);
|
|
void hwConstRead64(u32 mem, int mmreg);
|
|
void hwConstRead128(u32 mem, int xmmreg);
|
|
|
|
void hwConstWrite8 (u32 mem, int mmreg);
|
|
void hwConstWrite16(u32 mem, int mmreg);
|
|
void hwConstWrite32(u32 mem, int mmreg);
|
|
void hwConstWrite64(u32 mem, int mmreg);
|
|
void hwConstWrite128(u32 mem, int xmmreg);
|
|
|
|
extern void intcInterrupt();
|
|
extern void dmacInterrupt();
|
|
|
|
extern const int rdram_devices;
|
|
extern int rdram_sdevid;
|
|
|
|
#endif /* __HW_H__ */
|