mirror of https://github.com/PCSX2/pcsx2.git
257 lines
9.3 KiB
C++
257 lines
9.3 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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template< u16 OpcodeSSE >
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class SimdImpl_Shuffle
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{
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protected:
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template< u8 Prefix > struct Woot
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{
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__forceinline void operator()( const xRegisterSSE& to, const xRegisterSSE& from, u8 cmptype ) const { xOpWrite0F( Prefix, OpcodeSSE, to, from ); xWrite8( cmptype ); }
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__forceinline void operator()( const xRegisterSSE& to, const ModSibBase& from, u8 cmptype ) const { xOpWrite0F( Prefix, OpcodeSSE, to, from ); xWrite8( cmptype ); }
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Woot() {}
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};
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public:
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const Woot<0x00> PS;
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const Woot<0x66> PD;
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SimdImpl_Shuffle() {} //GCWhat?
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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class SimdImpl_PShuffle
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{
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public:
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SimdImpl_PShuffle() {}
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// Copies words from src and inserts them into dest at word locations selected with
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// the order operand (8 bit immediate).
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const SimdImpl_DestRegImmMMX<0x00,0x70> W;
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// Copies doublewords from src and inserts them into dest at dword locations selected
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// with the order operand (8 bit immediate).
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const SimdImpl_DestRegImmSSE<0x66,0x70> D;
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// Copies words from the low quadword of src and inserts them into the low quadword
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// of dest at word locations selected with the order operand (8 bit immediate).
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// The high quadword of src is copied to the high quadword of dest.
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const SimdImpl_DestRegImmSSE<0xf2,0x70> LW;
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// Copies words from the high quadword of src and inserts them into the high quadword
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// of dest at word locations selected with the order operand (8 bit immediate).
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// The low quadword of src is copied to the low quadword of dest.
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const SimdImpl_DestRegImmSSE<0xf3,0x70> HW;
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// [sSSE-3] Performs in-place shuffles of bytes in dest according to the shuffle
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// control mask in src. If the most significant bit (bit[7]) of each byte of the
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// shuffle control mask is set, then constant zero is written in the result byte.
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// Each byte in the shuffle control mask forms an index to permute the corresponding
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// byte in dest. The value of each index is the least significant 4 bits (128-bit
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// operation) or 3 bits (64-bit operation) of the shuffle control byte.
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//
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// Operands can be MMX or XMM registers.
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const SimdImpl_DestRegEither<0x66,0x0038> B;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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class SimdImpl_PUnpack
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{
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public:
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SimdImpl_PUnpack() {}
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// Unpack and interleave low-order bytes from src and dest into dest.
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const SimdImpl_DestRegEither<0x66,0x60> LBW;
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// Unpack and interleave low-order words from src and dest into dest.
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const SimdImpl_DestRegEither<0x66,0x61> LWD;
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// Unpack and interleave low-order doublewords from src and dest into dest.
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const SimdImpl_DestRegEither<0x66,0x62> LDQ;
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// Unpack and interleave low-order quadwords from src and dest into dest.
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const SimdImpl_DestRegSSE<0x66,0x6c> LQDQ;
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// Unpack and interleave high-order bytes from src and dest into dest.
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const SimdImpl_DestRegEither<0x66,0x68> HBW;
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// Unpack and interleave high-order words from src and dest into dest.
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const SimdImpl_DestRegEither<0x66,0x69> HWD;
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// Unpack and interleave high-order doublewords from src and dest into dest.
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const SimdImpl_DestRegEither<0x66,0x6a> HDQ;
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// Unpack and interleave high-order quadwords from src and dest into dest.
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const SimdImpl_DestRegSSE<0x66,0x6d> HQDQ;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// Pack with Signed or Unsigned Saturation
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//
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class SimdImpl_Pack
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{
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public:
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SimdImpl_Pack() {}
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// Converts packed signed word integers from src and dest into packed signed
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// byte integers in dest, using signed saturation.
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const SimdImpl_DestRegEither<0x66,0x63> SSWB;
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// Converts packed signed dword integers from src and dest into packed signed
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// word integers in dest, using signed saturation.
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const SimdImpl_DestRegEither<0x66,0x6b> SSDW;
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// Converts packed unsigned word integers from src and dest into packed unsigned
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// byte integers in dest, using unsigned saturation.
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const SimdImpl_DestRegEither<0x66,0x67> USWB;
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// [SSE-4.1] Converts packed unsigned dword integers from src and dest into packed
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// unsigned word integers in dest, using signed saturation.
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const SimdImpl_DestRegSSE<0x66,0x2b38> USDW;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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class SimdImpl_Unpack
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{
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public:
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SimdImpl_Unpack() {}
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// Unpacks the high doubleword [single-precision] values from src and dest into
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// dest, such that the result of dest looks like this:
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// dest[0] <- dest[2]
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// dest[1] <- src[2]
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// dest[2] <- dest[3]
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// dest[3] <- src[3]
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//
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const SimdImpl_DestRegSSE<0x00,0x15> HPS;
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// Unpacks the high quadword [double-precision] values from src and dest into
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// dest, such that the result of dest looks like this:
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// dest.lo <- dest.hi
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// dest.hi <- src.hi
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//
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const SimdImpl_DestRegSSE<0x66,0x15> HPD;
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// Unpacks the low doubleword [single-precision] values from src and dest into
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// dest, such that the result of dest looks like this:
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// dest[3] <- src[1]
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// dest[2] <- dest[1]
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// dest[1] <- src[0]
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// dest[0] <- dest[0]
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//
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const SimdImpl_DestRegSSE<0x00,0x14> LPS;
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// Unpacks the low quadword [double-precision] values from src and dest into
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// dest, effectively moving the low portion of src into the upper portion of dest.
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// The result of dest is loaded as such:
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// dest.hi <- src.lo
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// dest.lo <- dest.lo [remains unchanged!]
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//
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const SimdImpl_DestRegSSE<0x66,0x14> LPD;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// PINSRW/B/D [all but Word form are SSE4.1 only!]
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//
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class SimdImpl_PInsert
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{
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protected:
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template< u16 Opcode >
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class ByteDwordForms
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{
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public:
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ByteDwordForms() {}
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__forceinline void operator()( const xRegisterSSE& to, const xRegister32& from, u8 imm8 ) const
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{
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xOpWrite0F( 0x66, (Opcode<<8) | 0x3a, to, from, imm8 );
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}
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__forceinline void operator()( const xRegisterSSE& to, const ModSibBase& from, u8 imm8 ) const
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{
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xOpWrite0F( 0x66, (Opcode<<8) | 0x3a, to, from, imm8 );
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}
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};
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public:
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SimdImpl_PInsert() {}
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// Operation can be performed on either MMX or SSE src operands.
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__forceinline void W( const xRegisterSSE& to, const xRegister32& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0xc4, to, from, imm8 ); }
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__forceinline void W( const xRegisterSSE& to, const ModSibBase& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0xc4, to, from, imm8 ); }
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__forceinline void W( const xRegisterMMX& to, const xRegister32& from, u8 imm8 ) const { xOpWrite0F( 0xc4, to, from, imm8 ); }
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__forceinline void W( const xRegisterMMX& to, const ModSibBase& from, u8 imm8 ) const { xOpWrite0F( 0xc4, to, from, imm8 ); }
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// [SSE-4.1]
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const ByteDwordForms<0x20> B;
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// [SSE-4.1]
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const ByteDwordForms<0x22> D;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// PEXTRW/B/D [all but Word form are SSE4.1 only!]
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//
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// Note: Word form's indirect memory form is only available in SSE4.1.
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//
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class SimdImpl_PExtract
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{
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protected:
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template< u16 Opcode >
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class ByteDwordForms
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{
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public:
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ByteDwordForms() {}
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__forceinline void operator()( const xRegister32& to, const xRegisterSSE& from, u8 imm8 ) const
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{
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xOpWrite0F( 0x66, (Opcode<<8) | 0x3a, to, from, imm8 );
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}
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__forceinline void operator()( const ModSibBase& dest, const xRegisterSSE& from, u8 imm8 ) const
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{
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xOpWrite0F( 0x66, (Opcode<<8) | 0x3a, from, dest, imm8 );
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}
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};
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public:
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SimdImpl_PExtract() {}
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// Copies the word element specified by imm8 from src to dest. The upper bits
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// of dest are zero-extended (cleared). This can be used to extract any single packed
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// word value from src into an x86 32 bit register.
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//
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// [SSE-4.1] Note: Indirect memory forms of this instruction are an SSE-4.1 extension!
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//
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__forceinline void W( const xRegister32& to, const xRegisterSSE& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0xc5, to, from, imm8 ); }
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__forceinline void W( const xRegister32& to, const xRegisterMMX& from, u8 imm8 ) const { xOpWrite0F( 0xc5, to, from, imm8 ); }
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__forceinline void W( const ModSibBase& dest, const xRegisterSSE& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0x153a, from, dest, imm8 ); }
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// [SSE-4.1] Copies the byte element specified by imm8 from src to dest. The upper bits
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// of dest are zero-extended (cleared). This can be used to extract any single packed
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// byte value from src into an x86 32 bit register.
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const ByteDwordForms<0x14> B;
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// [SSE-4.1] Copies the dword element specified by imm8 from src to dest. This can be
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// used to extract any single packed dword value from src into an x86 32 bit register.
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const ByteDwordForms<0x16> D;
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};
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