mirror of https://github.com/PCSX2/pcsx2.git
552 lines
13 KiB
C++
552 lines
13 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "SPR.h"
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#include "VUmicro.h"
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#include "MTVU.h"
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static bool spr0finished = false;
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static bool spr1finished = false;
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static u32 mfifotransferred = 0;
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static void TestClearVUs(u32 madr, u32 qwc, bool isWrite)
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{
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if (madr >= 0x11000000 && (madr < 0x11010000))
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{
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// Access to VU memory is only allowed when the VU is stopped
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// Use Psychonauts for testing
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if ((madr < 0x11008000) && (VU0.VI[REG_VPU_STAT].UL & 0x1))
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{
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_vu0FinishMicro();
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//Catch up VU1 too
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CpuVU1->ExecuteBlock(0);
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}
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if ((madr >= 0x11008000) && (VU0.VI[REG_VPU_STAT].UL & 0x100) && (!THREAD_VU1 || !isWrite))
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{
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if (THREAD_VU1)
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vu1Thread.WaitVU();
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else
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CpuVU1->Execute(vu1RunCycles);
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cpuRegs.cycle = VU1.cycle;
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//Catch up VU0 too
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CpuVU0->ExecuteBlock(0);
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}
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if (madr < 0x11004000)
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{
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if(isWrite)
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{
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DbgCon.Warning("scratch pad clearing vu0");
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CpuVU0->Clear(madr&0xfff, qwc * 16);
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}
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if(((madr & 0xff0) + (qwc * 16)) > 0x1000 )
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{
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DevCon.Warning("Warning! SPR%d Crossing in to VU0 Micro Mirror address! Start MADR = %x, End MADR = %x", isWrite ? 0 : 1, madr, madr + (qwc * 16));
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}
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}
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else if (madr >= 0x11008000 && madr < 0x1100c000)
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{
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if(isWrite)
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{
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DbgCon.Warning("scratch pad clearing vu1");
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CpuVU1->Clear(madr&0x3fff, qwc * 16);
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}
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}
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else if (madr >= 0x11004000 && madr < 0x11008000)
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{
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// SPR trying to write to to VU0 Mem mirror address.
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if(((madr & 0xff0) + (qwc * 16)) > 0x1000)
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{
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DevCon.Warning("Warning! SPR%d Crossing in to VU0 Mem Mirror address! Start MADR = %x, End MADR = %x", isWrite ? 0 : 1, madr, madr + (qwc * 16));
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}
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}
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}
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}
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static void memcpy_to_spr(u32 dst, u8* src, size_t size)
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{
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dst &= _16kb - 1;
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if (dst + size >= _16kb) {
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size_t end = _16kb - dst;
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memcpy(&psSu128(dst), src, end);
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src += end;
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memcpy(&psSu128(0) , src, size - end);
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} else {
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memcpy(&psSu128(dst), src, size);
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}
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}
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static void memcpy_from_spr(u8* dst, u32 src, size_t size)
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{
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src &= _16kb - 1;
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if (src + size >= _16kb) {
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size_t end = _16kb - src;
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memcpy(dst, &psSu128(src), end);
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dst += end;
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memcpy(dst, &psSu128(0) , size - end);
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} else {
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memcpy(dst, &psSu128(src), size);
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}
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}
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int _SPR0chain()
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{
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tDMA_TAG *pMem;
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int partialqwc = 0;
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if (spr0ch.qwc == 0) return 0;
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pMem = SPRdmaGetAddr(spr0ch.madr, true);
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if (pMem == NULL) return -1;
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if(spr0ch.madr >= dmacRegs.rbor.ADDR && spr0ch.madr < (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16u))
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{
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if (dmacRegs.rbsr.RMSK == 0) // Shortcut when MFIFO isn't set up with a size (Hitman series)
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{
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spr0ch.madr += spr0ch.qwc << 4;
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spr0ch.sadr += spr0ch.qwc << 4;
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spr0ch.sadr &= 0x3FFF; // Limited to 16K
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spr0ch.qwc = 0;
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}
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else
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{
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partialqwc = std::min(spr0ch.qwc, 0x400 - ((spr0ch.sadr & 0x3fff) >> 4));
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if ((spr0ch.madr & ~dmacRegs.rbsr.RMSK) != dmacRegs.rbor.ADDR)
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Console.WriteLn("SPR MFIFO Write outside MFIFO area");
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else
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mfifotransferred += partialqwc;
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hwMFIFOWrite(spr0ch.madr, &psSu128(spr0ch.sadr), partialqwc);
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spr0ch.madr += partialqwc << 4;
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spr0ch.madr = dmacRegs.rbor.ADDR + (spr0ch.madr & dmacRegs.rbsr.RMSK);
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spr0ch.sadr += partialqwc << 4;
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spr0ch.sadr &= 0x3FFF; // Limited to 16K
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spr0ch.qwc -= partialqwc;
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}
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spr0finished = true;
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}
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else
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{
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// Taking an arbitary small value for games which like to check the QWC/MADR instead of STR, so get most of
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// the cycle delay out of the way before the end.
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partialqwc = std::min(spr0ch.qwc, 0x400 - ((spr0ch.sadr & 0x3fff) >> 4));
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memcpy_from_spr((u8*)pMem, spr0ch.sadr, partialqwc*16);
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// Clear VU mem also!
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TestClearVUs(spr0ch.madr, partialqwc, true);
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spr0ch.madr += partialqwc << 4;
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spr0ch.sadr += partialqwc << 4;
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spr0ch.sadr &= 0x3FFF; // Limited to 16K
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spr0ch.qwc -= partialqwc;
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}
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if (spr0ch.qwc == 0 && dmacRegs.ctrl.STS == STS_fromSPR)
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{
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if (spr0ch.chcr.MOD == NORMAL_MODE || ((spr0ch.chcr.TAG >> 28) & 0x7) == TAG_CNTS)
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{
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//DevCon.Warning("SPR0 %s Stall Control", spr0ch.chcr.MOD == NORMAL_MODE ? "Normal" : "Chain");
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dmacRegs.stadr.ADDR = spr0ch.madr; // Copy MADR to DMAC_STADR stall addr register
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}
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}
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return (partialqwc); // Bus is 1/2 the ee speed
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}
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__fi void SPR0chain()
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{
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int cycles = _SPR0chain() * BIAS;
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CPU_INT(DMAC_FROM_SPR, cycles);
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}
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void _SPR0interleave()
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{
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int qwc = spr0ch.qwc;
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int sqwc = dmacRegs.sqwc.SQWC;
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int tqwc = dmacRegs.sqwc.TQWC;
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tDMA_TAG *pMem;
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if (tqwc == 0) tqwc = qwc;
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//Console.WriteLn("dmaSPR0 interleave");
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SPR_LOG("SPR0 interleave size=%d, tqwc=%d, sqwc=%d, addr=%lx sadr=%lx",
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spr0ch.qwc, tqwc, sqwc, spr0ch.madr, spr0ch.sadr);
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CPU_INT(DMAC_FROM_SPR, qwc * BIAS);
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while (qwc > 0)
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{
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spr0ch.qwc = std::min(tqwc, qwc);
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qwc -= spr0ch.qwc;
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pMem = SPRdmaGetAddr(spr0ch.madr, true);
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if(spr0ch.qwc > (0x400 - ((spr0ch.sadr & 0x3fff) >> 4)))
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DevCon.Warning("Warning! Interleave on SPR0 going outside of SPR memory!");
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switch (dmacRegs.ctrl.MFD)
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{
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case MFD_VIF1:
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case MFD_GIF:
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hwMFIFOWrite(spr0ch.madr, &psSu128(spr0ch.sadr), spr0ch.qwc);
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mfifotransferred += spr0ch.qwc;
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break;
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case NO_MFD:
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case MFD_RESERVED:
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// Clear VU mem also!
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TestClearVUs(spr0ch.madr, spr0ch.qwc, true);
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memcpy_from_spr((u8*)pMem, spr0ch.sadr, spr0ch.qwc*16);
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break;
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}
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spr0ch.sadr += spr0ch.qwc * 16;
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spr0ch.sadr &= 0x3FFF; // Limited to 16K
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spr0ch.madr += (sqwc + spr0ch.qwc) * 16;
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}
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if (dmacRegs.ctrl.STS == STS_fromSPR)
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{
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//DevCon.Warning("SPR0 Interleave Stall Control");
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dmacRegs.stadr.ADDR = spr0ch.madr; // Copy MADR to DMAC_STADR stall addr register
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}
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spr0ch.qwc = 0;
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}
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static __fi void _dmaSPR0()
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{
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// Transfer Dn_QWC from SPR to Dn_MADR
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switch(spr0ch.chcr.MOD)
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{
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case NORMAL_MODE:
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{
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if (dmacRegs.ctrl.STS == STS_fromSPR) // STS == fromSPR
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{
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dmacRegs.stadr.ADDR = spr0ch.madr;
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}
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SPR0chain();
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spr0finished = true;
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return;
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}
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case CHAIN_MODE:
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{
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tDMA_TAG *ptag;
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bool done = false;
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if (spr0ch.qwc > 0)
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{
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SPR0chain();
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return;
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}
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// Destination Chain Mode
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ptag = (tDMA_TAG*)&psSu32(spr0ch.sadr);
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spr0ch.sadr += 16;
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spr0ch.sadr &= 0x3FFF; // Limited to 16K
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spr0ch.unsafeTransfer(ptag);
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spr0ch.madr = ptag[1]._u32; // MADR = ADDR field + SPR
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SPR_LOG("spr0 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx",
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ptag[1]._u32, ptag[0]._u32, spr0ch.qwc, ptag->ID, spr0ch.madr, spr0ch.sadr);
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switch (ptag->ID)
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{
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case TAG_CNTS: // CNTS - Transfer QWC following the tag (Stall Control)
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if (dmacRegs.ctrl.STS == STS_fromSPR) // STS == fromSPR - Initial Value
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{
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dmacRegs.stadr.ADDR = spr0ch.madr;
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}
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break;
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case TAG_CNT: // CNT - Transfer QWC following the tag.
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done = false;
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break;
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case TAG_END: // End - Transfer QWC following the tag
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done = true;
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break;
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}
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SPR0chain();
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if (spr0ch.chcr.TIE && ptag->IRQ) // Check TIE bit of CHCR and IRQ bit of tag
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{
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//Console.WriteLn("SPR0 TIE");
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done = true;
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}
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spr0finished = done;
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SPR_LOG("spr0 dmaChain complete %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx",
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ptag[1]._u32, ptag[0]._u32, spr0ch.qwc, ptag->ID, spr0ch.madr);
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break;
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}
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//case INTERLEAVE_MODE:
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default:
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{
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_SPR0interleave();
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spr0finished = true;
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break;
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}
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}
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}
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void SPRFROMinterrupt()
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{
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if (!spr0finished || spr0ch.qwc > 0)
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{
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_dmaSPR0();
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// The qwc check is simply because having data still to transfer from the packet can freak games out if they do a d.tadr == s.madr check
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// and there is still data to come over (FF12 ingame menu)
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if(mfifotransferred != 0 && spr0ch.qwc == 0)
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{
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switch (dmacRegs.ctrl.MFD)
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{
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case MFD_VIF1: // Most common case.
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case MFD_GIF:
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{
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if ((spr0ch.madr & ~dmacRegs.rbsr.RMSK) != dmacRegs.rbor.ADDR) Console.WriteLn("GIF MFIFO Write outside MFIFO area");
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spr0ch.madr = dmacRegs.rbor.ADDR + (spr0ch.madr & dmacRegs.rbsr.RMSK);
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//Console.WriteLn("mfifoGIFtransfer %x madr %x, tadr %x", gif->chcr._u32, gif->madr, gif->tadr);
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hwMFIFOResume(mfifotransferred);
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break;
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}
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default:
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break;
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}
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mfifotransferred = 0;
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}
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return;
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}
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spr0ch.chcr.STR = false;
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hwDmacIrq(DMAC_FROM_SPR);
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DMA_LOG("SPR0 DMA End");
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}
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void dmaSPR0() // fromSPR
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{
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SPR_LOG("dmaSPR0 chcr = %lx, madr = %lx, qwc = %lx, sadr = %lx",
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spr0ch.chcr._u32, spr0ch.madr, spr0ch.qwc, spr0ch.sadr);
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spr0finished = false; //Init
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if(spr0ch.chcr.MOD == CHAIN_MODE && spr0ch.qwc > 0)
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{
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//DevCon.Warning(L"SPR0 QWC on Chain " + spr0ch.chcr.desc());
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if (spr0ch.chcr.tag().ID == TAG_END) // But not TAG_REFE?
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{ // correct not REFE, Destination Chain doesnt have REFE!
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spr0finished = true;
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}
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}
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SPRFROMinterrupt();
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}
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__fi static void SPR1transfer(const void* data, int qwc)
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{
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if ((spr1ch.madr >= 0x11000000) && (spr1ch.madr < 0x11010000))
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{
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TestClearVUs(spr1ch.madr, spr1ch.qwc, false);
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}
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memcpy_to_spr(spr1ch.sadr, (u8*)data, qwc*16);
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spr1ch.sadr += qwc * 16;
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spr1ch.sadr &= 0x3FFF; // Limited to 16K
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}
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int _SPR1chain()
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{
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tDMA_TAG *pMem;
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if (spr1ch.qwc == 0) return 0;
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pMem = SPRdmaGetAddr(spr1ch.madr, false);
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if (pMem == NULL) return -1;
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int partialqwc = 0;
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// Taking an arbitary small value for games which like to check the QWC/MADR instead of STR, so get most of
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// the cycle delay out of the way before the end.
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partialqwc = std::min(spr1ch.qwc, 0x400u);
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SPR1transfer(pMem, partialqwc);
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spr1ch.madr += partialqwc * 16;
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spr1ch.qwc -= partialqwc;
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hwDmacSrcTadrInc(spr1ch);
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return (partialqwc);
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}
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__fi void SPR1chain()
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{
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int cycles = 0;
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cycles = _SPR1chain() * BIAS;
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CPU_INT(DMAC_TO_SPR, cycles);
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}
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void _SPR1interleave()
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{
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int qwc = spr1ch.qwc;
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int sqwc = dmacRegs.sqwc.SQWC;
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int tqwc = dmacRegs.sqwc.TQWC;
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tDMA_TAG *pMem;
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if (tqwc == 0) tqwc = qwc;
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SPR_LOG("SPR1 interleave size=%d, tqwc=%d, sqwc=%d, addr=%lx sadr=%lx",
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spr1ch.qwc, tqwc, sqwc, spr1ch.madr, spr1ch.sadr);
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CPU_INT(DMAC_TO_SPR, qwc * BIAS);
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while (qwc > 0)
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{
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spr1ch.qwc = std::min(tqwc, qwc);
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qwc -= spr1ch.qwc;
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pMem = SPRdmaGetAddr(spr1ch.madr, false);
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memcpy_to_spr(spr1ch.sadr, (u8*)pMem, spr1ch.qwc*16);
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spr1ch.sadr += spr1ch.qwc * 16;
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spr1ch.sadr &= 0x3FFF; // Limited to 16K
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spr1ch.madr += (sqwc + spr1ch.qwc) * 16;
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}
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spr1ch.qwc = 0;
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}
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void _dmaSPR1() // toSPR work function
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{
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switch(spr1ch.chcr.MOD)
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{
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case NORMAL_MODE:
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{
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//int cycles = 0;
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// Transfer Dn_QWC from Dn_MADR to SPR1
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SPR1chain();
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spr1finished = true;
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return;
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}
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case CHAIN_MODE:
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{
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tDMA_TAG *ptag;
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bool done = false;
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if (spr1ch.qwc > 0)
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{
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SPR_LOG("spr1 Normal or in Progress size=%d, addr=%lx taddr=%lx saddr=%lx", spr1ch.qwc, spr1ch.madr, spr1ch.tadr, spr1ch.sadr);
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// Transfer Dn_QWC from Dn_MADR to SPR1
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SPR1chain();
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return;
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}
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// Chain Mode
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ptag = SPRdmaGetAddr(spr1ch.tadr, false); // Set memory pointer to TADR
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if (!spr1ch.transfer("SPR1 Tag", ptag))
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{
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done = true;
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spr1finished = done;
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}
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spr1ch.madr = ptag[1]._u32; // MADR = ADDR field + SPR
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// Transfer dma tag if tte is set
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if (spr1ch.chcr.TTE)
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{
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SPR_LOG("SPR TTE: %x_%x\n", ptag[3]._u32, ptag[2]._u32);
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SPR1transfer(ptag, 1); // Transfer Tag
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|
}
|
|
|
|
SPR_LOG("spr1 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx taddr=%lx saddr=%lx",
|
|
ptag[1]._u32, ptag[0]._u32, spr1ch.qwc, ptag->ID, spr1ch.madr, spr1ch.tadr, spr1ch.sadr);
|
|
|
|
done = hwDmacSrcChain(spr1ch, ptag->ID);
|
|
SPR1chain(); // Transfers the data set by the switch
|
|
|
|
if (spr1ch.chcr.TIE && ptag->IRQ) // Check TIE bit of CHCR and IRQ bit of tag
|
|
{
|
|
SPR_LOG("dmaIrq Set");
|
|
|
|
//Console.WriteLn("SPR1 TIE");
|
|
done = true;
|
|
}
|
|
|
|
spr1finished = done;
|
|
break;
|
|
}
|
|
//case INTERLEAVE_MODE:
|
|
default:
|
|
{
|
|
_SPR1interleave();
|
|
spr1finished = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void dmaSPR1() // toSPR
|
|
{
|
|
SPR_LOG("dmaSPR1 chcr = 0x%x, madr = 0x%x, qwc = 0x%x\n"
|
|
" tadr = 0x%x, sadr = 0x%x",
|
|
spr1ch.chcr._u32, spr1ch.madr, spr1ch.qwc,
|
|
spr1ch.tadr, spr1ch.sadr);
|
|
|
|
spr1finished = false; // Init
|
|
|
|
if(spr1ch.chcr.MOD == CHAIN_MODE && spr1ch.qwc > 0)
|
|
{
|
|
//DevCon.Warning(L"SPR1 QWC on Chain " + spr1ch.chcr.desc());
|
|
if ((spr1ch.chcr.tag().ID == TAG_END) || (spr1ch.chcr.tag().ID == TAG_REFE) || (spr1ch.chcr.tag().IRQ && spr1ch.chcr.TIE))
|
|
{
|
|
spr1finished = true;
|
|
}
|
|
}
|
|
|
|
SPRTOinterrupt();
|
|
}
|
|
|
|
void SPRTOinterrupt()
|
|
{
|
|
SPR_LOG("SPR1 Interrupt");
|
|
if (!spr1finished || spr1ch.qwc > 0)
|
|
{
|
|
_dmaSPR1();
|
|
return;
|
|
}
|
|
|
|
DMA_LOG("SPR1 DMA End");
|
|
spr1ch.chcr.STR = false;
|
|
hwDmacIrq(DMAC_TO_SPR);
|
|
}
|
|
|
|
void SaveStateBase::sprFreeze()
|
|
{
|
|
FreezeTag("SPRdma");
|
|
|
|
Freeze(spr0finished);
|
|
Freeze(spr1finished);
|
|
Freeze(mfifotransferred);
|
|
}
|