mirror of https://github.com/PCSX2/pcsx2.git
822 lines
25 KiB
C++
822 lines
25 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include <time.h>
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#include <cmath>
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#include "R3000A.h"
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#include "Counters.h"
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#include "IopCounters.h"
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#include "GS.h"
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#include "VUmicro.h"
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using namespace Threading;
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extern u8 psxhblankgate;
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extern void ApplyPatch( int place = 1);
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static const uint EECNT_FUTURE_TARGET = 0x10000000;
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u64 profile_starttick = 0;
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u64 profile_totalticks = 0;
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int gates = 0;
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// Counter 4 takes care of scanlines - hSync/hBlanks
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// Counter 5 takes care of vSync/vBlanks
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Counter counters[4];
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SyncCounter hsyncCounter;
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SyncCounter vsyncCounter;
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u32 nextsCounter; // records the cpuRegs.cycle value of the last call to rcntUpdate()
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s32 nextCounter; // delta from nextsCounter, in cycles, until the next rcntUpdate()
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void rcntReset(int index) {
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counters[index].count = 0;
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counters[index].sCycleT = cpuRegs.cycle;
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}
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// Updates the state of the nextCounter value (if needed) to serve
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// any pending events for the given counter.
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// Call this method after any modifications to the state of a counter.
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static __forceinline void _rcntSet( int cntidx )
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{
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s32 c;
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jASSUME( cntidx <= 4 ); // rcntSet isn't valid for h/vsync counters.
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const Counter& counter = counters[cntidx];
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// Stopped or special hsync gate?
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if (!counter.mode.IsCounting || (counter.mode.ClockSource == 0x3) ) return;
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// check for special cases where the overflow or target has just passed
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// (we probably missed it because we're doing/checking other things)
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if( counter.count > 0x10000 || counter.count > counter.target )
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{
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nextCounter = 4;
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return;
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}
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// nextCounter is relative to the cpuRegs.cycle when rcntUpdate() was last called.
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// However, the current _rcntSet could be called at any cycle count, so we need to take
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// that into account. Adding the difference from that cycle count to the current one
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// will do the trick!
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c = ((0x10000 - counter.count) * counter.rate) - (cpuRegs.cycle - counter.sCycleT);
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c += cpuRegs.cycle - nextsCounter; // adjust for time passed since last rcntUpdate();
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if (c < nextCounter)
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{
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nextCounter = c;
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cpuSetNextBranch( nextsCounter, nextCounter ); //Need to update on counter resets/target changes
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}
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// Ignore target diff if target is currently disabled.
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// (the overflow is all we care about since it goes first, and then the
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// target will be turned on afterward, and handled in the next event test).
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if( counter.target & EECNT_FUTURE_TARGET )
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{
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return;
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}
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else
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{
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c = ((counter.target - counter.count) * counter.rate) - (cpuRegs.cycle - counter.sCycleT);
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c += cpuRegs.cycle - nextsCounter; // adjust for time passed since last rcntUpdate();
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if (c < nextCounter)
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{
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nextCounter = c;
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cpuSetNextBranch( nextsCounter, nextCounter ); //Need to update on counter resets/target changes
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}
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}
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}
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static __forceinline void cpuRcntSet()
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{
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int i;
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nextsCounter = cpuRegs.cycle;
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nextCounter = vsyncCounter.CycleT - (cpuRegs.cycle - vsyncCounter.sCycle);
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for (i = 0; i < 4; i++)
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_rcntSet( i );
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// sanity check!
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if( nextCounter < 0 ) nextCounter = 0;
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}
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void rcntInit() {
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int i;
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memzero(counters);
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for (i=0; i<4; i++) {
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counters[i].rate = 2;
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counters[i].target = 0xffff;
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}
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counters[0].interrupt = 9;
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counters[1].interrupt = 10;
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counters[2].interrupt = 11;
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counters[3].interrupt = 12;
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hsyncCounter.Mode = MODE_HRENDER;
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hsyncCounter.sCycle = cpuRegs.cycle;
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vsyncCounter.Mode = MODE_VRENDER;
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vsyncCounter.sCycle = cpuRegs.cycle;
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UpdateVSyncRate();
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for (i=0; i<4; i++) rcntReset(i);
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cpuRcntSet();
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}
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// debug code, used for stats
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int g_nhsyncCounter;
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static uint iFrame = 0;
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#ifndef _WIN32
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#include <sys/time.h>
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#endif
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static s64 m_iTicks=0;
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static u64 m_iStart=0;
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struct vSyncTimingInfo
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{
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u32 Framerate; // frames per second * 100 (so 2500 for PAL and 2997 for NTSC)
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u32 Render; // time from vblank end to vblank start (cycles)
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u32 Blank; // time from vblank start to vblank end (cycles)
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u32 hSyncError; // rounding error after the duration of a rendered frame (cycles)
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u32 hRender; // time from hblank end to hblank start (cycles)
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u32 hBlank; // time from hblank start to hblank end (cycles)
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u32 hScanlinesPerFrame; // number of scanlines per frame (525/625 for NTSC/PAL)
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};
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static vSyncTimingInfo vSyncInfo;
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static void vSyncInfoCalc( vSyncTimingInfo* info, u32 framesPerSecond, u32 scansPerFrame )
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{
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// Important: Cannot use floats or doubles here. The emulator changes rounding modes
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// depending on user-set speedhack options, and it can break float/double code
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// (as in returning infinities and junk)
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// NOTE: mgs3 likes a /4 vsync, but many games prefer /2. This seems to indicate a
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// problem in the counters vsync gates somewhere.
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u64 Frame = ((u64)PS2CLK * 1000000ULL) / framesPerSecond;
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u64 HalfFrame = Frame / 2;
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u64 Blank = HalfFrame / 2; // two blanks and renders per frame
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u64 Render = HalfFrame - Blank; // so use the half-frame value for these...
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// Important! The hRender/hBlank timers should be 50/50 for best results.
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// In theory a 70%/30% ratio would be more correct but in practice it runs
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// like crap and totally screws audio synchronization and other things.
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u64 Scanline = Frame / scansPerFrame;
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u64 hBlank = Scanline / 2;
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u64 hRender = Scanline - hBlank;
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info->Framerate = framesPerSecond;
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info->Render = (u32)(Render/10000);
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info->Blank = (u32)(Blank/10000);
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info->hRender = (u32)(hRender/10000);
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info->hBlank = (u32)(hBlank/10000);
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info->hScanlinesPerFrame = scansPerFrame;
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// Apply rounding:
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if( ( Render - info->Render ) >= 5000 ) info->Render++;
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else if( ( Blank - info->Blank ) >= 5000 ) info->Blank++;
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if( ( hRender - info->hRender ) >= 5000 ) info->hRender++;
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else if( ( hBlank - info->hBlank ) >= 5000 ) info->hBlank++;
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// Calculate accumulative hSync rounding error per half-frame:
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{
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u32 hSyncCycles = ((info->hRender + info->hBlank) * scansPerFrame) / 2;
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u32 vSyncCycles = (info->Render + info->Blank);
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info->hSyncError = vSyncCycles - hSyncCycles;
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}
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// Note: In NTSC modes there is some small rounding error in the vsync too,
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// however it would take thousands of frames for it to amount to anything and
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// is thus not worth the effort at this time.
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}
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u32 UpdateVSyncRate()
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{
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static const char *limiterMsg = "Framelimiter rate updated (UpdateVSyncRate): %d.%d fps";
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// fixme - According to some docs, progressive-scan modes actually refresh slower than
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// interlaced modes. But I can't fathom how, since the refresh rate is a function of
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// the television and all the docs I found on TVs made no indication that they ever
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// run anything except their native refresh rate.
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//#define VBLANK_NTSC ((Config.PsxType & 2) ? 59.94 : 59.82) //59.94 is more precise
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//#define VBLANK_PAL ((Config.PsxType & 2) ? 50.00 : 49.76)
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if( gsRegionMode == Region_PAL )
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{
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if( vSyncInfo.Framerate != FRAMERATE_PAL )
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vSyncInfoCalc( &vSyncInfo, FRAMERATE_PAL, SCANLINES_TOTAL_PAL );
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}
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else
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{
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if( vSyncInfo.Framerate != FRAMERATE_NTSC )
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vSyncInfoCalc( &vSyncInfo, FRAMERATE_NTSC, SCANLINES_TOTAL_NTSC );
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}
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hsyncCounter.CycleT = vSyncInfo.hRender; // Amount of cycles before the counter will be updated
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vsyncCounter.CycleT = vSyncInfo.Render; // Amount of cycles before the counter will be updated
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if( EmuConfig.Video.EnableFrameLimiting && (EmuConfig.Video.FpsLimit > 0) )
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{
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s64 ticks = GetTickFrequency() / EmuConfig.Video.FpsLimit;
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if( m_iTicks != ticks )
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{
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m_iTicks = ticks;
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gsOnModeChanged( vSyncInfo.Framerate, m_iTicks );
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Console.WriteLn( limiterMsg, EmuConfig.Video.FpsLimit, 0 );
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}
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}
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else
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{
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s64 ticks = (GetTickFrequency() * 50) / vSyncInfo.Framerate;
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if( m_iTicks != ticks )
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{
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m_iTicks = ticks;
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gsOnModeChanged( vSyncInfo.Framerate, m_iTicks );
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Console.WriteLn( limiterMsg, vSyncInfo.Framerate/50, (vSyncInfo.Framerate*2)%100 );
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}
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}
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m_iStart = GetCPUTicks();
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cpuRcntSet();
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return (u32)m_iTicks;
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}
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void frameLimitReset()
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{
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m_iStart = GetCPUTicks();
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}
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// Framelimiter - Measures the delta time between calls and stalls until a
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// certain amount of time passes if such time hasn't passed yet.
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// See the GS FrameSkip function for details on why this is here and not in the GS.
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extern int limitOn;
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static __forceinline void frameLimit()
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{
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// 999 means the user would rather just have framelimiting turned off...
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if( /*!EmuConfig.Video.EnableFrameLimiting*/ !limitOn || EmuConfig.Video.FpsLimit >= 999 ) return;
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s64 sDeltaTime;
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u64 uExpectedEnd;
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u64 iEnd;
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uExpectedEnd = m_iStart + m_iTicks;
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iEnd = GetCPUTicks();
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sDeltaTime = iEnd - uExpectedEnd;
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// If the framerate drops too low, reset the expected value. This avoids
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// excessive amounts of "fast forward" syndrome which would occur if we
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// tried to catch up too much.
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if( sDeltaTime > m_iTicks*8 )
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{
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m_iStart = iEnd - m_iTicks;
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// Let the GS Skipper know we lost time.
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// Keeps the GS skipper from trying to catch up to a framerate
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// that the limiter already gave up on.
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gsSyncLimiterLostTime( (s32)(m_iStart - uExpectedEnd) );
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return;
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}
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// use the expected frame completion time as our starting point.
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// improves smoothness by making the framelimiter more adaptive to the
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// imperfect TIMESLICE() wait, and allows it to speed up a wee bit after
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// slow frames to "catch up."
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m_iStart = uExpectedEnd;
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// Shortcut for cases where no waiting is needed (they're running slow already,
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// so don't bog 'em down with extra math...)
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if( sDeltaTime >= 0 ) return;
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// If we're way ahead then we can afford to sleep the thread a bit.
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// (note, sleep(1) thru sleep(2) tend to be the least accurate sleeps, and longer
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// sleeps tend to be pretty reliable, so that's why the convoluted if/else below)
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s32 msec = (int)((sDeltaTime*-1000) / (s64)GetTickFrequency());
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if( msec > 4 ) Threading::Sleep( msec );
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else if( msec > 2 ) Threading::Sleep( 1 );
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// Sleep is not picture-perfect accurate, but it's actually not necessary to
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// maintain a "perfect" lock to uExpectedEnd anyway. if we're a little ahead
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// starting this frame, it'll just sleep longer the next to make up for it. :)
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}
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static __forceinline void VSyncStart(u32 sCycle)
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{
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EECNT_LOG( "///////// EE COUNTER VSYNC START \\\\\\\\\\\\\\\\\\\\ (frame: %d)", iFrame );
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vSyncDebugStuff( iFrame ); // EE Profiling and Debug code
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if ((CSRw & 0x8))
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{
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if (!(GSIMR&0x800))
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{
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gsIrq();
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}
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GSCSRr|= 0x8;
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}
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hwIntcIrq(INTC_VBLANK_S);
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psxVBlankStart();
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if (gates) rcntStartGate(true, sCycle); // Counters Start Gate code
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if (EmuConfig.EnablePatches) ApplyPatch(); // fixme - Apply patches
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// INTC - VB Blank Start Hack --
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// Hack fix! This corrects a freezeup in Granda 2 where it decides to spin
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// on the INTC_STAT register after the exception handler has already cleared
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// it. But be warned! Set the value to larger than 4 and it breaks Dark
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// Cloud and other games. -_-
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// How it works: Normally the INTC raises exceptions immediately at the end of the
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// current branch test. But in the case of Grandia 2, the game's code is spinning
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// on the INTC status, and the exception handler (for some reason?) clears the INTC
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// before returning *and* returns to a location other than EPC. So the game never
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// gets to the point where it sees the INTC Irq set true.
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// (I haven't investigated why Dark Cloud freezes on larger values)
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// (all testing done using the recompiler -- dunno how the ints respond yet)
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//cpuRegs.eCycle[30] = 2;
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// Should no longer be required (Refraction)
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}
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static __forceinline void VSyncEnd(u32 sCycle)
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{
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EECNT_LOG( "///////// EE COUNTER VSYNC END \\\\\\\\\\\\\\\\\\\\ (frame: %d)", iFrame );
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iFrame++;
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gsPostVsyncEnd( true );
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hwIntcIrq(INTC_VBLANK_E); // HW Irq
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psxVBlankEnd(); // psxCounters vBlank End
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if (gates) rcntEndGate(true, sCycle); // Counters End Gate Code
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frameLimit(); // limit FPS
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// This doesn't seem to be needed here. Games only seem to break with regard to the
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// vsyncstart irq.
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//cpuRegs.eCycle[30] = 2;
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}
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//#define VSYNC_DEBUG // Uncomment this to enable some vSync Timer debugging features.
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#ifdef VSYNC_DEBUG
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static u32 hsc=0;
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static int vblankinc = 0;
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#endif
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__forceinline void rcntUpdate_hScanline()
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{
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if( !cpuTestCycle( hsyncCounter.sCycle, hsyncCounter.CycleT ) ) return;
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//iopBranchAction = 1;
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if (hsyncCounter.Mode & MODE_HBLANK) { //HBLANK Start
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rcntStartGate(false, hsyncCounter.sCycle);
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psxCheckStartGate16(0);
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// Setup the hRender's start and end cycle information:
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hsyncCounter.sCycle += vSyncInfo.hBlank; // start (absolute cycle value)
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hsyncCounter.CycleT = vSyncInfo.hRender; // endpoint (delta from start value)
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hsyncCounter.Mode = MODE_HRENDER;
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}
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else { //HBLANK END / HRENDER Begin
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if (CSRw & 0x4)
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{
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if (!(GSIMR&0x400))
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{
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gsIrq();
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}
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GSCSRr |= 4; // signal
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}
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if (gates) rcntEndGate(false, hsyncCounter.sCycle);
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if (psxhblankgate) psxCheckEndGate16(0);
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// set up the hblank's start and end cycle information:
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hsyncCounter.sCycle += vSyncInfo.hRender; // start (absolute cycle value)
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hsyncCounter.CycleT = vSyncInfo.hBlank; // endpoint (delta from start value)
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hsyncCounter.Mode = MODE_HBLANK;
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# ifdef VSYNC_DEBUG
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hsc++;
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# endif
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}
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}
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__forceinline void rcntUpdate_vSync()
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{
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s32 diff = (cpuRegs.cycle - vsyncCounter.sCycle);
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if( diff < vsyncCounter.CycleT ) return;
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if (vsyncCounter.Mode == MODE_VSYNC)
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{
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Cpu->CheckExecutionState();
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VSyncEnd(vsyncCounter.sCycle);
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vsyncCounter.sCycle += vSyncInfo.Blank;
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vsyncCounter.CycleT = vSyncInfo.Render;
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vsyncCounter.Mode = MODE_VRENDER;
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}
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else // VSYNC end / VRENDER begin
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{
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VSyncStart(vsyncCounter.sCycle);
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vsyncCounter.sCycle += vSyncInfo.Render;
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vsyncCounter.CycleT = vSyncInfo.Blank;
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vsyncCounter.Mode = MODE_VSYNC;
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// Accumulate hsync rounding errors:
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hsyncCounter.sCycle += vSyncInfo.hSyncError;
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if (CHECK_MICROVU0) vsyncVUrec(0);
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if (CHECK_MICROVU1) vsyncVUrec(1);
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# ifdef VSYNC_DEBUG
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vblankinc++;
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if( vblankinc > 1 )
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{
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if( hsc != vSyncInfo.hScanlinesPerFrame )
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Console.WriteLn( " ** vSync > Abnormal Scanline Count: %d", hsc );
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hsc = 0;
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vblankinc = 0;
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}
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# endif
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}
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}
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static __forceinline void _cpuTestTarget( int i )
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{
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if (counters[i].count < counters[i].target) return;
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if(counters[i].mode.TargetInterrupt) {
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|
|
EECNT_LOG("EE Counter[%d] TARGET reached - mode=%x, count=%x, target=%x", i, counters[i].mode, counters[i].count, counters[i].target);
|
|
counters[i].mode.TargetReached = 1;
|
|
hwIntcIrq(counters[i].interrupt);
|
|
|
|
// The PS2 only resets if the interrupt is enabled - Tested on PS2
|
|
if (counters[i].mode.ZeroReturn)
|
|
counters[i].count -= counters[i].target; // Reset on target
|
|
else
|
|
counters[i].target |= EECNT_FUTURE_TARGET;
|
|
}
|
|
else counters[i].target |= EECNT_FUTURE_TARGET;
|
|
}
|
|
|
|
static __forceinline void _cpuTestOverflow( int i )
|
|
{
|
|
if (counters[i].count <= 0xffff) return;
|
|
|
|
if (counters[i].mode.OverflowInterrupt) {
|
|
EECNT_LOG("EE Counter[%d] OVERFLOW - mode=%x, count=%x", i, counters[i].mode, counters[i].count);
|
|
counters[i].mode.OverflowReached = 1;
|
|
hwIntcIrq(counters[i].interrupt);
|
|
}
|
|
|
|
// wrap counter back around zero, and enable the future target:
|
|
counters[i].count -= 0x10000;
|
|
counters[i].target &= 0xffff;
|
|
}
|
|
|
|
|
|
// forceinline note: this method is called from two locations, but one
|
|
// of them is the interpreter, which doesn't count. ;) So might as
|
|
// well forceinline it!
|
|
__forceinline void rcntUpdate()
|
|
{
|
|
rcntUpdate_vSync();
|
|
|
|
// Update counters so that we can perform overflow and target tests.
|
|
|
|
for (int i=0; i<=3; i++)
|
|
{
|
|
// We want to count gated counters (except the hblank which exclude below, and are
|
|
// counted by the hblank timer instead)
|
|
|
|
//if ( gates & (1<<i) ) continue;
|
|
|
|
if (!counters[i].mode.IsCounting ) continue;
|
|
|
|
if(counters[i].mode.ClockSource != 0x3) // don't count hblank sources
|
|
{
|
|
s32 change = cpuRegs.cycle - counters[i].sCycleT;
|
|
if( change < 0 ) change = 0; // sanity check!
|
|
|
|
counters[i].count += change / counters[i].rate;
|
|
change -= (change / counters[i].rate) * counters[i].rate;
|
|
counters[i].sCycleT = cpuRegs.cycle - change;
|
|
|
|
// Check Counter Targets and Overflows:
|
|
_cpuTestTarget( i );
|
|
_cpuTestOverflow( i );
|
|
}
|
|
else counters[i].sCycleT = cpuRegs.cycle;
|
|
}
|
|
|
|
cpuRcntSet();
|
|
}
|
|
|
|
static __forceinline void _rcntSetGate( int index )
|
|
{
|
|
if (counters[index].mode.EnableGate)
|
|
{
|
|
// If the Gate Source is hblank and the clock selection is also hblank
|
|
// then the gate is disabled and the counter acts as a normal hblank source.
|
|
|
|
if( !(counters[index].mode.GateSource == 0 && counters[index].mode.ClockSource == 3) )
|
|
{
|
|
EECNT_LOG( "EE Counter[%d] Using Gate! Source=%s, Mode=%d.",
|
|
index, counters[index].mode.GateSource ? "vblank" : "hblank", counters[index].mode.GateMode );
|
|
|
|
gates |= (1<<index);
|
|
counters[index].mode.IsCounting = 0;
|
|
rcntReset(index);
|
|
return;
|
|
}
|
|
else
|
|
EECNT_LOG( "EE Counter[%d] GATE DISABLED because of hblank source.", index );
|
|
}
|
|
|
|
gates &= ~(1<<index);
|
|
}
|
|
|
|
// mode - 0 means hblank source, 8 means vblank source.
|
|
__forceinline void rcntStartGate(bool isVblank, u32 sCycle)
|
|
{
|
|
int i;
|
|
|
|
for (i=0; i <=3; i++)
|
|
{
|
|
//if ((mode == 0) && ((counters[i].mode & 0x83) == 0x83))
|
|
if (!isVblank && counters[i].mode.IsCounting && (counters[i].mode.ClockSource == 3) )
|
|
{
|
|
// Update counters using the hblank as the clock. This keeps the hblank source
|
|
// nicely in sync with the counters and serves as an optimization also, since these
|
|
// counter won't recieve special rcntUpdate scheduling.
|
|
|
|
// Note: Target and overflow tests must be done here since they won't be done
|
|
// currectly by rcntUpdate (since it's not being scheduled for these counters)
|
|
|
|
counters[i].count += HBLANK_COUNTER_SPEED;
|
|
_cpuTestTarget( i );
|
|
_cpuTestOverflow( i );
|
|
}
|
|
|
|
if (!(gates & (1<<i))) continue;
|
|
if ((!!counters[i].mode.GateSource) != isVblank) continue;
|
|
|
|
switch (counters[i].mode.GateMode) {
|
|
case 0x0: //Count When Signal is low (off)
|
|
|
|
// Just set the start cycle (sCycleT) -- counting will be done as needed
|
|
// for events (overflows, targets, mode changes, and the gate off below)
|
|
|
|
counters[i].mode.IsCounting = 1;
|
|
counters[i].sCycleT = sCycle;
|
|
EECNT_LOG("EE Counter[%d] %s StartGate Type0, count = %x",
|
|
isVblank ? "vblank" : "hblank", i, counters[i].count );
|
|
break;
|
|
|
|
case 0x2: // reset and start counting on vsync end
|
|
// this is the vsync start so do nothing.
|
|
break;
|
|
|
|
case 0x1: //Reset and start counting on Vsync start
|
|
case 0x3: //Reset and start counting on Vsync start and end
|
|
counters[i].mode.IsCounting = 1;
|
|
counters[i].count = 0;
|
|
counters[i].target &= 0xffff;
|
|
counters[i].sCycleT = sCycle;
|
|
EECNT_LOG("EE Counter[%d] %s StartGate Type%d, count = %x",
|
|
isVblank ? "vblank" : "hblank", i, counters[i].mode.GateMode, counters[i].count );
|
|
break;
|
|
}
|
|
}
|
|
|
|
// No need to update actual counts here. Counts are calculated as needed by reads to
|
|
// rcntRcount(). And so long as sCycleT is set properly, any targets or overflows
|
|
// will be scheduled and handled.
|
|
|
|
// Note: No need to set counters here. They'll get set when control returns to
|
|
// rcntUpdate, since we're being called from there anyway.
|
|
}
|
|
|
|
// mode - 0 means hblank signal, 8 means vblank signal.
|
|
__forceinline void rcntEndGate(bool isVblank , u32 sCycle)
|
|
{
|
|
int i;
|
|
|
|
for(i=0; i <=3; i++) { //Gates for counters
|
|
if (!(gates & (1<<i))) continue;
|
|
if ((!!counters[i].mode.GateSource) != isVblank) continue;
|
|
|
|
switch (counters[i].mode.GateMode) {
|
|
case 0x0: //Count When Signal is low (off)
|
|
|
|
// Set the count here. Since the timer is being turned off it's
|
|
// important to record its count at this point (it won't be counted by
|
|
// calls to rcntUpdate).
|
|
|
|
counters[i].count = rcntRcount(i);
|
|
counters[i].mode.IsCounting = 0;
|
|
counters[i].sCycleT = sCycle;
|
|
EECNT_LOG("EE Counter[%d] %s EndGate Type0, count = %x",
|
|
isVblank ? "vblank" : "hblank", i, counters[i].count );
|
|
break;
|
|
|
|
case 0x1: // Reset and start counting on Vsync start
|
|
// this is the vsync end so do nothing
|
|
break;
|
|
|
|
case 0x2: //Reset and start counting on Vsync end
|
|
case 0x3: //Reset and start counting on Vsync start and end
|
|
counters[i].mode.IsCounting = 1;
|
|
counters[i].count = 0;
|
|
counters[i].target &= 0xffff;
|
|
counters[i].sCycleT = sCycle;
|
|
EECNT_LOG("EE Counter[%d] %s EndGate Type%d, count = %x",
|
|
isVblank ? "vblank" : "hblank", i, counters[i].mode.GateMode, counters[i].count );
|
|
break;
|
|
}
|
|
}
|
|
// Note: No need to set counters here. They'll get set when control returns to
|
|
// rcntUpdate, since we're being called from there anyway.
|
|
}
|
|
|
|
__forceinline void rcntWmode(int index, u32 value)
|
|
{
|
|
if(counters[index].mode.IsCounting) {
|
|
if(counters[index].mode.ClockSource != 0x3) {
|
|
|
|
u32 change = cpuRegs.cycle - counters[index].sCycleT;
|
|
if( change > 0 )
|
|
{
|
|
counters[index].count += change / counters[index].rate;
|
|
change -= (change / counters[index].rate) * counters[index].rate;
|
|
counters[index].sCycleT = cpuRegs.cycle - change;
|
|
}
|
|
}
|
|
}
|
|
else counters[index].sCycleT = cpuRegs.cycle;
|
|
|
|
// Clear OverflowReached and TargetReached flags (0xc00 mask), but *only* if they are set to 1 in the
|
|
// given value. (yes, the bits are cleared when written with '1's).
|
|
|
|
counters[index].modeval &= ~(value & 0xc00);
|
|
counters[index].modeval = (counters[index].modeval & 0xc00) | (value & 0x3ff);
|
|
EECNT_LOG("EE Counter[%d] writeMode = %x passed value=%x", index, counters[index].modeval, value );
|
|
|
|
switch (counters[index].mode.ClockSource) { //Clock rate divisers *2, they use BUSCLK speed not PS2CLK
|
|
case 0: counters[index].rate = 2; break;
|
|
case 1: counters[index].rate = 32; break;
|
|
case 2: counters[index].rate = 512; break;
|
|
case 3: counters[index].rate = vSyncInfo.hBlank+vSyncInfo.hRender; break;
|
|
}
|
|
|
|
_rcntSetGate( index );
|
|
_rcntSet( index );
|
|
}
|
|
|
|
__forceinline void rcntWcount(int index, u32 value)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] writeCount = %x, oldcount=%x, target=%x", index, value, counters[index].count, counters[index].target );
|
|
|
|
counters[index].count = value & 0xffff;
|
|
|
|
// reset the target, and make sure we don't get a premature target.
|
|
counters[index].target &= 0xffff;
|
|
if( counters[index].count > counters[index].target )
|
|
counters[index].target |= EECNT_FUTURE_TARGET;
|
|
|
|
// re-calculate the start cycle of the counter based on elapsed time since the last counter update:
|
|
if(counters[index].mode.IsCounting) {
|
|
if(counters[index].mode.ClockSource != 0x3) {
|
|
s32 change = cpuRegs.cycle - counters[index].sCycleT;
|
|
if( change > 0 ) {
|
|
change -= (change / counters[index].rate) * counters[index].rate;
|
|
counters[index].sCycleT = cpuRegs.cycle - change;
|
|
}
|
|
}
|
|
}
|
|
else counters[index].sCycleT = cpuRegs.cycle;
|
|
|
|
_rcntSet( index );
|
|
}
|
|
|
|
__forceinline void rcntWtarget(int index, u32 value)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] writeTarget = %x", index, value);
|
|
|
|
counters[index].target = value & 0xffff;
|
|
|
|
// guard against premature (instant) targeting.
|
|
// If the target is behind the current count, set it up so that the counter must
|
|
// overflow first before the target fires:
|
|
|
|
if(counters[index].mode.IsCounting) {
|
|
if(counters[index].mode.ClockSource != 0x3) {
|
|
|
|
u32 change = cpuRegs.cycle - counters[index].sCycleT;
|
|
if( change > 0 )
|
|
{
|
|
counters[index].count += change / counters[index].rate;
|
|
change -= (change / counters[index].rate) * counters[index].rate;
|
|
counters[index].sCycleT = cpuRegs.cycle - change;
|
|
}
|
|
}
|
|
}
|
|
|
|
if( counters[index].target <= rcntCycle(index) )
|
|
counters[index].target |= EECNT_FUTURE_TARGET;
|
|
|
|
_rcntSet( index );
|
|
}
|
|
|
|
__forceinline void rcntWhold(int index, u32 value)
|
|
{
|
|
EECNT_LOG("EE Counter[%d] Hold Write = %x", index, value);
|
|
counters[index].hold = value;
|
|
}
|
|
|
|
__forceinline u32 rcntRcount(int index)
|
|
{
|
|
u32 ret;
|
|
|
|
// only count if the counter is turned on (0x80) and is not an hsync gate (!0x03)
|
|
if (counters[index].mode.IsCounting && (counters[index].mode.ClockSource != 0x3))
|
|
ret = counters[index].count + ((cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate);
|
|
else
|
|
ret = counters[index].count;
|
|
|
|
// Spams the Console.
|
|
EECNT_LOG("EE Counter[%d] readCount32 = %x", index, ret);
|
|
return ret;
|
|
}
|
|
|
|
__forceinline u32 rcntCycle(int index)
|
|
{
|
|
if (counters[index].mode.IsCounting && (counters[index].mode.ClockSource != 0x3))
|
|
return counters[index].count + ((cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate);
|
|
else
|
|
return counters[index].count;
|
|
}
|
|
|
|
void SaveStateBase::rcntFreeze()
|
|
{
|
|
Freeze( counters );
|
|
Freeze( hsyncCounter );
|
|
Freeze( vsyncCounter );
|
|
Freeze( nextCounter );
|
|
Freeze( nextsCounter );
|
|
|
|
if( IsLoading() )
|
|
{
|
|
UpdateVSyncRate();
|
|
|
|
// make sure the gate flags are set based on the counter modes...
|
|
for( int i=0; i<4; i++ )
|
|
_rcntSetGate( i );
|
|
|
|
iopBranchAction = 1; // probably not needed but won't hurt anything either.
|
|
}
|
|
}
|