mirror of https://github.com/PCSX2/pcsx2.git
134 lines
3.5 KiB
C++
134 lines
3.5 KiB
C++
// SPDX-FileCopyrightText: 2002-2023 PCSX2 Dev Team
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// SPDX-License-Identifier: LGPL-3.0+
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#pragma once
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//------------------------------------------------------------------
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// Micro VU - Pass 2 Functions
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Flag Allocators
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//------------------------------------------------------------------
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__fi static const x32& getFlagReg(uint fInst)
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{
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static const x32* const gprFlags[4] = {&gprF0, &gprF1, &gprF2, &gprF3};
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pxAssert(fInst < 4);
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return *gprFlags[fInst];
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}
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__fi void setBitSFLAG(const x32& reg, const x32& regT, int bitTest, int bitSet)
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{
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xTEST(regT, bitTest);
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xForwardJZ8 skip;
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xOR(reg, bitSet);
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skip.SetTarget();
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}
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__fi void setBitFSEQ(const x32& reg, int bitX)
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{
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xTEST(reg, bitX);
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xForwardJump8 skip(Jcc_Zero);
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xOR(reg, bitX);
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skip.SetTarget();
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}
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__fi void mVUallocSFLAGa(const x32& reg, int fInstance)
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{
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xMOV(reg, getFlagReg(fInstance));
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}
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__fi void mVUallocSFLAGb(const x32& reg, int fInstance)
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{
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xMOV(getFlagReg(fInstance), reg);
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}
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// Normalize Status Flag
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__ri void mVUallocSFLAGc(const x32& reg, const x32& regT, int fInstance)
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{
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xXOR(reg, reg);
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mVUallocSFLAGa(regT, fInstance);
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setBitSFLAG(reg, regT, 0x0f00, 0x0001); // Z Bit
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setBitSFLAG(reg, regT, 0xf000, 0x0002); // S Bit
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setBitSFLAG(reg, regT, 0x000f, 0x0040); // ZS Bit
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setBitSFLAG(reg, regT, 0x00f0, 0x0080); // SS Bit
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xAND(regT, 0xffff0000); // DS/DI/OS/US/D/I/O/U Bits
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xSHR(regT, 14);
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xOR(reg, regT);
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}
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// Denormalizes Status Flag; destroys tmp1/tmp2
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__ri void mVUallocSFLAGd(u32* memAddr, const x32& reg = eax, const x32& tmp1 = ecx, const x32& tmp2 = edx)
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{
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xMOV(tmp2, ptr32[memAddr]);
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xMOV(reg, tmp2);
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xSHR(reg, 3);
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xAND(reg, 0x18);
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xMOV(tmp1, tmp2);
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xSHL(tmp1, 11);
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xAND(tmp1, 0x1800);
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xOR(reg, tmp1);
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xSHL(tmp2, 14);
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xAND(tmp2, 0x3cf0000);
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xOR(reg, tmp2);
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}
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__fi void mVUallocMFLAGa(mV, const x32& reg, int fInstance)
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{
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xMOVZX(reg, ptr16[&mVU.macFlag[fInstance]]);
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}
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__fi void mVUallocMFLAGb(mV, const x32& reg, int fInstance)
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{
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//xAND(reg, 0xffff);
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if (fInstance < 4) xMOV(ptr32[&mVU.macFlag[fInstance]], reg); // microVU
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else xMOV(ptr32[&mVU.regs().VI[REG_MAC_FLAG].UL], reg); // macroVU
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}
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__fi void mVUallocCFLAGa(mV, const x32& reg, int fInstance)
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{
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if (fInstance < 4) xMOV(reg, ptr32[&mVU.clipFlag[fInstance]]); // microVU
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else xMOV(reg, ptr32[&mVU.regs().VI[REG_CLIP_FLAG].UL]); // macroVU
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}
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__fi void mVUallocCFLAGb(mV, const x32& reg, int fInstance)
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{
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if (fInstance < 4) xMOV(ptr32[&mVU.clipFlag[fInstance]], reg); // microVU
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else xMOV(ptr32[&mVU.regs().VI[REG_CLIP_FLAG].UL], reg); // macroVU
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}
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//------------------------------------------------------------------
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// VI Reg Allocators
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//------------------------------------------------------------------
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void microRegAlloc::writeVIBackup(const xRegisterInt& reg)
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{
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microVU& mVU = index ? microVU1 : microVU0;
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xMOV(ptr32[&mVU.VIbackup], xRegister32(reg));
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}
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//------------------------------------------------------------------
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// P/Q Reg Allocators
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//------------------------------------------------------------------
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__fi void getPreg(mV, const xmm& reg)
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{
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mVUunpack_xyzw(reg, xmmPQ, (2 + mVUinfo.readP));
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}
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__fi void getQreg(const xmm& reg, int qInstance)
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{
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mVUunpack_xyzw(reg, xmmPQ, qInstance);
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}
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__ri void writeQreg(const xmm& reg, int qInstance)
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{
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if (qInstance)
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xINSERTPS(xmmPQ, reg, _MM_MK_INSERTPS_NDX(0, 1, 0));
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else
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xMOVSS(xmmPQ, reg);
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}
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