mirror of https://github.com/PCSX2/pcsx2.git
637 lines
14 KiB
C++
637 lines
14 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "R5900OpcodeTables.h"
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#include "R5900Exceptions.h"
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#include "System/SysThreads.h"
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#include "Elfheader.h"
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#include "../DebugTools/Breakpoints.h"
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#include <float.h>
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using namespace R5900; // for OPCODE and OpcodeImpl
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extern int vu0branch, vu1branch;
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static int branch2 = 0;
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static u32 cpuBlockCycles = 0; // 3 bit fixed point version of cycle count
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static std::string disOut;
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static void intEventTest();
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// These macros are used to assemble the repassembler functions
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static void debugI()
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{
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if( !IsDevBuild ) return;
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if( cpuRegs.GPR.n.r0.UD[0] || cpuRegs.GPR.n.r0.UD[1] ) Console.Error("R0 is not zero!!!!");
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}
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void intBreakpoint(bool memcheck)
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{
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u32 pc = cpuRegs.pc;
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if (CBreakPoints::CheckSkipFirst(pc) != 0)
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return;
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if (!memcheck)
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{
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auto cond = CBreakPoints::GetBreakPointCondition(pc);
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if (cond && !cond->Evaluate())
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return;
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}
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CBreakPoints::SetBreakpointTriggered(true);
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GetCoreThread().PauseSelf();
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throw Exception::ExitCpuExecute();
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}
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void intMemcheck(u32 op, u32 bits, bool store)
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{
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// compute accessed address
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u32 start = cpuRegs.GPR.r[(op >> 21) & 0x1F].UD[0];
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if ((s16)op != 0)
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start += (s16)op;
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if (bits == 128)
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start &= ~0x0F;
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start = standardizeBreakpointAddress(start);
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u32 end = start + bits/8;
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auto checks = CBreakPoints::GetMemChecks();
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for (size_t i = 0; i < checks.size(); i++)
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{
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auto& check = checks[i];
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if (check.result == 0)
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continue;
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if ((check.cond & MEMCHECK_WRITE) == 0 && store)
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continue;
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if ((check.cond & MEMCHECK_READ) == 0 && !store)
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continue;
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if (start < check.end && check.start < end)
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intBreakpoint(true);
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}
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}
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void intCheckMemcheck()
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{
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u32 pc = cpuRegs.pc;
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int needed = isMemcheckNeeded(pc);
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if (needed == 0)
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return;
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u32 op = memRead32(needed == 2 ? pc+4 : pc);
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const OPCODE& opcode = GetInstruction(op);
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bool store = (opcode.flags & IS_STORE) != 0;
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switch (opcode.flags & MEMTYPE_MASK)
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{
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case MEMTYPE_BYTE:
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intMemcheck(op,8,store);
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break;
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case MEMTYPE_HALF:
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intMemcheck(op,16,store);
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break;
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case MEMTYPE_WORD:
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intMemcheck(op,32,store);
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break;
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case MEMTYPE_DWORD:
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intMemcheck(op,64,store);
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break;
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case MEMTYPE_QWORD:
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intMemcheck(op,128,store);
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break;
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}
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}
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static void execI()
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{
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// execI is called for every instruction so it must remains as light as possible.
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// If you enable the next define, Interpreter will be much slower (around
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// ~4fps on 3.9GHz Haswell vs ~8fps (even 10fps on dev build))
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// Extra note: due to some cycle count issue PCSX2's internal debugger is
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// not yet usable with the interpreter
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//#define EXTRA_DEBUG
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#ifdef EXTRA_DEBUG
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// check if any breakpoints or memchecks are triggered by this instruction
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if (isBreakpointNeeded(cpuRegs.pc))
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intBreakpoint(false);
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intCheckMemcheck();
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#endif
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u32 pc = cpuRegs.pc;
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// We need to increase the pc before executing the memRead32. An exception could appears
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// and it expects the PC counter to be pre-incremented
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cpuRegs.pc += 4;
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// interprete instruction
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cpuRegs.code = memRead32( pc );
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// Honestly I think this code is useless nowadays.
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#ifdef EXTRA_DEBUG
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if( IsDebugBuild )
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debugI();
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#endif
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const OPCODE& opcode = GetCurrentInstruction();
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#if 0
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static long int runs = 0;
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//use this to find out what opcodes your game uses. very slow! (rama)
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runs++;
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if (runs > 1599999999){ //leave some time to startup the testgame
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if (opcode.Name[0] == 'L') { //find all opcodes beginning with "L"
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Console.WriteLn ("Load %s", opcode.Name);
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}
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}
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#endif
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#if 0
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static long int print_me = 0;
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// Based on cycle
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// if( cpuRegs.cycle > 0x4f24d714 )
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// Or dump from a particular PC (useful to debug handler/syscall)
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if (pc == 0x80000000) {
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print_me = 2000;
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}
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if (print_me) {
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print_me--;
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disOut.clear();
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disR5900Fasm(disOut, cpuRegs.code, pc);
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CPU_LOG( disOut.c_str() );
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}
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#endif
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cpuBlockCycles += opcode.cycles;
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opcode.interpret();
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}
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static __fi void _doBranch_shared(u32 tar)
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{
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branch2 = cpuRegs.branch = 1;
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execI();
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// branch being 0 means an exception was thrown, since only the exception
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// handler should ever clear it.
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if( cpuRegs.branch != 0 )
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{
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cpuRegs.pc = tar;
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cpuRegs.branch = 0;
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}
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}
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static void __fastcall doBranch( u32 target )
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{
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_doBranch_shared( target );
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cpuRegs.cycle += cpuBlockCycles >> 3;
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cpuBlockCycles &= (1<<3)-1;
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intEventTest();
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}
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void __fastcall intDoBranch(u32 target)
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{
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//Console.WriteLn("Interpreter Branch ");
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_doBranch_shared( target );
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if( Cpu == &intCpu )
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{
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cpuRegs.cycle += cpuBlockCycles >> 3;
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cpuBlockCycles &= (1<<3)-1;
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intEventTest();
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}
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}
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void intSetBranch()
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{
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branch2 = /*cpuRegs.branch =*/ 1;
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}
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////////////////////////////////////////////////////////////////////
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// R5900 Branching Instructions!
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// These are the interpreter versions of the branch instructions. Unlike other
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// types of interpreter instructions which can be called safely from the recompilers,
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// these instructions are not "recSafe" because they may not invoke the
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// necessary branch test logic that the recs need to maintain sync with the
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// cpuRegs.pc and delaySlot instruction and such.
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namespace R5900 {
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namespace Interpreter {
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namespace OpcodeImpl {
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/*********************************************************
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* Jump to target *
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* Format: OP target *
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*********************************************************/
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// fixme: looking at the other branching code, shouldn't those _SetLinks in BGEZAL and such only be set
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// if the condition is true? --arcum42
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void J()
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{
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doBranch(_JumpTarget_);
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}
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void JAL()
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{
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// 0x3563b8 is the start address of the function that invalidate entry in TLB cache
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if (EmuConfig.Gamefixes.GoemonTlbHack) {
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if (_JumpTarget_ == 0x3563b8)
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GoemonUnloadTlb(cpuRegs.GPR.n.a0.UL[0]);
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}
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_SetLink(31);
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doBranch(_JumpTarget_);
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}
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/*********************************************************
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* Register branch logic *
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* Format: OP rs, rt, offset *
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*********************************************************/
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void BEQ() // Branch if Rs == Rt
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] == cpuRegs.GPR.r[_Rt_].SD[0])
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doBranch(_BranchTarget_);
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else
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intEventTest();
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}
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void BNE() // Branch if Rs != Rt
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] != cpuRegs.GPR.r[_Rt_].SD[0])
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doBranch(_BranchTarget_);
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else
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intEventTest();
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}
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/*********************************************************
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* Register branch logic *
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* Format: OP rs, offset *
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*********************************************************/
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void BGEZ() // Branch if Rs >= 0
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
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{
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doBranch(_BranchTarget_);
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}
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}
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void BGEZAL() // Branch if Rs >= 0 and link
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{
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_SetLink(31);
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if (cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
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{
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doBranch(_BranchTarget_);
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}
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}
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void BGTZ() // Branch if Rs > 0
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] > 0)
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{
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doBranch(_BranchTarget_);
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}
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}
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void BLEZ() // Branch if Rs <= 0
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] <= 0)
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{
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doBranch(_BranchTarget_);
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}
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}
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void BLTZ() // Branch if Rs < 0
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] < 0)
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{
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doBranch(_BranchTarget_);
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}
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}
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void BLTZAL() // Branch if Rs < 0 and link
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{
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_SetLink(31);
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if (cpuRegs.GPR.r[_Rs_].SD[0] < 0)
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{
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doBranch(_BranchTarget_);
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}
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}
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/*********************************************************
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* Register branch logic Likely *
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* Format: OP rs, offset *
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*********************************************************/
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void BEQL() // Branch if Rs == Rt
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] == cpuRegs.GPR.r[_Rt_].SD[0])
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BNEL() // Branch if Rs != Rt
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] != cpuRegs.GPR.r[_Rt_].SD[0])
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BLEZL() // Branch if Rs <= 0
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] <= 0)
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BGTZL() // Branch if Rs > 0
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] > 0)
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BLTZL() // Branch if Rs < 0
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] < 0)
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BGEZL() // Branch if Rs >= 0
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BLTZALL() // Branch if Rs < 0 and link
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{
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_SetLink(31);
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if(cpuRegs.GPR.r[_Rs_].SD[0] < 0)
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BGEZALL() // Branch if Rs >= 0 and link
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{
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_SetLink(31);
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if(cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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/*********************************************************
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* Register jump *
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* Format: OP rs, rd *
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*********************************************************/
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void JR()
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{
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// 0x33ad48 and 0x35060c are the return address of the function (0x356250) that populate the TLB cache
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if (EmuConfig.Gamefixes.GoemonTlbHack) {
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u32 add = cpuRegs.GPR.r[_Rs_].UL[0];
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if (add == 0x33ad48 || add == 0x35060c)
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GoemonPreloadTlb();
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}
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doBranch(cpuRegs.GPR.r[_Rs_].UL[0]);
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}
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void JALR()
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{
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u32 temp = cpuRegs.GPR.r[_Rs_].UL[0];
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if (_Rd_) _SetLink(_Rd_);
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doBranch(temp);
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}
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} } } // end namespace R5900::Interpreter::OpcodeImpl
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// --------------------------------------------------------------------------------------
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// R5900cpu/intCpu interface (implementations)
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// --------------------------------------------------------------------------------------
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static void intReserve()
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{
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// fixme : detect cpu for use the optimize asm code
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}
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static void intAlloc()
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{
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// Nothing to do!
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}
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static void intReset()
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{
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cpuRegs.branch = 0;
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branch2 = 0;
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}
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static void intEventTest()
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{
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// Perform counters, ints, and IOP updates:
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_cpuEventTest_Shared();
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}
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static void intExecute()
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{
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bool instruction_was_cancelled;
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enum ExecuteState {
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RESET,
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GAME_LOADING,
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GAME_RUNNING
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};
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ExecuteState state = RESET;
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do {
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instruction_was_cancelled = false;
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try {
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// The execution was splited in three parts so it is easier to
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// resume it after a cancelled instruction.
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switch (state) {
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case RESET:
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do
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execI();
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while (cpuRegs.pc != (g_eeloadMain ? g_eeloadMain : EELOAD_START));
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if (cpuRegs.pc == EELOAD_START)
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{
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// The EELOAD _start function is the same across all BIOS versions afaik
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u32 mainjump = memRead32(EELOAD_START + 0x9c);
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if (mainjump >> 26 == 3) // JAL
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g_eeloadMain = ((EELOAD_START + 0xa0) & 0xf0000000U) | (mainjump << 2 & 0x0fffffffU);
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}
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else if (cpuRegs.pc == g_eeloadMain)
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{
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eeloadHook();
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if (g_SkipBiosHack)
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{
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// See comments on this code in iR5900-32.cpp's recRecompile()
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u32 typeAexecjump = memRead32(EELOAD_START + 0x470);
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u32 typeBexecjump = memRead32(EELOAD_START + 0x5B0);
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u32 typeCexecjump = memRead32(EELOAD_START + 0x618);
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u32 typeDexecjump = memRead32(EELOAD_START + 0x600);
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if ((typeBexecjump >> 26 == 3) || (typeCexecjump >> 26 == 3) || (typeDexecjump >> 26 == 3)) // JAL to 0x822B8
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g_eeloadExec = EELOAD_START + 0x2B8;
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else if (typeAexecjump >> 26 == 3) // JAL to 0x82170
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g_eeloadExec = EELOAD_START + 0x170;
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else
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Console.WriteLn("intExecute: Could not enable launch arguments for fast boot mode; unidentified BIOS version! Please report this to the PCSX2 developers.");
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}
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}
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else if (cpuRegs.pc == g_eeloadExec)
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eeloadHook2();
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if (g_GameLoading)
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state = GAME_LOADING;
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else
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break;
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case GAME_LOADING:
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if (ElfEntry != 0xFFFFFFFF) {
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do
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execI();
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while (cpuRegs.pc != ElfEntry);
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eeGameStarting();
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}
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state = GAME_RUNNING;
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case GAME_RUNNING:
|
|
while (true)
|
|
execI();
|
|
}
|
|
}
|
|
catch( Exception::ExitCpuExecute& ) { }
|
|
catch( Exception::CancelInstruction& ) { instruction_was_cancelled = true; }
|
|
|
|
// For example a tlb miss will throw an exception. Cpu must be resumed
|
|
// to execute the handler
|
|
} while (instruction_was_cancelled);
|
|
}
|
|
|
|
static void intCheckExecutionState()
|
|
{
|
|
if( GetCoreThread().HasPendingStateChangeRequest() )
|
|
throw Exception::ExitCpuExecute();
|
|
}
|
|
|
|
static void intStep()
|
|
{
|
|
execI();
|
|
}
|
|
|
|
static void intClear(u32 Addr, u32 Size)
|
|
{
|
|
}
|
|
|
|
static void intShutdown() {
|
|
}
|
|
|
|
static void intThrowException( const BaseR5900Exception& ex )
|
|
{
|
|
// No tricks needed; C++ stack unwnding should suffice for MSW and GCC alike.
|
|
ex.Rethrow();
|
|
}
|
|
|
|
static void intThrowException( const BaseException& ex )
|
|
{
|
|
// No tricks needed; C++ stack unwnding should suffice for MSW and GCC alike.
|
|
ex.Rethrow();
|
|
}
|
|
|
|
static void intSetCacheReserve( uint reserveInMegs )
|
|
{
|
|
}
|
|
|
|
static uint intGetCacheReserve()
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
R5900cpu intCpu =
|
|
{
|
|
intReserve,
|
|
intShutdown,
|
|
|
|
intReset,
|
|
intStep,
|
|
intExecute,
|
|
|
|
intCheckExecutionState,
|
|
intThrowException,
|
|
intThrowException,
|
|
intClear,
|
|
|
|
intGetCacheReserve,
|
|
intSetCacheReserve,
|
|
};
|