mirror of https://github.com/PCSX2/pcsx2.git
178 lines
4.2 KiB
C++
178 lines
4.2 KiB
C++
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2009 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#ifndef _R5900_EXCEPTIONS_H_
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#define _R5900_EXCEPTIONS_H_
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namespace R5900Exception
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{
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using Exception::Ps2Generic;
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//////////////////////////////////////////////////////////////////////////////////
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// Abstract base class for R5900 exceptions; contains the cpuRegs instance at the
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// time the exception is raised.
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//
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class BaseExcept : public Ps2Generic
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{
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public:
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const cpuRegisters cpuState;
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public:
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virtual ~BaseExcept() throw()=0;
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explicit BaseExcept( const std::string& msg ) :
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Exception::Ps2Generic( "(EE) " + msg ),
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cpuState( cpuRegs )
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{
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}
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u32 GetPc() const { return cpuState.pc; }
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bool IsDelaySlot() const { return !!cpuState.IsDelaySlot; }
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};
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//////////////////////////////////////////////////////////////////////////////////
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//
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class AddressError : public BaseExcept
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{
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public:
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const bool OnWrite;
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const u32 Address;
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public:
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virtual ~AddressError() throw() {}
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explicit AddressError( u32 ps2addr, bool onWrite ) :
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BaseExcept( fmt_string( "Address error, addr=0x%x [%s]", ps2addr, onWrite ? "store" : "load" ) ),
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OnWrite( onWrite ),
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Address( ps2addr )
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{}
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};
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//////////////////////////////////////////////////////////////////////////////////
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//
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class TLBMiss : public BaseExcept
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{
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public:
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const bool OnWrite;
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const u32 Address;
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public:
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virtual ~TLBMiss() throw() {}
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explicit TLBMiss( u32 ps2addr, bool onWrite ) :
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BaseExcept( fmt_string( "Tlb Miss, addr=0x%x [%s]", ps2addr, onWrite ? "store" : "load" ) ),
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OnWrite( onWrite ),
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Address( ps2addr )
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{}
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};
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//////////////////////////////////////////////////////////////////////////////////
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//
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class BusError : public BaseExcept
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{
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public:
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const bool OnWrite;
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const u32 Address;
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public:
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virtual ~BusError() throw() {}
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//
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explicit BusError( u32 ps2addr, bool onWrite ) :
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BaseExcept( fmt_string( "Bus Error, addr=0x%x [%s]", ps2addr, onWrite ? "store" : "load" ) ),
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OnWrite( onWrite ),
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Address( ps2addr )
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{}
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};
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//////////////////////////////////////////////////////////////////////////////////
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//
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class SystemCall : public BaseExcept
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{
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public:
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virtual ~SystemCall() throw() {}
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explicit SystemCall() :
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BaseExcept( "SystemCall [SYSCALL]" )
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{}
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};
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//////////////////////////////////////////////////////////////////////////////////
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//
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class Trap : public BaseExcept
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{
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public:
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const u16 TrapCode;
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public:
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virtual ~Trap() throw() {}
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// Generates a trap for immediate-style Trap opcodes
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explicit Trap() :
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BaseExcept( "Trap" ),
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TrapCode( 0 )
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{}
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// Generates a trap for register-style Trap instructions, which contain an
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// error code in the opcode
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explicit Trap( u16 trapcode ) :
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BaseExcept( "Trap" ),
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TrapCode( trapcode )
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{}
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};
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//////////////////////////////////////////////////////////////////////////////////
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//
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class Break : public BaseExcept
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{
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public:
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virtual ~Break() throw() {}
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explicit Break() :
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BaseExcept( "Break Instruction" )
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{}
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};
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//////////////////////////////////////////////////////////////////////////////////
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//
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class Overflow : public BaseExcept
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{
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public:
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virtual ~Overflow() throw() {}
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explicit Overflow() :
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BaseExcept( "Overflow" )
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{}
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};
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//////////////////////////////////////////////////////////////////////////////////
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//
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class DebugBreakpoint : public BaseExcept
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{
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public:
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virtual ~DebugBreakpoint() throw() {}
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explicit DebugBreakpoint() :
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BaseExcept( "Debug Breakpoint" )
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{}
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};
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}
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#endif
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