mirror of https://github.com/PCSX2/pcsx2.git
806 lines
30 KiB
C++
806 lines
30 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "common/emitter/internal.h"
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#include "common/emitter/tools.h"
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// Mask of valid bit fields for the target CPU. Typically this is either 0xFFFF (SSE2
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// or better) or 0xFFBF (SSE1 and earlier). Code can ensure a safe/valid MXCSR by
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// AND'ing this mask against an MXCSR prior to LDMXCSR.
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SSE_MXCSR MXCSR_Mask;
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const char* EnumToString(SSE_RoundMode sse)
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{
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switch (sse)
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{
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case SSEround_Nearest:
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return "Nearest";
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case SSEround_NegInf:
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return "NegativeInfinity";
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case SSEround_PosInf:
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return "PositiveInfinity";
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case SSEround_Chop:
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return "Chop";
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default:
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return "Invalid";
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}
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}
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SSE_RoundMode SSE_MXCSR::GetRoundMode() const
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{
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return (SSE_RoundMode)RoundingControl;
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}
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SSE_MXCSR& SSE_MXCSR::SetRoundMode(SSE_RoundMode mode)
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{
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pxAssert((uint)mode < 4);
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RoundingControl = (u32)mode;
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return *this;
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}
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SSE_MXCSR& SSE_MXCSR::ClearExceptionFlags()
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{
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bitmask &= ~0x3f;
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return *this;
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}
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SSE_MXCSR& SSE_MXCSR::EnableExceptions()
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{
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bitmask &= ~(0x3f << 7);
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return *this;
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}
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SSE_MXCSR& SSE_MXCSR::DisableExceptions()
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{
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bitmask |= 0x3f << 7;
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return *this;
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}
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// Applies the reserve bits mask for the current running cpu, as fetched from the CPU
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// during CPU init/detection.
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SSE_MXCSR& SSE_MXCSR::ApplyReserveMask()
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{
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bitmask &= MXCSR_Mask.bitmask;
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return *this;
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}
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SSE_MXCSR::operator x86Emitter::xIndirect32() const
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{
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return x86Emitter::ptr32[&bitmask];
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}
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namespace x86Emitter
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{
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// ------------------------------------------------------------------------
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// SimdPrefix - If the lower byte of the opcode is 0x38 or 0x3a, then the opcode is
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// treated as a 16 bit value (in SSE 0x38 and 0x3a denote prefixes for extended SSE3/4
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// instructions). Any other lower value assumes the upper value is 0 and ignored.
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// Non-zero upper bytes, when the lower byte is not the 0x38 or 0x3a prefix, will
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// generate an assertion.
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//
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__emitinline void SimdPrefix(u8 prefix, u16 opcode)
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{
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#ifdef __M_X86_64
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pxAssertMsg(prefix == 0, "REX prefix must be just before the opcode");
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#endif
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const bool is16BitOpcode = ((opcode & 0xff) == 0x38) || ((opcode & 0xff) == 0x3a);
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// If the lower byte is not a valid prefix and the upper byte is non-zero it
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// means we made a mistake!
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if (!is16BitOpcode)
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pxAssert((opcode >> 8) == 0);
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if (prefix != 0)
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{
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if (is16BitOpcode)
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xWrite32((opcode << 16) | 0x0f00 | prefix);
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else
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{
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xWrite16(0x0f00 | prefix);
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xWrite8(opcode);
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}
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}
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else
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{
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if (is16BitOpcode)
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{
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xWrite8(0x0f);
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xWrite16(opcode);
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}
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else
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xWrite16((opcode << 8) | 0x0f);
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}
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}
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const xImplSimd_DestRegEither xPAND = {0x66, 0xdb};
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const xImplSimd_DestRegEither xPANDN = {0x66, 0xdf};
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const xImplSimd_DestRegEither xPOR = {0x66, 0xeb};
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const xImplSimd_DestRegEither xPXOR = {0x66, 0xef};
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// [SSE-4.1] Performs a bitwise AND of dest against src, and sets the ZF flag
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// only if all bits in the result are 0. PTEST also sets the CF flag according
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// to the following condition: (xmm2/m128 AND NOT xmm1) == 0;
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const xImplSimd_DestRegSSE xPTEST = {0x66, 0x1738};
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// =====================================================================================================
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// SSE Conversion Operations, as looney as they are.
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// =====================================================================================================
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// These enforce pointer strictness for Indirect forms, due to the otherwise completely confusing
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// nature of the functions. (so if a function expects an m32, you must use (u32*) or ptr32[]).
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//
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__fi void xCVTDQ2PD(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0xf3, 0xe6); }
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__fi void xCVTDQ2PD(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSSE(0xf3, 0xe6); }
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__fi void xCVTDQ2PS(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0x00, 0x5b); }
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__fi void xCVTDQ2PS(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0x00, 0x5b); }
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__fi void xCVTPD2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0xf2, 0xe6); }
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__fi void xCVTPD2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0xf2, 0xe6); }
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__fi void xCVTPD2PS(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0x66, 0x5a); }
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__fi void xCVTPD2PS(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0x66, 0x5a); }
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__fi void xCVTPI2PD(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSSE(0x66, 0x2a); }
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__fi void xCVTPI2PS(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSSE(0x00, 0x2a); }
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__fi void xCVTPS2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0x66, 0x5b); }
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__fi void xCVTPS2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0x66, 0x5b); }
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__fi void xCVTPS2PD(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0x00, 0x5a); }
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__fi void xCVTPS2PD(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSSE(0x00, 0x5a); }
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__fi void xCVTSD2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSSE(0xf2, 0x2d); }
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__fi void xCVTSD2SI(const xRegister32or64& to, const xIndirect64& from) { OpWriteSSE(0xf2, 0x2d); }
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__fi void xCVTSD2SS(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0xf2, 0x5a); }
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__fi void xCVTSD2SS(const xRegisterSSE& to, const xIndirect64& from) { OpWriteSSE(0xf2, 0x5a); }
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__fi void xCVTSI2SS(const xRegisterSSE& to, const xRegister32or64& from) { OpWriteSSE(0xf3, 0x2a); }
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__fi void xCVTSI2SS(const xRegisterSSE& to, const xIndirect32& from) { OpWriteSSE(0xf3, 0x2a); }
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__fi void xCVTSS2SD(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0xf3, 0x5a); }
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__fi void xCVTSS2SD(const xRegisterSSE& to, const xIndirect32& from) { OpWriteSSE(0xf3, 0x5a); }
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__fi void xCVTSS2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSSE(0xf3, 0x2d); }
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__fi void xCVTSS2SI(const xRegister32or64& to, const xIndirect32& from) { OpWriteSSE(0xf3, 0x2d); }
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__fi void xCVTTPD2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0x66, 0xe6); }
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__fi void xCVTTPD2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0x66, 0xe6); }
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__fi void xCVTTPS2DQ(const xRegisterSSE& to, const xRegisterSSE& from) { OpWriteSSE(0xf3, 0x5b); }
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__fi void xCVTTPS2DQ(const xRegisterSSE& to, const xIndirect128& from) { OpWriteSSE(0xf3, 0x5b); }
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__fi void xCVTTSD2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSSE(0xf2, 0x2c); }
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__fi void xCVTTSD2SI(const xRegister32or64& to, const xIndirect64& from) { OpWriteSSE(0xf2, 0x2c); }
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__fi void xCVTTSS2SI(const xRegister32or64& to, const xRegisterSSE& from) { OpWriteSSE(0xf3, 0x2c); }
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__fi void xCVTTSS2SI(const xRegister32or64& to, const xIndirect32& from) { OpWriteSSE(0xf3, 0x2c); }
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// ------------------------------------------------------------------------
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void xImplSimd_DestRegSSE::operator()(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(Prefix, Opcode); }
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void xImplSimd_DestRegSSE::operator()(const xRegisterSSE& to, const xIndirectVoid& from) const { OpWriteSSE(Prefix, Opcode); }
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void xImplSimd_DestRegImmSSE::operator()(const xRegisterSSE& to, const xRegisterSSE& from, u8 imm) const { xOpWrite0F(Prefix, Opcode, to, from, imm); }
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void xImplSimd_DestRegImmSSE::operator()(const xRegisterSSE& to, const xIndirectVoid& from, u8 imm) const { xOpWrite0F(Prefix, Opcode, to, from, imm); }
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void xImplSimd_DestRegEither::operator()(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(Prefix, Opcode); }
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void xImplSimd_DestRegEither::operator()(const xRegisterSSE& to, const xIndirectVoid& from) const { OpWriteSSE(Prefix, Opcode); }
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void xImplSimd_DestSSE_CmpImm::operator()(const xRegisterSSE& to, const xRegisterSSE& from, SSE2_ComparisonType imm) const { xOpWrite0F(Prefix, Opcode, to, from, imm); }
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void xImplSimd_DestSSE_CmpImm::operator()(const xRegisterSSE& to, const xIndirectVoid& from, SSE2_ComparisonType imm) const { xOpWrite0F(Prefix, Opcode, to, from, imm); }
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// =====================================================================================================
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// SIMD Arithmetic Instructions
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// =====================================================================================================
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void _SimdShiftHelper::operator()(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(Prefix, Opcode); }
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void _SimdShiftHelper::operator()(const xRegisterSSE& to, const xIndirectVoid& from) const { OpWriteSSE(Prefix, Opcode); }
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void _SimdShiftHelper::operator()(const xRegisterSSE& to, u8 imm8) const
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{
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xOpWrite0F(0x66, OpcodeImm, (int)Modcode, to);
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xWrite8(imm8);
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}
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void xImplSimd_Shift::DQ(const xRegisterSSE& to, u8 imm8) const
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{
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xOpWrite0F(0x66, 0x73, (int)Q.Modcode + 1, to, imm8);
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}
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const xImplSimd_ShiftWithoutQ xPSRA =
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{
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{0x66, 0xe1, 0x71, 4}, // W
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{0x66, 0xe2, 0x72, 4} // D
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};
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const xImplSimd_Shift xPSRL =
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{
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{0x66, 0xd1, 0x71, 2}, // W
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{0x66, 0xd2, 0x72, 2}, // D
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{0x66, 0xd3, 0x73, 2}, // Q
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};
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const xImplSimd_Shift xPSLL =
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{
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{0x66, 0xf1, 0x71, 6}, // W
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{0x66, 0xf2, 0x72, 6}, // D
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{0x66, 0xf3, 0x73, 6}, // Q
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};
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const xImplSimd_AddSub xPADD =
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{
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{0x66, 0xdc + 0x20}, // B
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{0x66, 0xdc + 0x21}, // W
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{0x66, 0xdc + 0x22}, // D
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{0x66, 0xd4}, // Q
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{0x66, 0xdc + 0x10}, // SB
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{0x66, 0xdc + 0x11}, // SW
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{0x66, 0xdc}, // USB
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{0x66, 0xdc + 1}, // USW
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};
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const xImplSimd_AddSub xPSUB =
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{
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{0x66, 0xd8 + 0x20}, // B
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{0x66, 0xd8 + 0x21}, // W
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{0x66, 0xd8 + 0x22}, // D
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{0x66, 0xfb}, // Q
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{0x66, 0xd8 + 0x10}, // SB
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{0x66, 0xd8 + 0x11}, // SW
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{0x66, 0xd8}, // USB
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{0x66, 0xd8 + 1}, // USW
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};
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const xImplSimd_PMul xPMUL =
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{
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{0x66, 0xd5}, // LW
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{0x66, 0xe5}, // HW
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{0x66, 0xe4}, // HUW
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{0x66, 0xf4}, // UDQ
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{0x66, 0x0b38}, // HRSW
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{0x66, 0x4038}, // LD
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{0x66, 0x2838}, // DQ
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};
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const xImplSimd_rSqrt xRSQRT =
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{
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{0x00, 0x52}, // PS
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{0xf3, 0x52} // SS
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};
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const xImplSimd_rSqrt xRCP =
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{
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{0x00, 0x53}, // PS
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{0xf3, 0x53} // SS
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};
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const xImplSimd_Sqrt xSQRT =
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{
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{0x00, 0x51}, // PS
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{0xf3, 0x51}, // SS
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{0xf2, 0x51} // SS
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};
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const xImplSimd_AndNot xANDN =
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{
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{0x00, 0x55}, // PS
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{0x66, 0x55} // PD
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};
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const xImplSimd_PAbsolute xPABS =
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{
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{0x66, 0x1c38}, // B
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{0x66, 0x1d38}, // W
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{0x66, 0x1e38} // D
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};
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const xImplSimd_PSign xPSIGN =
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{
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{0x66, 0x0838}, // B
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{0x66, 0x0938}, // W
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{0x66, 0x0a38}, // D
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};
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const xImplSimd_PMultAdd xPMADD =
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{
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{0x66, 0xf5}, // WD
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{0x66, 0xf438}, // UBSW
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};
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const xImplSimd_HorizAdd xHADD =
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{
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{0xf2, 0x7c}, // PS
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{0x66, 0x7c}, // PD
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};
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const xImplSimd_DotProduct xDP =
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{
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{0x66, 0x403a}, // PS
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{0x66, 0x413a}, // PD
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};
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const xImplSimd_Round xROUND =
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{
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{0x66, 0x083a}, // PS
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{0x66, 0x093a}, // PD
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{0x66, 0x0a3a}, // SS
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{0x66, 0x0b3a}, // SD
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};
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// =====================================================================================================
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// SIMD Comparison Instructions
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// =====================================================================================================
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void xImplSimd_Compare::PS(const xRegisterSSE& to, const xRegisterSSE& from) const { xOpWrite0F(0x00, 0xc2, to, from, (u8)CType); }
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void xImplSimd_Compare::PS(const xRegisterSSE& to, const xIndirectVoid& from) const { xOpWrite0F(0x00, 0xc2, to, from, (u8)CType); }
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void xImplSimd_Compare::PD(const xRegisterSSE& to, const xRegisterSSE& from) const { xOpWrite0F(0x66, 0xc2, to, from, (u8)CType); }
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void xImplSimd_Compare::PD(const xRegisterSSE& to, const xIndirectVoid& from) const { xOpWrite0F(0x66, 0xc2, to, from, (u8)CType); }
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void xImplSimd_Compare::SS(const xRegisterSSE& to, const xRegisterSSE& from) const { xOpWrite0F(0xf3, 0xc2, to, from, (u8)CType); }
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void xImplSimd_Compare::SS(const xRegisterSSE& to, const xIndirectVoid& from) const { xOpWrite0F(0xf3, 0xc2, to, from, (u8)CType); }
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void xImplSimd_Compare::SD(const xRegisterSSE& to, const xRegisterSSE& from) const { xOpWrite0F(0xf2, 0xc2, to, from, (u8)CType); }
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void xImplSimd_Compare::SD(const xRegisterSSE& to, const xIndirectVoid& from) const { xOpWrite0F(0xf2, 0xc2, to, from, (u8)CType); }
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const xImplSimd_MinMax xMIN =
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{
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{0x00, 0x5d}, // PS
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{0x66, 0x5d}, // PD
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{0xf3, 0x5d}, // SS
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{0xf2, 0x5d}, // SD
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};
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const xImplSimd_MinMax xMAX =
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{
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{0x00, 0x5f}, // PS
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{0x66, 0x5f}, // PD
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{0xf3, 0x5f}, // SS
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{0xf2, 0x5f}, // SD
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};
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// [TODO] : Merge this into the xCMP class, so that they are notation as: xCMP.EQ
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const xImplSimd_Compare xCMPEQ = {SSE2_Equal};
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const xImplSimd_Compare xCMPLT = {SSE2_Less};
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const xImplSimd_Compare xCMPLE = {SSE2_LessOrEqual};
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const xImplSimd_Compare xCMPUNORD = {SSE2_LessOrEqual};
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const xImplSimd_Compare xCMPNE = {SSE2_NotEqual};
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const xImplSimd_Compare xCMPNLT = {SSE2_NotLess};
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const xImplSimd_Compare xCMPNLE = {SSE2_NotLessOrEqual};
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const xImplSimd_Compare xCMPORD = {SSE2_Ordered};
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const xImplSimd_COMI xCOMI =
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{
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{0x00, 0x2f}, // SS
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{0x66, 0x2f}, // SD
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};
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const xImplSimd_COMI xUCOMI =
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{
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{0x00, 0x2e}, // SS
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{0x66, 0x2e}, // SD
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};
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const xImplSimd_PCompare xPCMP =
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{
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{0x66, 0x74}, // EQB
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{0x66, 0x75}, // EQW
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{0x66, 0x76}, // EQD
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{0x66, 0x64}, // GTB
|
|
{0x66, 0x65}, // GTW
|
|
{0x66, 0x66}, // GTD
|
|
};
|
|
|
|
const xImplSimd_PMinMax xPMIN =
|
|
{
|
|
{0x66, 0xda}, // UB
|
|
{0x66, 0xea}, // SW
|
|
{0x66, 0x3838}, // SB
|
|
{0x66, 0x3938}, // SD
|
|
|
|
{0x66, 0x3a38}, // UW
|
|
{0x66, 0x3b38}, // UD
|
|
};
|
|
|
|
const xImplSimd_PMinMax xPMAX =
|
|
{
|
|
{0x66, 0xde}, // UB
|
|
{0x66, 0xee}, // SW
|
|
{0x66, 0x3c38}, // SB
|
|
{0x66, 0x3d38}, // SD
|
|
|
|
{0x66, 0x3e38}, // UW
|
|
{0x66, 0x3f38}, // UD
|
|
};
|
|
|
|
// =====================================================================================================
|
|
// SIMD Shuffle/Pack (Shuffle puck?)
|
|
// =====================================================================================================
|
|
|
|
__fi void xImplSimd_Shuffle::_selector_assertion_check(u8 selector) const
|
|
{
|
|
pxAssertMsg((selector & ~3) == 0,
|
|
"Invalid immediate operand on SSE Shuffle: Upper 6 bits of the SSE Shuffle-PD Selector are reserved and must be zero.");
|
|
}
|
|
|
|
void xImplSimd_Shuffle::PS(const xRegisterSSE& to, const xRegisterSSE& from, u8 selector) const
|
|
{
|
|
xOpWrite0F(0xc6, to, from, selector);
|
|
}
|
|
|
|
void xImplSimd_Shuffle::PS(const xRegisterSSE& to, const xIndirectVoid& from, u8 selector) const
|
|
{
|
|
xOpWrite0F(0xc6, to, from, selector);
|
|
}
|
|
|
|
void xImplSimd_Shuffle::PD(const xRegisterSSE& to, const xRegisterSSE& from, u8 selector) const
|
|
{
|
|
_selector_assertion_check(selector);
|
|
xOpWrite0F(0x66, 0xc6, to, from, selector & 0x3);
|
|
}
|
|
|
|
void xImplSimd_Shuffle::PD(const xRegisterSSE& to, const xIndirectVoid& from, u8 selector) const
|
|
{
|
|
_selector_assertion_check(selector);
|
|
xOpWrite0F(0x66, 0xc6, to, from, selector & 0x3);
|
|
}
|
|
|
|
void xImplSimd_InsertExtractHelper::operator()(const xRegisterSSE& to, const xRegister32& from, u8 imm8) const
|
|
{
|
|
xOpWrite0F(0x66, Opcode, to, from, imm8);
|
|
}
|
|
|
|
void xImplSimd_InsertExtractHelper::operator()(const xRegisterSSE& to, const xIndirectVoid& from, u8 imm8) const
|
|
{
|
|
xOpWrite0F(0x66, Opcode, to, from, imm8);
|
|
}
|
|
|
|
void xImplSimd_PInsert::W(const xRegisterSSE& to, const xRegister32& from, u8 imm8) const { xOpWrite0F(0x66, 0xc4, to, from, imm8); }
|
|
void xImplSimd_PInsert::W(const xRegisterSSE& to, const xIndirectVoid& from, u8 imm8) const { xOpWrite0F(0x66, 0xc4, to, from, imm8); }
|
|
|
|
void SimdImpl_PExtract::W(const xRegister32& to, const xRegisterSSE& from, u8 imm8) const { xOpWrite0F(0x66, 0xc5, to, from, imm8); }
|
|
void SimdImpl_PExtract::W(const xIndirectVoid& dest, const xRegisterSSE& from, u8 imm8) const { xOpWrite0F(0x66, 0x153a, from, dest, imm8); }
|
|
|
|
const xImplSimd_Shuffle xSHUF = {};
|
|
|
|
const xImplSimd_PShuffle xPSHUF =
|
|
{
|
|
{0x66, 0x70}, // D
|
|
{0xf2, 0x70}, // LW
|
|
{0xf3, 0x70}, // HW
|
|
|
|
{0x66, 0x0038}, // B
|
|
};
|
|
|
|
const SimdImpl_PUnpack xPUNPCK =
|
|
{
|
|
{0x66, 0x60}, // LBW
|
|
{0x66, 0x61}, // LWD
|
|
{0x66, 0x62}, // LDQ
|
|
{0x66, 0x6c}, // LQDQ
|
|
|
|
{0x66, 0x68}, // HBW
|
|
{0x66, 0x69}, // HWD
|
|
{0x66, 0x6a}, // HDQ
|
|
{0x66, 0x6d}, // HQDQ
|
|
};
|
|
|
|
const SimdImpl_Pack xPACK =
|
|
{
|
|
{0x66, 0x63}, // SSWB
|
|
{0x66, 0x6b}, // SSDW
|
|
{0x66, 0x67}, // USWB
|
|
{0x66, 0x2b38}, // USDW
|
|
};
|
|
|
|
const xImplSimd_Unpack xUNPCK =
|
|
{
|
|
{0x00, 0x15}, // HPS
|
|
{0x66, 0x15}, // HPD
|
|
{0x00, 0x14}, // LPS
|
|
{0x66, 0x14}, // LPD
|
|
};
|
|
|
|
const xImplSimd_PInsert xPINSR =
|
|
{
|
|
{0x203a}, // B
|
|
{0x223a}, // D
|
|
};
|
|
|
|
const SimdImpl_PExtract xPEXTR =
|
|
{
|
|
{0x143a}, // B
|
|
{0x163a}, // D
|
|
};
|
|
|
|
// =====================================================================================================
|
|
// SIMD Move And Blend Instructions
|
|
// =====================================================================================================
|
|
|
|
void xImplSimd_MovHL::PS(const xRegisterSSE& to, const xIndirectVoid& from) const { xOpWrite0F(Opcode, to, from); }
|
|
void xImplSimd_MovHL::PS(const xIndirectVoid& to, const xRegisterSSE& from) const { xOpWrite0F(Opcode + 1, from, to); }
|
|
|
|
void xImplSimd_MovHL::PD(const xRegisterSSE& to, const xIndirectVoid& from) const { xOpWrite0F(0x66, Opcode, to, from); }
|
|
void xImplSimd_MovHL::PD(const xIndirectVoid& to, const xRegisterSSE& from) const { xOpWrite0F(0x66, Opcode + 1, from, to); }
|
|
|
|
void xImplSimd_MovHL_RtoR::PS(const xRegisterSSE& to, const xRegisterSSE& from) const { xOpWrite0F(Opcode, to, from); }
|
|
void xImplSimd_MovHL_RtoR::PD(const xRegisterSSE& to, const xRegisterSSE& from) const { xOpWrite0F(0x66, Opcode, to, from); }
|
|
|
|
static const u16 MovPS_OpAligned = 0x28; // Aligned [aps] form
|
|
static const u16 MovPS_OpUnaligned = 0x10; // unaligned [ups] form
|
|
|
|
void xImplSimd_MoveSSE::operator()(const xRegisterSSE& to, const xRegisterSSE& from) const
|
|
{
|
|
if (to != from)
|
|
xOpWrite0F(Prefix, MovPS_OpAligned, to, from);
|
|
}
|
|
|
|
void xImplSimd_MoveSSE::operator()(const xRegisterSSE& to, const xIndirectVoid& from) const
|
|
{
|
|
// ModSib form is aligned if it's displacement-only and the displacement is aligned:
|
|
bool isReallyAligned = isAligned || (((from.Displacement & 0x0f) == 0) && from.Index.IsEmpty() && from.Base.IsEmpty());
|
|
|
|
xOpWrite0F(Prefix, isReallyAligned ? MovPS_OpAligned : MovPS_OpUnaligned, to, from);
|
|
}
|
|
|
|
void xImplSimd_MoveSSE::operator()(const xIndirectVoid& to, const xRegisterSSE& from) const
|
|
{
|
|
// ModSib form is aligned if it's displacement-only and the displacement is aligned:
|
|
bool isReallyAligned = isAligned || ((to.Displacement & 0x0f) == 0 && to.Index.IsEmpty() && to.Base.IsEmpty());
|
|
xOpWrite0F(Prefix, isReallyAligned ? MovPS_OpAligned + 1 : MovPS_OpUnaligned + 1, from, to);
|
|
}
|
|
|
|
static const u8 MovDQ_PrefixAligned = 0x66; // Aligned [dqa] form
|
|
static const u8 MovDQ_PrefixUnaligned = 0xf3; // unaligned [dqu] form
|
|
|
|
void xImplSimd_MoveDQ::operator()(const xRegisterSSE& to, const xRegisterSSE& from) const
|
|
{
|
|
if (to != from)
|
|
xOpWrite0F(MovDQ_PrefixAligned, 0x6f, to, from);
|
|
}
|
|
|
|
void xImplSimd_MoveDQ::operator()(const xRegisterSSE& to, const xIndirectVoid& from) const
|
|
{
|
|
// ModSib form is aligned if it's displacement-only and the displacement is aligned:
|
|
bool isReallyAligned = isAligned || ((from.Displacement & 0x0f) == 0 && from.Index.IsEmpty() && from.Base.IsEmpty());
|
|
xOpWrite0F(isReallyAligned ? MovDQ_PrefixAligned : MovDQ_PrefixUnaligned, 0x6f, to, from);
|
|
}
|
|
|
|
void xImplSimd_MoveDQ::operator()(const xIndirectVoid& to, const xRegisterSSE& from) const
|
|
{
|
|
// ModSib form is aligned if it's displacement-only and the displacement is aligned:
|
|
bool isReallyAligned = isAligned || ((to.Displacement & 0x0f) == 0 && to.Index.IsEmpty() && to.Base.IsEmpty());
|
|
|
|
// use opcode 0x7f : alternate ModRM encoding (reverse src/dst)
|
|
xOpWrite0F(isReallyAligned ? MovDQ_PrefixAligned : MovDQ_PrefixUnaligned, 0x7f, from, to);
|
|
}
|
|
|
|
void xImplSimd_PMove::BW(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase); }
|
|
void xImplSimd_PMove::BW(const xRegisterSSE& to, const xIndirect64& from) const { OpWriteSSE(0x66, OpcodeBase); }
|
|
|
|
void xImplSimd_PMove::BD(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x100); }
|
|
void xImplSimd_PMove::BD(const xRegisterSSE& to, const xIndirect32& from) const { OpWriteSSE(0x66, OpcodeBase + 0x100); }
|
|
|
|
void xImplSimd_PMove::BQ(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x200); }
|
|
void xImplSimd_PMove::BQ(const xRegisterSSE& to, const xIndirect16& from) const { OpWriteSSE(0x66, OpcodeBase + 0x200); }
|
|
|
|
void xImplSimd_PMove::WD(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x300); }
|
|
void xImplSimd_PMove::WD(const xRegisterSSE& to, const xIndirect64& from) const { OpWriteSSE(0x66, OpcodeBase + 0x300); }
|
|
|
|
void xImplSimd_PMove::WQ(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x400); }
|
|
void xImplSimd_PMove::WQ(const xRegisterSSE& to, const xIndirect32& from) const { OpWriteSSE(0x66, OpcodeBase + 0x400); }
|
|
|
|
void xImplSimd_PMove::DQ(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x500); }
|
|
void xImplSimd_PMove::DQ(const xRegisterSSE& to, const xIndirect64& from) const { OpWriteSSE(0x66, OpcodeBase + 0x500); }
|
|
|
|
|
|
const xImplSimd_MoveSSE xMOVAPS = {0x00, true};
|
|
const xImplSimd_MoveSSE xMOVUPS = {0x00, false};
|
|
|
|
#ifdef ALWAYS_USE_MOVAPS
|
|
const xImplSimd_MoveSSE xMOVDQA = {0x00, true};
|
|
const xImplSimd_MoveSSE xMOVAPD = {0x00, true};
|
|
|
|
const xImplSimd_MoveSSE xMOVDQU = {0x00, false};
|
|
const xImplSimd_MoveSSE xMOVUPD = {0x00, false};
|
|
#else
|
|
const xImplSimd_MoveDQ xMOVDQA = {0x66, true};
|
|
const xImplSimd_MoveSSE xMOVAPD = {0x66, true};
|
|
|
|
const xImplSimd_MoveDQ xMOVDQU = {0xf3, false};
|
|
const xImplSimd_MoveSSE xMOVUPD = {0x66, false};
|
|
#endif
|
|
|
|
|
|
const xImplSimd_MovHL xMOVH = {0x16};
|
|
const xImplSimd_MovHL xMOVL = {0x12};
|
|
|
|
const xImplSimd_MovHL_RtoR xMOVLH = {0x16};
|
|
const xImplSimd_MovHL_RtoR xMOVHL = {0x12};
|
|
|
|
const xImplSimd_Blend xBLEND =
|
|
{
|
|
{0x66, 0x0c3a}, // PS
|
|
{0x66, 0x0d3a}, // PD
|
|
{0x66, 0x1438}, // VPS
|
|
{0x66, 0x1538}, // VPD
|
|
};
|
|
|
|
const xImplSimd_PMove xPMOVSX = {0x2038};
|
|
const xImplSimd_PMove xPMOVZX = {0x3038};
|
|
|
|
// [SSE-3]
|
|
const xImplSimd_DestRegSSE xMOVSLDUP = {0xf3, 0x12};
|
|
|
|
// [SSE-3]
|
|
const xImplSimd_DestRegSSE xMOVSHDUP = {0xf3, 0x16};
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
// MMX Mov Instructions (MOVD, MOVQ, MOVSS).
|
|
//
|
|
// Notes:
|
|
// * Some of the functions have been renamed to more clearly reflect what they actually
|
|
// do. Namely we've affixed "ZX" to several MOVs that take a register as a destination
|
|
// since that's what they do (MOVD clears upper 32/96 bits, etc).
|
|
//
|
|
// * MOVD has valid forms for MMX and XMM registers.
|
|
//
|
|
|
|
__fi void xMOVDZX(const xRegisterSSE& to, const xRegister32or64& from) { xOpWrite0F(0x66, 0x6e, to, from); }
|
|
__fi void xMOVDZX(const xRegisterSSE& to, const xIndirectVoid& src) { xOpWrite0F(0x66, 0x6e, to, src); }
|
|
|
|
__fi void xMOVD(const xRegister32or64& to, const xRegisterSSE& from) { xOpWrite0F(0x66, 0x7e, from, to); }
|
|
__fi void xMOVD(const xIndirectVoid& dest, const xRegisterSSE& from) { xOpWrite0F(0x66, 0x7e, from, dest); }
|
|
|
|
// Moves from XMM to XMM, with the *upper 64 bits* of the destination register
|
|
// being cleared to zero.
|
|
__fi void xMOVQZX(const xRegisterSSE& to, const xRegisterSSE& from) { xOpWrite0F(0xf3, 0x7e, to, from); }
|
|
|
|
// Moves from XMM to XMM, with the *upper 64 bits* of the destination register
|
|
// being cleared to zero.
|
|
__fi void xMOVQZX(const xRegisterSSE& to, const xIndirectVoid& src) { xOpWrite0F(0xf3, 0x7e, to, src); }
|
|
|
|
// Moves from XMM to XMM, with the *upper 64 bits* of the destination register
|
|
// being cleared to zero.
|
|
__fi void xMOVQZX(const xRegisterSSE& to, const void* src) { xOpWrite0F(0xf3, 0x7e, to, src); }
|
|
|
|
// Moves lower quad of XMM to ptr64 (no bits are cleared)
|
|
__fi void xMOVQ(const xIndirectVoid& dest, const xRegisterSSE& from) { xOpWrite0F(0x66, 0xd6, from, dest); }
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
|
|
#define IMPLEMENT_xMOVS(ssd, prefix) \
|
|
__fi void xMOV##ssd(const xRegisterSSE& to, const xRegisterSSE& from) \
|
|
{ \
|
|
if (to != from) \
|
|
xOpWrite0F(prefix, 0x10, to, from); \
|
|
} \
|
|
__fi void xMOV##ssd##ZX(const xRegisterSSE& to, const xIndirectVoid& from) { xOpWrite0F(prefix, 0x10, to, from); } \
|
|
__fi void xMOV##ssd(const xIndirectVoid& to, const xRegisterSSE& from) { xOpWrite0F(prefix, 0x11, from, to); }
|
|
|
|
IMPLEMENT_xMOVS(SS, 0xf3)
|
|
IMPLEMENT_xMOVS(SD, 0xf2)
|
|
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
// Non-temporal movs only support a register as a target (ie, load form only, no stores)
|
|
//
|
|
|
|
__fi void xMOVNTDQA(const xRegisterSSE& to, const xIndirectVoid& from)
|
|
{
|
|
xOpWrite0F(0x66, 0x2a38, to.Id, from);
|
|
}
|
|
|
|
__fi void xMOVNTDQA(const xIndirectVoid& to, const xRegisterSSE& from) { xOpWrite0F(0x66, 0xe7, from, to); }
|
|
|
|
__fi void xMOVNTPD(const xIndirectVoid& to, const xRegisterSSE& from) { xOpWrite0F(0x66, 0x2b, from, to); }
|
|
__fi void xMOVNTPS(const xIndirectVoid& to, const xRegisterSSE& from) { xOpWrite0F(0x2b, from, to); }
|
|
|
|
// ------------------------------------------------------------------------
|
|
|
|
__fi void xMOVMSKPS(const xRegister32& to, const xRegisterSSE& from) { xOpWrite0F(0x50, to, from); }
|
|
__fi void xMOVMSKPD(const xRegister32& to, const xRegisterSSE& from) { xOpWrite0F(0x66, 0x50, to, from, true); }
|
|
|
|
// xMASKMOV:
|
|
// Selectively write bytes from mm1/xmm1 to memory location using the byte mask in mm2/xmm2.
|
|
// The default memory location is specified by DS:EDI. The most significant bit in each byte
|
|
// of the mask operand determines whether the corresponding byte in the source operand is
|
|
// written to the corresponding byte location in memory.
|
|
__fi void xMASKMOV(const xRegisterSSE& to, const xRegisterSSE& from) { xOpWrite0F(0x66, 0xf7, to, from); }
|
|
|
|
// xPMOVMSKB:
|
|
// Creates a mask made up of the most significant bit of each byte of the source
|
|
// operand and stores the result in the low byte or word of the destination operand.
|
|
// Upper bits of the destination are cleared to zero.
|
|
//
|
|
// When operating on a 64-bit (MMX) source, the byte mask is 8 bits; when operating on
|
|
// 128-bit (SSE) source, the byte mask is 16-bits.
|
|
//
|
|
__fi void xPMOVMSKB(const xRegister32or64& to, const xRegisterSSE& from) { xOpWrite0F(0x66, 0xd7, to, from); }
|
|
|
|
// [sSSE-3] Concatenates dest and source operands into an intermediate composite,
|
|
// shifts the composite at byte granularity to the right by a constant immediate,
|
|
// and extracts the right-aligned result into the destination.
|
|
//
|
|
__fi void xPALIGNR(const xRegisterSSE& to, const xRegisterSSE& from, u8 imm8) { xOpWrite0F(0x66, 0x0f3a, to, from, imm8); }
|
|
|
|
|
|
// --------------------------------------------------------------------------------------
|
|
// INSERTPS / EXTRACTPS [SSE4.1 only!]
|
|
// --------------------------------------------------------------------------------------
|
|
// [TODO] these might be served better as classes, especially if other instructions use
|
|
// the M32,sse,imm form (I forget offhand if any do).
|
|
|
|
|
|
// [SSE-4.1] Insert a single-precision floating-point value from src into a specified
|
|
// location in dest, and selectively zero out the data elements in dest according to
|
|
// the mask field in the immediate byte. The source operand can be a memory location
|
|
// (32 bits) or an XMM register (lower 32 bits used).
|
|
//
|
|
// Imm8 provides three fields:
|
|
// * COUNT_S: The value of Imm8[7:6] selects the dword element from src. It is 0 if
|
|
// the source is a memory operand.
|
|
// * COUNT_D: The value of Imm8[5:4] selects the target dword element in dest.
|
|
// * ZMASK: Each bit of Imm8[3:0] selects a dword element in dest to be written
|
|
// with 0.0 if set to 1.
|
|
//
|
|
__emitinline void xINSERTPS(const xRegisterSSE& to, const xRegisterSSE& from, u8 imm8) { xOpWrite0F(0x66, 0x213a, to, from, imm8); }
|
|
__emitinline void xINSERTPS(const xRegisterSSE& to, const xIndirect32& from, u8 imm8) { xOpWrite0F(0x66, 0x213a, to, from, imm8); }
|
|
|
|
// [SSE-4.1] Extract a single-precision floating-point value from src at an offset
|
|
// determined by imm8[1-0]*32. The extracted single precision floating-point value
|
|
// is stored into the low 32-bits of dest (or at a 32-bit memory pointer).
|
|
//
|
|
__emitinline void xEXTRACTPS(const xRegister32or64& to, const xRegisterSSE& from, u8 imm8) { xOpWrite0F(0x66, 0x173a, to, from, imm8); }
|
|
__emitinline void xEXTRACTPS(const xIndirect32& dest, const xRegisterSSE& from, u8 imm8) { xOpWrite0F(0x66, 0x173a, from, dest, imm8); }
|
|
|
|
|
|
// =====================================================================================================
|
|
// Ungrouped Instructions!
|
|
// =====================================================================================================
|
|
|
|
|
|
// Store Streaming SIMD Extension Control/Status to Mem32.
|
|
__emitinline void xSTMXCSR(const xIndirect32& dest)
|
|
{
|
|
xOpWrite0F(0, 0xae, 3, dest);
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}
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|
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// Load Streaming SIMD Extension Control/Status from Mem32.
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__emitinline void xLDMXCSR(const xIndirect32& src)
|
|
{
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xOpWrite0F(0, 0xae, 2, src);
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|
}
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// Save x87 FPU, MMX Technology, and SSE State to buffer
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|
// Target buffer must be at least 512 bytes in length to hold the result.
|
|
__emitinline void xFXSAVE(const xIndirectVoid& dest)
|
|
{
|
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xOpWrite0F(0, 0xae, 0, dest);
|
|
}
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|
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// Restore x87 FPU, MMX , XMM, and MXCSR State.
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|
// Source buffer should be 512 bytes in length.
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__emitinline void xFXRSTOR(const xIndirectVoid& src)
|
|
{
|
|
xOpWrite0F(0, 0xae, 1, src);
|
|
}
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} // namespace x86Emitter
|