mirror of https://github.com/PCSX2/pcsx2.git
711 lines
18 KiB
C++
711 lines
18 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2014-2014 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "MipsAssembler.h"
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// just an empty class, so that it's not necessary to remove all the calls manually
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// will make it easier to update if there are changes later on
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class Logger
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{
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public:
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enum ErrorType { Warning, Error, FatalError, Notice };
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static void printError(ErrorType type, const wchar_t* text, ...)
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{
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//
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}
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static void queueError(ErrorType type, const wchar_t* text, ...)
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{
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//
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}
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};
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const tMipsRegister MipsRegister[] = {
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{ "r0", 0, 2 }, { "zero", 0, 4}, { "$0", 0, 2 }, { "$zero", 0, 5 },
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{ "at", 1, 2 }, { "r1", 1, 2 }, { "$1", 1, 2 }, { "$at", 1, 3 },
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{ "v0", 2, 2 }, { "r2", 2, 2 }, { "$v0", 2, 3 },
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{ "v1", 3, 2 }, { "r3", 3, 2 }, { "$v1", 3, 3 },
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{ "a0", 4, 2 }, { "r4", 4, 2 }, { "$a0", 4, 3 },
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{ "a1", 5, 2 }, { "r5", 5, 2 }, { "$a1", 5, 3 },
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{ "a2", 6, 2 }, { "r6", 6, 2 }, { "$a2", 6, 3 },
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{ "a3", 7, 2 }, { "r7", 7, 2 }, { "$a3", 7, 3 },
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{ "t0", 8, 2 }, { "r8", 8, 2 }, { "$t0", 8, 3 },
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{ "t1", 9, 2 }, { "r9", 9, 2 }, { "$t1", 9, 3 },
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{ "t2", 10, 2 }, { "r10", 10, 3 }, { "$t2", 10, 3 },
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{ "t3", 11, 2 }, { "r11", 11, 3 }, { "$t3", 11, 3 },
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{ "t4", 12, 2 }, { "r12", 12, 3 }, { "$t4", 12, 3 },
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{ "t5", 13, 2 }, { "r13", 13, 3 }, { "$t5", 13, 3 },
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{ "t6", 14, 2 }, { "r14", 14, 3 }, { "$t6", 14, 3 },
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{ "t7", 15, 2 }, { "r15", 15, 3 }, { "$t7", 15, 3 },
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{ "s0", 16, 2 }, { "r16", 16, 3 }, { "$s0", 16, 3 },
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{ "s1", 17, 2 }, { "r17", 17, 3 }, { "$s1", 17, 3 },
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{ "s2", 18, 2 }, { "r18", 18, 3 }, { "$s2", 18, 3 },
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{ "s3", 19, 2 }, { "r19", 19, 3 }, { "$s3", 19, 3 },
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{ "s4", 20, 2 }, { "r20", 20, 3 }, { "$s4", 20, 3 },
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{ "s5", 21, 2 }, { "r21", 21, 3 }, { "$s5", 21, 3 },
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{ "s6", 22, 2 }, { "r22", 22, 3 }, { "$s6", 22, 3 },
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{ "s7", 23, 2 }, { "r23", 23, 3 }, { "$s7", 23, 3 },
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{ "t8", 24, 2 }, { "r24", 24, 3 }, { "$t8", 24, 3 },
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{ "t9", 25, 2 }, { "r25", 25, 3 }, { "$t9", 25, 3 },
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{ "k0", 26, 2 }, { "r26", 26, 3 }, { "$k0", 26, 3 },
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{ "k1", 27, 2 }, { "r27", 27, 3 }, { "$k1", 27, 3 },
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{ "gp", 28, 2 }, { "r28", 28, 3 }, { "$gp", 28, 3 },
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{ "sp", 29, 2 }, { "r29", 29, 3 }, { "$sp", 29, 3 },
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{ "fp", 30, 2 }, { "r30", 30, 3 }, { "$fp", 30, 3 },
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{ "ra", 31, 2 }, { "r31", 31, 3 }, { "$ra", 31, 3 },
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{ NULL, -1, 0}
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};
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const tMipsRegister MipsFloatRegister[] = {
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{ "f0", 0, 2}, { "$f0", 0, 3 },
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{ "f1", 1, 2}, { "$f1", 1, 3 },
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{ "f2", 2, 2}, { "$f2", 2, 3 },
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{ "f3", 3, 2}, { "$f3", 3, 3 },
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{ "f4", 4, 2}, { "$f4", 4, 3 },
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{ "f5", 5, 2}, { "$f5", 5, 3 },
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{ "f6", 6, 2}, { "$f6", 6, 3 },
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{ "f7", 7, 2}, { "$f7", 7, 3 },
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{ "f8", 8, 2}, { "$f8", 8, 3 },
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{ "f9", 9, 2}, { "$f9", 9, 3 },
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{ "f10", 10, 3}, { "$f10", 10, 4 },
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{ "f11", 11, 3}, { "$f11", 11, 4 },
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{ "f12", 12, 3}, { "$f12", 12, 4 },
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{ "f13", 13, 3}, { "$f13", 13, 4 },
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{ "f14", 14, 3}, { "$f14", 14, 4 },
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{ "f15", 15, 3}, { "$f15", 15, 4 },
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{ "f16", 16, 3}, { "$f16", 16, 4 },
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{ "f17", 17, 3}, { "$f17", 17, 4 },
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{ "f18", 18, 3}, { "$f18", 18, 4 },
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{ "f19", 19, 3}, { "$f19", 19, 4 },
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{ "f20", 20, 3}, { "$f20", 20, 4 },
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{ "f21", 21, 3}, { "$f21", 21, 4 },
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{ "f22", 22, 3}, { "$f22", 22, 4 },
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{ "f23", 23, 3}, { "$f23", 23, 4 },
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{ "f24", 24, 3}, { "$f24", 24, 4 },
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{ "f25", 25, 3}, { "$f25", 25, 4 },
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{ "f26", 26, 3}, { "$f26", 26, 4 },
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{ "f27", 27, 3}, { "$f27", 27, 4 },
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{ "f28", 28, 3}, { "$f28", 28, 4 },
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{ "f29", 29, 3}, { "$f29", 29, 4 },
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{ "f30", 30, 3}, { "$f30", 30, 4 },
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{ "f31", 31, 3}, { "$f31", 31, 4 }
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};
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const tMipsRegister MipsPs2Cop2FpRegister[] = {
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{ "vf0", 0, 3}, { "$vf0", 0, 4 },
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{ "vf1", 1, 3}, { "$vf1", 1, 4 },
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{ "vf2", 2, 3}, { "$vf2", 2, 4 },
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{ "vf3", 3, 3}, { "$vf3", 3, 4 },
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{ "vf4", 4, 3}, { "$vf4", 4, 4 },
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{ "vf5", 5, 3}, { "$vf5", 5, 4 },
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{ "vf6", 6, 3}, { "$vf6", 6, 4 },
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{ "vf7", 7, 3}, { "$vf7", 7, 4 },
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{ "vf8", 8, 3}, { "$vf8", 8, 4 },
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{ "vf9", 9, 3}, { "$vf9", 9, 4 },
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{ "vf00", 0, 4}, { "$vf00", 0, 5 },
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{ "vf01", 1, 4}, { "$vf01", 1, 5 },
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{ "vf02", 2, 4}, { "$vf02", 2, 5 },
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{ "vf03", 3, 4}, { "$vf03", 3, 5 },
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{ "vf04", 4, 4}, { "$vf04", 4, 5 },
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{ "vf05", 5, 4}, { "$vf05", 5, 5 },
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{ "vf06", 6, 4}, { "$vf06", 6, 5 },
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{ "vf07", 7, 4}, { "$vf07", 7, 5 },
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{ "vf08", 8, 4}, { "$vf08", 8, 5 },
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{ "vf09", 9, 4}, { "$vf09", 9, 5 },
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{ "vf10", 10, 4}, { "$vf10", 10, 5 },
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{ "vf11", 11, 4}, { "$vf11", 11, 5 },
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{ "vf12", 12, 4}, { "$vf12", 12, 5 },
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{ "vf13", 13, 4}, { "$vf13", 13, 5 },
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{ "vf14", 14, 4}, { "$vf14", 14, 5 },
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{ "vf15", 15, 4}, { "$vf15", 15, 5 },
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{ "vf16", 16, 4}, { "$vf16", 16, 5 },
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{ "vf17", 17, 4}, { "$vf17", 17, 5 },
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{ "vf18", 18, 4}, { "$vf18", 18, 5 },
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{ "vf19", 19, 4}, { "$vf19", 19, 5 },
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{ "vf20", 20, 4}, { "$vf20", 20, 5 },
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{ "vf21", 21, 4}, { "$vf21", 21, 5 },
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{ "vf22", 22, 4}, { "$vf22", 22, 5 },
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{ "vf23", 23, 4}, { "$vf23", 23, 5 },
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{ "vf24", 24, 4}, { "$vf24", 24, 5 },
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{ "vf25", 25, 4}, { "$vf25", 25, 5 },
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{ "vf26", 26, 4}, { "$vf26", 26, 5 },
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{ "vf27", 27, 4}, { "$vf27", 27, 5 },
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{ "vf28", 28, 4}, { "$vf28", 28, 5 },
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{ "vf29", 29, 4}, { "$vf29", 29, 5 },
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{ "vf30", 30, 4}, { "$vf30", 30, 5 },
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{ "vf31", 31, 4}, { "$vf31", 31, 5 }
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};
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void SplitLine(const char* Line, char* Name, char* Arguments)
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{
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while (*Line == ' ' || *Line == '\t') Line++;
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while (*Line != ' ' && *Line != '\t')
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{
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if (*Line == 0)
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{
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*Name = 0;
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*Arguments = 0;
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return;
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}
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*Name++ = *Line++;
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}
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*Name = 0;
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while (*Line == ' ' || *Line == '\t') Line++;
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while (*Line != 0)
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{
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*Arguments++ = *Line++;
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}
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*Arguments = 0;
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}
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bool MipsAssembleOpcode(const char* line, DebugInterface* cpu, u32 address, u32& dest, std::string& errorText)
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{
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char name[64],args[256];
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SplitLine(line,name,args);
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CMipsInstruction opcode(cpu);
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if (cpu == NULL || !opcode.Load(name,args,(int)address))
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{
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errorText = opcode.getErrorMessage();
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return false;
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}
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if (!opcode.Validate())
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{
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errorText = "Parameter failure.";
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return false;
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}
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opcode.Encode();
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dest = opcode.getEncoding();
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return true;
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}
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bool MipsGetRegister(const char* source, int& RetLen, MipsRegisterInfo& Result)
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{
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for (int z = 0; MipsRegister[z].name != NULL; z++)
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{
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int len = MipsRegister[z].len;
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if (strncmp(MipsRegister[z].name,source,len) == 0) // okay so far
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{
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if (source[len] == ',' || source[len] == '\n' || source[len] == 0
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|| source[len] == ')' || source[len] == '(' || source[len] == '-') // one of these has to come after a register
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{
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memcpy(Result.name,source,len);
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Result.name[len] = 0;
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Result.num = MipsRegister[z].num;
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RetLen = len;
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return true;
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}
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}
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}
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return false;
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}
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int MipsGetRegister(const char* source, int& RetLen)
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{
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for (int z = 0; MipsRegister[z].name != NULL; z++)
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{
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int len = MipsRegister[z].len;
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if (strncmp(MipsRegister[z].name,source,len) == 0) // okay so far
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{
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if (source[len] == ',' || source[len] == '\n' || source[len] == 0
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|| source[len] == ')' || source[len] == '(' || source[len] == '-') // one of these has to come after a register
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{
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RetLen = len;
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return MipsRegister[z].num;
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}
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}
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}
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return -1;
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}
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bool MipsGetFloatRegister(const char* source, int& RetLen, MipsRegisterInfo& Result)
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{
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for (int z = 0; MipsFloatRegister[z].name != NULL; z++)
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{
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int len = MipsFloatRegister[z].len;
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if (strncmp(MipsFloatRegister[z].name,source,len) == 0) // okay so far
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{
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if (source[len] == ',' || source[len] == '\n' || source[len] == 0
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|| source[len] == ')' || source[len] == '(' || source[len] == '-') // one of these has to come after a register
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{
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memcpy(Result.name,source,len);
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Result.name[len] = 0;
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Result.num = MipsFloatRegister[z].num;
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RetLen = len;
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return true;
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}
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}
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}
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return false;
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}
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bool MipsGetPs2VectorRegister(const char* source, int& RetLen, MipsRegisterInfo& Result)
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{
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for (int z = 0; MipsPs2Cop2FpRegister[z].name != NULL; z++)
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{
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int len = MipsPs2Cop2FpRegister[z].len;
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if (strncmp(MipsPs2Cop2FpRegister[z].name,source,len) == 0) // okay so far
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{
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if (source[len] == ',' || source[len] == '\n' || source[len] == 0
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|| source[len] == ')' || source[len] == '(' || source[len] == '-') // one of these has to come after a register
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{
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memcpy(Result.name,source,len);
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Result.name[len] = 0;
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Result.num = MipsPs2Cop2FpRegister[z].num;
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RetLen = len;
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return true;
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}
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}
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}
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return false;
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}
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int MipsGetFloatRegister(const char* source, int& RetLen)
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{
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for (int z = 0; MipsFloatRegister[z].name != NULL; z++)
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{
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int len = MipsFloatRegister[z].len;
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if (strncmp(MipsFloatRegister[z].name,source,len) == 0) // okay so far
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{
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if (source[len] == ',' || source[len] == '\n' || source[len] == 0
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|| source[len] == ')' || source[len] == '(' || source[len] == '-') // one of these has to come after a register
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{
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RetLen = len;
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return MipsFloatRegister[z].num;
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}
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}
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}
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return -1;
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}
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bool MipsCheckImmediate(const char* Source, DebugInterface* cpu, int& dest, int& RetLen)
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{
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char Buffer[512];
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int BufferPos = 0;
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int l;
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if (MipsGetRegister(Source,l) != -1) // error
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{
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return false;
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}
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int SourceLen = 0;
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while (true)
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{
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if (*Source == '\'' && *(Source+2) == '\'')
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{
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Buffer[BufferPos++] = *Source++;
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Buffer[BufferPos++] = *Source++;
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Buffer[BufferPos++] = *Source++;
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SourceLen+=3;
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continue;
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}
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if (*Source == 0 || *Source == '\n' || *Source == ',')
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{
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Buffer[BufferPos] = 0;
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break;
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}
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if ( *Source == ' ' || *Source == '\t')
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{
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Source++;
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SourceLen++;
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continue;
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}
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if (*Source == '(') // could be part of the opcode
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{
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if (MipsGetRegister(Source+1,l) != -1) // end
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{
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Buffer[BufferPos] = 0;
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break;
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}
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}
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Buffer[BufferPos++] = *Source++;
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SourceLen++;
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}
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if (BufferPos == 0) return false;
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RetLen = SourceLen;
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PostfixExpression postfix;
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if (!cpu->initExpression(Buffer,postfix))
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return false;
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u64 value;
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if (!cpu->parseExpression(postfix,value))
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return false;
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dest = (int) value;
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return true;
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}
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CMipsInstruction::CMipsInstruction(DebugInterface* cpu) :
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Opcode(), NoCheckError(false), Loaded(false), RamPos(0),
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registers(), immediateType(MIPS_NOIMMEDIATE), immediate(),
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vfpuSize(0), encoding(0), error()
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{
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this->cpu = cpu;
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}
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bool CMipsInstruction::Load(const char* Name, const char* Params, int RamPos)
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{
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bool paramfail = false;
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NoCheckError = false;
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this->RamPos = RamPos;
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const MipsArchDefinition& arch = mipsArchs[MARCH_PS2];
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for (int z = 0; MipsOpcodes[z].name != NULL; z++)
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{
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if ((MipsOpcodes[z].archs & arch.supportSets) == 0)
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continue;
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if ((MipsOpcodes[z].archs & arch.excludeMask) != 0)
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continue;
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if ((MipsOpcodes[z].flags & MO_64BIT) && !(arch.flags & MO_64BIT))
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continue;
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if ((MipsOpcodes[z].flags & MO_FPU) && !(arch.flags & MO_FPU))
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continue;
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if (parseOpcode(MipsOpcodes[z],Name))
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{
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if (LoadEncoding(MipsOpcodes[z],Params))
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{
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Loaded = true;
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return true;
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}
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paramfail = true;
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}
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}
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if (!NoCheckError)
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{
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if (paramfail)
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{
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error = "Parameter failure.";
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} else {
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error = "Invalid opcode.";
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}
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}
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return false;
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}
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bool CMipsInstruction::parseOpcode(const tMipsOpcode& SourceOpcode, const char* Line)
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{
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vfpuSize = -1;
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const char* SourceEncoding = SourceOpcode.name;
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while (*SourceEncoding != 0)
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{
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if (*Line == 0) return false;
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switch (*SourceEncoding)
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{
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case 'S': // vfpu size
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switch (*Line)
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{
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case 's':
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vfpuSize = 0;
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break;
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case 'p':
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vfpuSize = 1;
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break;
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case 't':
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vfpuSize = 2;
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break;
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case 'q':
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vfpuSize = 3;
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break;
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default:
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return false;
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}
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SourceEncoding++;
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Line++;
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break;
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default:
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if (*SourceEncoding++ != *Line++) return false;
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break;
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}
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}
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// there's something else, bad
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return (*Line == 0);
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}
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bool CMipsInstruction::LoadEncoding(const tMipsOpcode& SourceOpcode, const char* Line)
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{
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int RetLen;
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immediateType = MIPS_NOIMMEDIATE;
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registers.reset();
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if (vfpuSize == -1)
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{
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if (SourceOpcode.flags & MO_VFPU_SINGLE)
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vfpuSize = 0;
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else if (SourceOpcode.flags & MO_VFPU_QUAD)
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vfpuSize = 3;
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}
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const char* SourceEncoding = SourceOpcode.encoding;
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while (*Line == ' ' || *Line == '\t') Line++;
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if (!(*SourceEncoding == 0 && *Line == 0))
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{
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while (*SourceEncoding != 0)
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{
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while (*Line == ' ' || *Line == '\t') Line++;
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if (*Line == 0) return false;
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switch (*SourceEncoding)
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{
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case 'T': // float reg
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if (!MipsGetFloatRegister(Line,RetLen,registers.frt)) return false;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 'D': // float reg
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if (!MipsGetFloatRegister(Line,RetLen,registers.frd)) return false;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 'S': // float reg
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if (!MipsGetFloatRegister(Line,RetLen,registers.frs)) return false;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 't':
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if (!MipsGetRegister(Line,RetLen,registers.grt)) return false;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 'd':
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if (!MipsGetRegister(Line,RetLen,registers.grd)) return false;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 's':
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if (!MipsGetRegister(Line,RetLen,registers.grs)) return false;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 'V': // ps2 vector registers
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switch (*(SourceEncoding+1))
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{
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case 's':
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if (!MipsGetPs2VectorRegister(Line,RetLen,registers.ps2vrs)) return false;
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Line += RetLen;
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break;
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case 't':
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if (!MipsGetPs2VectorRegister(Line,RetLen,registers.ps2vrt)) return false;
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Line += RetLen;
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break;
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case 'd':
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if (!MipsGetPs2VectorRegister(Line,RetLen,registers.ps2vrd)) return false;
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Line += RetLen;
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break;
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default:
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return false;
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}
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SourceEncoding += 2;
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break;
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case 'a': // 5 bit immediate
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if (!MipsCheckImmediate(Line,cpu,immediate.originalValue,RetLen)) return false;
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immediateType = MIPS_IMMEDIATE5;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 'i': // 16 bit immediate
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if (!MipsCheckImmediate(Line,cpu,immediate.originalValue,RetLen)) return false;
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immediateType = MIPS_IMMEDIATE16;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 'b': // 20 bit immediate
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if (!MipsCheckImmediate(Line,cpu,immediate.originalValue,RetLen)) return false;
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immediateType = MIPS_IMMEDIATE20;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 'I': // 32 bit immediate
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if (!MipsCheckImmediate(Line,cpu,immediate.originalValue,RetLen)) return false;
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immediateType = MIPS_IMMEDIATE26;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 'r': // forced register
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if (MipsGetRegister(Line,RetLen) != *(SourceEncoding+1)) return false;
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Line += RetLen;
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SourceEncoding += 2;
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break;
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case '/': // forced letter
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SourceEncoding++; // fallthrough
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default: // everything else
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if (*SourceEncoding++ != *Line++) return false;
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break;
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}
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}
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}
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while (*Line == ' ' || *Line == '\t') Line++;
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if (*Line != 0) return false; // there's something else, bad
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// opcode is ok - now set all flags
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Opcode = SourceOpcode;
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immediate.value = immediate.originalValue;
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setOmittedRegisters();
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return true;
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}
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void CMipsInstruction::setOmittedRegisters()
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{
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// copy over omitted registers
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if (Opcode.flags & MO_RSD)
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registers.grd = registers.grs;
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if (Opcode.flags & MO_RST)
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registers.grt = registers.grs;
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if (Opcode.flags & MO_RDT)
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registers.grt = registers.grd;
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if (Opcode.flags & MO_FRSD)
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registers.frd = registers.frs;
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}
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int getImmediateBits(MipsImmediateType type)
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{
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switch (type)
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{
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case MIPS_IMMEDIATE5:
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return 5;
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case MIPS_IMMEDIATE16:
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return 16;
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case MIPS_IMMEDIATE20:
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return 20;
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case MIPS_IMMEDIATE26:
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return 26;
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default:
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return 0;
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}
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}
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bool CMipsInstruction::Validate()
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{
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if (RamPos % 4)
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{
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Logger::queueError(Logger::Error,L"opcode not aligned to word boundary");
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return false;
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}
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// check immediates
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if (immediateType != MIPS_NOIMMEDIATE)
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{
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immediate.originalValue = immediate.value;
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if (Opcode.flags & MO_IMMALIGNED) // immediate must be aligned
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{
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if (immediate.value % 4)
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{
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Logger::queueError(Logger::Error,L"Immediate must be word aligned",immediate.value);
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return false;
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}
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}
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if (Opcode.flags & MO_IPCA) // absolute value >> 2)
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{
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immediate.value = (immediate.value >> 2) & 0x3FFFFFF;
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} else if (Opcode.flags & MO_IPCR) // relative 16 bit value
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{
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int num = (immediate.value-RamPos-4);
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if (num > 0x20000 || num < (-0x20000))
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{
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Logger::queueError(Logger::Error,L"Branch target %08X out of range",immediate.value);
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return false;
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}
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immediate.value = num >> 2;
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}
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int immediateBits = getImmediateBits(immediateType);
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unsigned int mask = (0xFFFFFFFF << (32-immediateBits)) >> (32-immediateBits);
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int digits = (immediateBits+3) / 4;
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if ((unsigned int)std::abs(immediate.value) > mask)
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{
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Logger::queueError(Logger::Error,L"Immediate value %0*X out of range",digits,immediate.value);
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return false;
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}
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immediate.value &= mask;
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}
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return true;
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}
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void CMipsInstruction::encodeNormal()
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{
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encoding = Opcode.destencoding;
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if (registers.grs.num != -1) encoding |= MIPS_RS(registers.grs.num); // source reg
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if (registers.grt.num != -1) encoding |= MIPS_RT(registers.grt.num); // target reg
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if (registers.grd.num != -1) encoding |= MIPS_RD(registers.grd.num); // dest reg
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if (registers.frt.num != -1) encoding |= MIPS_FT(registers.frt.num); // float target reg
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if (registers.frs.num != -1) encoding |= MIPS_FS(registers.frs.num); // float source reg
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if (registers.frd.num != -1) encoding |= MIPS_FD(registers.frd.num); // float dest reg
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if (registers.ps2vrt.num != -1) encoding |= (registers.ps2vrt.num << 16); // ps2 vector target reg
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if (registers.ps2vrs.num != -1) encoding |= (registers.ps2vrs.num << 21); // ps2 vector source reg
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if (registers.ps2vrd.num != -1) encoding |= (registers.ps2vrd.num << 6); // ps2 vector dest reg
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switch (immediateType)
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{
|
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case MIPS_NOIMMEDIATE:
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break;
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|
case MIPS_IMMEDIATE5:
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|
case MIPS_IMMEDIATE20:
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encoding |= immediate.value << 6;
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break;
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case MIPS_IMMEDIATE16:
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case MIPS_IMMEDIATE26:
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encoding |= immediate.value;
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break;
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}
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}
|
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void CMipsInstruction::Encode()
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{
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encodeNormal();
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}
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