mirror of https://github.com/PCSX2/pcsx2.git
110 lines
2.6 KiB
C++
110 lines
2.6 KiB
C++
// SPDX-FileCopyrightText: 2002-2023 PCSX2 Dev Team
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// SPDX-License-Identifier: LGPL-3.0+
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#include "Common.h"
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#include "SIO/Sio2.h"
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#include "SIO/Sio0.h"
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#include "CDVD/CDVD.h"
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#include "CDVD/Ps1CD.h"
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#include "IopCounters.h"
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#include "IopDma.h"
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#include "IopHw.h"
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#include "Mdec.h"
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#include "R3000A.h"
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#include "x86/iR5900.h"
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// NOTE: Any modifications to read/write fns should also go into their const counterparts
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// found in iPsxHw.cpp.
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void psxHwReset() {
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/* if (Config.Sio) psxHu32(0x1070) |= 0x80;
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if (Config.SpuIrq) psxHu32(0x1070) |= 0x200;*/
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memset(iopHw, 0, 0x10000);
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mdecInit(); //initialize mdec decoder
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cdrReset();
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cdvdReset();
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psxRcntInit();
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}
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__fi u8 psxHw4Read8(u32 add)
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{
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u16 mem = add & 0xFF;
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u8 ret = cdvdRead(mem);
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PSXHW_LOG("HwRead8 from Cdvd [segment 0x1f40], addr 0x%02x = 0x%02x", mem, ret);
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return ret;
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}
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__fi void psxHw4Write8(u32 add, u8 value)
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{
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u8 mem = (u8)add; // only lower 8 bits are relevant (cdvd regs mirror across the page)
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cdvdWrite(mem, value);
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PSXHW_LOG("HwWrite8 to Cdvd [segment 0x1f40], addr 0x%02x = 0x%02x", mem, value);
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}
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void psxDmaInterrupt(int n)
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{
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if(n == 33) {
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for (int i = 0; i < 6; i++) {
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if (HW_DMA_ICR & (1 << (16 + i))) {
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if (HW_DMA_ICR & (1 << (24 + i))) {
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if (HW_DMA_ICR & (1 << 23)) {
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HW_DMA_ICR |= 0x80000000; //Set master IRQ condition met
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}
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psxRegs.CP0.n.Cause &= ~0x7C;
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iopIntcIrq(3);
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break;
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}
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}
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}
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} else if (HW_DMA_ICR & (1 << (16 + n)))
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{
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HW_DMA_ICR |= (1 << (24 + n));
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if (HW_DMA_ICR & (1 << 23)) {
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HW_DMA_ICR |= 0x80000000; //Set master IRQ condition met
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}
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iopIntcIrq(3);
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}
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}
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void psxDmaInterrupt2(int n)
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{
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// SIF0 and SIF1 DMA IRQ's cannot be supressed due to a mask flag for "tag" interrupts being available which cannot be disabled.
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// The hardware can't disinguish between the DMA End and Tag Interrupt flags on these channels so interrupts always fire
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bool fire_interrupt = n == 2 || n == 3;
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if (n == 33) {
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for (int i = 0; i < 6; i++) {
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if (HW_DMA_ICR2 & (1 << (24 + i))) {
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if (HW_DMA_ICR2 & (1 << (16 + i)) || i == 2 || i == 3) {
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fire_interrupt = true;
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break;
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}
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}
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}
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}
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else if (HW_DMA_ICR2 & (1 << (16 + n)))
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{
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/*
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if (HW_DMA_ICR2 & (1 << (24 + n))) {
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Console.WriteLn("*PCSX2*: HW_DMA_ICR2 n=%d already set", n);
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}
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if (psxHu32(0x1070) & 8) {
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Console.WriteLn("*PCSX2*: psxHu32(0x1070) 8 already set (n=%d)", n);
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}*/
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fire_interrupt = true;
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}
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if (fire_interrupt)
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{
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if(n != 33)
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HW_DMA_ICR2 |= (1 << (24 + n));
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if (HW_DMA_ICR2 & (1 << 23)) {
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HW_DMA_ICR2 |= 0x80000000; //Set master IRQ condition met
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}
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iopIntcIrq(3);
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}
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}
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