mirror of https://github.com/PCSX2/pcsx2.git
118 lines
3.8 KiB
C
118 lines
3.8 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __PSXHW_H__
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#define __PSXHW_H__
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#define HW_DMA0_MADR (psxHu32(0x1080)) // MDEC in DMA
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#define HW_DMA0_BCR (psxHu32(0x1084))
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#define HW_DMA0_CHCR (psxHu32(0x1088))
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#define HW_DMA1_MADR (psxHu32(0x1090)) // MDEC out DMA
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#define HW_DMA1_BCR (psxHu32(0x1094))
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#define HW_DMA1_CHCR (psxHu32(0x1098))
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#define HW_DMA2_MADR (psxHu32(0x10a0)) // GPU DMA
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#define HW_DMA2_BCR (psxHu32(0x10a4))
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#define HW_DMA2_CHCR (psxHu32(0x10a8))
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#define HW_DMA2_TADR (psxHu32(0x10ac))
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#define HW_DMA3_MADR (psxHu32(0x10b0)) // CDROM DMA
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#define HW_DMA3_BCR (psxHu32(0x10b4))
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#define HW_DMA3_BCR_L16 (psxHu16(0x10b4))
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#define HW_DMA3_BCR_H16 (psxHu16(0x10b6))
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#define HW_DMA3_CHCR (psxHu32(0x10b8))
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#define HW_DMA4_MADR (psxHu32(0x10c0)) // SPU DMA
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#define HW_DMA4_BCR (psxHu32(0x10c4))
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#define HW_DMA4_CHCR (psxHu32(0x10c8))
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#define HW_DMA4_TADR (psxHu32(0x10cc))
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#define HW_DMA6_MADR (psxHu32(0x10e0)) // GPU DMA (OT)
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#define HW_DMA6_BCR (psxHu32(0x10e4))
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#define HW_DMA6_CHCR (psxHu32(0x10e8))
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#define HW_DMA7_MADR (psxHu32(0x1500)) // SPU2 DMA
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#define HW_DMA7_BCR (psxHu32(0x1504))
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#define HW_DMA7_CHCR (psxHu32(0x1508))
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#define HW_DMA8_MADR (psxHu32(0x1510)) // DEV9 DMA
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#define HW_DMA8_BCR (psxHu32(0x1514))
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#define HW_DMA8_CHCR (psxHu32(0x1518))
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#define HW_DMA9_MADR (psxHu32(0x1520)) // SIF0 DMA
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#define HW_DMA9_BCR (psxHu32(0x1524))
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#define HW_DMA9_CHCR (psxHu32(0x1528))
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#define HW_DMA9_TADR (psxHu32(0x152c))
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#define HW_DMA10_MADR (psxHu32(0x1530)) // SIF1 DMA
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#define HW_DMA10_BCR (psxHu32(0x1534))
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#define HW_DMA10_CHCR (psxHu32(0x1538))
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#define HW_DMA11_MADR (psxHu32(0x1540)) // SIO2 in
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#define HW_DMA11_BCR (psxHu32(0x1544))
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#define HW_DMA11_CHCR (psxHu32(0x1548))
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#define HW_DMA12_MADR (psxHu32(0x1550)) // SIO2 out
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#define HW_DMA12_BCR (psxHu32(0x1554))
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#define HW_DMA12_CHCR (psxHu32(0x1558))
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#define HW_DMA_PCR (psxHu32(0x10f0))
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#define HW_DMA_ICR (psxHu32(0x10f4))
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#define HW_DMA_PCR2 (psxHu32(0x1570))
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#define HW_DMA_ICR2 (psxHu32(0x1574))
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#define PSX_INT(n, ecycle) \
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psxRegs.interrupt|= 1 << n; \
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g_psxNextBranchCycle = min(g_psxNextBranchCycle, psxRegs.cycle+ecycle); \
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psxRegs.sCycle[n] = psxRegs.cycle; \
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psxRegs.eCycle[n] = ecycle;
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void psxHwReset();
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u8 psxHwRead8 (u32 add);
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int psxHwConstRead8(u32 x86reg, u32 add, u32 sign);
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u16 psxHwRead16(u32 add);
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int psxHwConstRead16(u32 x86reg, u32 add, u32 sign);
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u32 psxHwRead32(u32 add);
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int psxHwConstRead32(u32 x86reg, u32 add);
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void psxHwWrite8 (u32 add, u8 value);
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void psxHwConstWrite8(u32 add, int mmreg);
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void psxHwWrite16(u32 add, u16 value);
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void psxHwConstWrite16(u32 add, int mmreg);
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void psxHwWrite32(u32 add, u32 value);
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void psxHwConstWrite32(u32 add, int mmreg);
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u8 psxHw4Read8 (u32 add);
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int psxHw4ConstRead8 (u32 x86reg, u32 add, u32 sign);
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void psxHw4Write8(u32 add, u8 value);
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void psxHw4ConstWrite8(u32 add, int mmreg);
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int psxHwFreeze(gzFile f, int Mode);
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void psxDmaInterrupt(int n);
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void psxDmaInterrupt2(int n);
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#endif /* __PSXHW_H__ */
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