mirror of https://github.com/PCSX2/pcsx2.git
494 lines
13 KiB
C
494 lines
13 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <string.h>
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#include <time.h>
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#include <math.h>
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#include "Common.h"
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#include "PsxCommon.h"
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int gates = 0;
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u8 eehblankgate = 0;
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int cnts = 5;
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extern u8 psxhblankgate;
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int hblankend = 1;
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Counter counters[6];
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u32 nextCounter, nextsCounter;
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void rcntUpdTarget(int index) {
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counters[index].sCycleT = cpuRegs.cycle;
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counters[index].CycleT = (counters[index].target - rcntRcount(index)) * counters[index].rate;
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}
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void rcntUpd(int index) {
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counters[index].sCycle = cpuRegs.cycle;
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counters[index].Cycle = (0xffff - (rcntRcount(index)&0xffff)) * counters[index].rate;
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rcntUpdTarget(index);
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}
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void rcntReset(int index) {
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counters[index].count = 0;
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counters[index].mode&= ~0x00400C00;
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rcntUpd(index);
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}
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void rcntSet() {
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u32 c;
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int i;
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nextCounter = 0xffff;
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nextsCounter = cpuRegs.cycle;
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for (i = 0; i < 4; i++) {
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if ((counters[i].mode & 0x380) < 0x80) continue; // Stopped
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if (counters[i].mode & 0x200){
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c = (0xffff - rcntCycle(i)) * counters[i].rate;
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if (c < nextCounter) {
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nextCounter = c;
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}
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}
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if ((counters[i].mode & 0x500) == 0x100){
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c = (counters[i].target - rcntCycle(i)) * counters[i].rate;
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if (c < nextCounter) {
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nextCounter = c;
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}
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}
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}
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//Calculate HBlank
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c = counters[4].CycleT - (cpuRegs.cycle - counters[4].sCycleT);
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if (c < nextCounter) {
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nextCounter = c;
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}
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c = counters[5].CycleT - (cpuRegs.cycle - counters[5].sCycleT);
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if (c < nextCounter) {
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nextCounter = c;
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}
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}
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void rcntInit() {
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int i;
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memset(counters, 0, sizeof(counters));
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for (i=0; i<4; i++) {
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counters[i].rate = 2;
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counters[i].target = 0xffff;
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}
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counters[0].interrupt = 9;
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counters[1].interrupt = 10;
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counters[2].interrupt = 11;
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counters[3].interrupt = 12;
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counters[4].mode = 0x3c0; // The VSync counter mode
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//counters[4].count = 0;
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counters[5].mode = 0x3c0;
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UpdateVSyncRate();
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counters[4].sCycleT = cpuRegs.cycle;
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counters[4].sCycle = cpuRegs.cycle;
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counters[4].CycleT = counters[4].rate;
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counters[4].Cycle = counters[4].rate;
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counters[5].sCycleT = cpuRegs.cycle;
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counters[5].sCycle = cpuRegs.cycle;
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counters[5].CycleT = counters[5].rate;
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counters[5].Cycle = counters[5].rate;
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for (i=0; i<4; i++) rcntUpd(i);
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rcntSet();
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}
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void UpdateVSyncRate() {
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if (Config.PsxType & 1) {
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counters[4].rate = PS2HBLANK_PAL;
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if(Config.PsxType & 2)counters[5].rate = PS2VBLANK_PAL_INT;
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else counters[5].rate = PS2VBLANK_PAL;
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} else {
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counters[4].rate = PS2HBLANK_NTSC;
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if(Config.PsxType & 2)counters[5].rate = PS2VBLANK_NTSC_INT;
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else counters[5].rate = PS2VBLANK_NTSC;
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}
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}
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#define NOSTATS
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// debug code, used for stats
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int g_nCounters[4];
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extern u32 s_lastvsync[2];
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LARGE_INTEGER lfreq;
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static int iFrame = 0;
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void FrameLimiter()
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{
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static u32 dwStartTime = 0, dwEndTime = 0;
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// do over 4 frames instead of 1
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if( (iFrame&3) == 0 ) {
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u32 frames = (Config.PsxType&1) ? (4000 / 50 -1) : (4000 / 60 - 1);
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dwEndTime = timeGetTime();
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if( dwEndTime < dwStartTime + frames ) {
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Sleep(frames-(dwEndTime-dwStartTime));
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}
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dwStartTime = timeGetTime();
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}
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}
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extern u32 CSRw;
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extern u32 SuperVUGetRecTimes(int clear);
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extern u32 vu0time;
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#include "VU.h"
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void VSync() {
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//QueryPerformanceFrequency(&lfreq);
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if (counters[5].mode & 0x10000) { // VSync End (22 hsyncs)
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// swap the vsync field
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u32 newfield = (*(u32*)(PS2MEM_GS+0x1000)&0x2000) ? 0 : 0x2000;
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*(u32*)(PS2MEM_GS+0x1000) = (*(u32*)(PS2MEM_GS+0x1000) & ~(1<<13)) | newfield;
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iFrame++;
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// wait until GS stops
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if( CHECK_MULTIGS ) {
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GSRingBufVSync(newfield);
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}
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else {
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#ifdef GSCAPTURE
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extern u32 g_gstransnum;
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g_gstransnum = 0;
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#endif
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GSvsync(newfield);
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}
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//SysPrintf("c: %x, %x\n", cpuRegs.cycle, *(u32*)&VU1.Micro[16]);
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//if( (iFrame%20) == 0 ) SysPrintf("svu time: %d\n", SuperVUGetRecTimes(1));
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// if( (iFrame%10) == 0 ) {
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// SysPrintf("vu0 time: %d\n", vu0time);
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// vu0time = 0;
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// }
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#ifdef PCSX2_DEVBUILD
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if( g_TestRun.enabled && g_TestRun.frame > 0 ) {
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if( iFrame > g_TestRun.frame ) {
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// take a snapshot
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if( g_TestRun.pimagename != NULL && GSmakeSnapshot2 != NULL ) {
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if( g_TestRun.snapdone ) {
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g_TestRun.curimage++;
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g_TestRun.snapdone = 0;
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g_TestRun.frame += 20;
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if( g_TestRun.curimage >= g_TestRun.numimages ) {
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// exit
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SysClose();
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exit(0);
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}
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}
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else {
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// query for the image
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GSmakeSnapshot2(g_TestRun.pimagename, &g_TestRun.snapdone, g_TestRun.jpgcapture);
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}
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}
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else {
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// exit
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SysClose();
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exit(0);
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}
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}
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}
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#endif
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if( CHECK_FRAMELIMIT ) FrameLimiter();
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counters[5].mode&= ~0x10000;
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//UpdateVSyncRate();
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GSCSRr |= 8; // signal
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if (CSRw & 0x8){
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CSRw &= ~8;
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if (!(GSIMR&0x800) )
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gsIrq();
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}
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hwIntcIrq(3);
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psxVSyncEnd();
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#ifndef NOSTATS
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statsVSync();
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#endif
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if(gates)rcntEndGate(0x8);
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SysUpdate();
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} else { // VSync Start (240 hsyncs)
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//UpdateVSyncRateEnd();
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//SysPrintf("ctrs: %d %d %d %d\n", g_nCounters[0], g_nCounters[1], g_nCounters[2], g_nCounters[3]);
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//SysPrintf("vif: %d\n", (((LARGE_INTEGER*)g_nCounters)->QuadPart * 1000000) / lfreq.QuadPart);
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//memset(g_nCounters, 0, 16);
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counters[5].mode|= 0x10000;
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//GSCSRr|= 0x8;
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hwIntcIrq(2);
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psxVSyncStart();
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if(Config.Patch) applypatch(1);
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if(gates)rcntStartGate(0x8);
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// __Log("%u %u 0\n", cpuRegs.cycle-s_lastvsync[1], timeGetTime()-s_lastvsync[0]);
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// s_lastvsync[0] = timeGetTime();
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// s_lastvsync[1] = cpuRegs.cycle;
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}
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}
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void rcntUpdate() {
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int i;
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for (i=0; i<=3; i++) {
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if ((counters[i].mode & 0x380) < 0x80) continue; // Stopped
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if (rcntCycle(i) >= counters[i].target) { // Target interrupt
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if ((counters[i].mode & 0x500) == 0x100) { // 0x400 == 0 so target interrupt hasnt happened
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counters[i].mode|= 0x0400; // Target flag
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//counters[i].mode&= ~0x800;
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hwIntcIrq(counters[i].interrupt);
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// SysPrintf("counter[%d] target interrupt (%x)\n", i, cpuRegs.cycle);
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}
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if (counters[i].mode & 0x40) { // Reset on target
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counters[i].count = 0;
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rcntUpd(i);
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}
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}
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if (rcntCycle(i) >= 0xffff) {
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if (counters[i].mode & 0x0200) { // Overflow interrupt
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counters[i].mode|= 0x0800; // Overflow flag
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hwIntcIrq(counters[i].interrupt);
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// SysPrintf("counter[%d] overflow interrupt (%x)\n", i, cpuRegs.cycle);
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}
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counters[i].count = 0;
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rcntUpd(i);
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}
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}
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if ((cpuRegs.cycle - counters[4].sCycleT) >= counters[4].CycleT / 2 && hblankend == 0){
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GSCSRr |= 4; // signal
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if (CSRw & 0x4){
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CSRw &= ~4;
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if (!(GSIMR&0x400) )
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gsIrq();
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}
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if(eehblankgate)rcntEndGate(0);
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if(psxhblankgate)psxCheckEndGate(0);
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hblankend = 1;
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}
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if ((cpuRegs.cycle - counters[4].sCycleT) >= counters[4].CycleT) {
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counters[4].sCycleT = cpuRegs.cycle;
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counters[4].sCycle = cpuRegs.cycle;
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counters[4].CycleT = counters[4].rate;
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counters[4].Cycle = counters[4].rate;
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if(gates)rcntStartGate(0);
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psxCheckStartGate(0);
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hblankend = 0;
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}
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if ((cpuRegs.cycle - counters[5].sCycleT) >= counters[5].CycleT / 2 && (counters[5].mode & 0x10000)) VSync();
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if ((cpuRegs.cycle - counters[5].sCycleT) >= counters[5].CycleT) {
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counters[5].sCycleT = cpuRegs.cycle;
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counters[5].sCycle = cpuRegs.cycle;
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counters[5].CycleT = counters[5].rate;
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counters[5].Cycle = counters[5].rate;
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VSync();
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}
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rcntSet();
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}
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void rcntWcount(int index, u32 value) {
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//SysPrintf ("writeCcount[%d] = %x\n", index, value);
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("EE count write %d count %x eecycle %x\n", index, counters[index].count, cpuRegs.eCycle);
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#endif
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//counters[index].mode &= ~0x00400C00;
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counters[index].count = value;
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rcntUpd(index);
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rcntSet();
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}
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void rcntWmode(int index, u32 value) {
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// SysPrintf ("writeCmode[%ld] = %lx\n", index, value);
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("EE counter set %d mode %x\n", index, counters[index].mode);
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#endif
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if (value & 0xc00) {
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counters[index].mode &= ~(value & 0xc00);
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}
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/*if ((counters[index].mode & 0x37F) == (value & 0x37f)){ //Stop Counting
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if((counters[index].mode & 0x80) != (value & 0x80)){
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SysPrintf("EE Counter %x %s\n", index, (counters[index].mode & 0x80) ? "stopped" : "started");
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if(counters[index].mode & 0x80) counters[index].count = rcntRcount(index);
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counters[index].mode ^= 0x80;
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rcntUpd(index);
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}
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rcntSet();
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return;
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}*/
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if(!(value & 0x80)){
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counters[index].count = rcntRcount(index);
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rcntUpd(index);
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}
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counters[index].mode = (value & 0x3ff) | (counters[index].mode & 0xc00);
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switch (value & 0x3) { //Clock rate divisers *2, they use BUSCLK speed not PS2CLK
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case 0: counters[index].rate = 2; break;
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case 1: counters[index].rate = 32; break;
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case 2: counters[index].rate = 512; break;
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case 3: counters[index].rate = PS2HBLANK; break;
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}
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if((counters[index].mode & 0xF) == 0x7) {
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gates &= ~(1<<index);
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}else if(counters[index].mode & 0x4){
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gates |= 1<<index;
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SysPrintf("Gate Being set on %x, mode %x\n", index, counters[index].mode & 0xf);
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}
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else gates &= ~(1<<index);
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rcntSet();
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}
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void rcntStartGate(int mode){
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int i;
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for(i=0; i <=3; i++){ //Gates for counters
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if(!(gates & (1<<i))) continue;
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if ((counters[i].mode & 0x8) != mode) continue;
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//SysPrintf("Gates init %x\n", i);
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if(mode == 0) eehblankgate |= 1;
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switch((counters[i].mode & 0x30) >> 4){
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case 0x0: //Count When Signal is low (off)
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counters[i].count = rcntRcount(i);
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//rcntUpd(i);
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counters[i].mode &= ~0x80;
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break;
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case 0x1: //Reset and start counting on Vsync start
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counters[i].mode |= 0x80;
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rcntReset(i);
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break;
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case 0x2: //Reset and start counting on Vsync end
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//Do Nothing
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break;
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case 0x3: //Reset and start counting on Vsync start and end
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counters[i].mode |= 0x80;
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rcntReset(i);
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break;
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default:
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SysPrintf("EE Start Counter %x Gate error\n", i);
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break;
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}
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}
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}
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void rcntEndGate(int mode){
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int i;
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for(i=0; i <=3; i++){ //Gates for counters
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if(!(gates & (1<<i))) continue;
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if ((counters[i].mode & 0x8) != mode) continue;
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if(mode == 0) eehblankgate &= ~1;
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//SysPrintf("Gates end init %x\n", i);
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switch((counters[i].mode & 0x30) >> 4){
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case 0x0: //Count When Signal is low (off)
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rcntUpd(i);
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counters[i].mode |= 0x80;
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break;
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case 0x1: //Reset and start counting on Vsync start
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//Do Nothing
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break;
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case 0x2: //Reset and start counting on Vsync end
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rcntReset(i);
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counters[i].mode |= 0x80;
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break;
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case 0x3: //Reset and start counting on Vsync start and end
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rcntReset(i);
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counters[i].mode |= 0x80;
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break;
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default:
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SysPrintf("EE Start Counter %x Gate error\n", i);
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break;
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}
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}
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}
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void rcntWtarget(int index, u32 value) {
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//SysPrintf ("writeCtarget[%ld] = %lx\n", index, value);
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("EE target write %d target %x eecycle %x\n", index, counters[index].target, cpuRegs.eCycle);
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#endif
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counters[index].target = value;
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//counters[index].mode &= ~0x00400400;
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counters[index].CycleT = (counters[index].target - rcntRcount(index)) * counters[index].rate;
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//rcntUpdTarget(index);
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rcntSet();
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}
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void rcntWhold(int index, u32 value) {
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//SysPrintf ("writeChold[%ld] = %lx\n", index, value);
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counters[index].hold = value;
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//rcntUpd(index);
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//rcntSet();
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}
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u16 rcntRcount(int index) {
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u16 ret;
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if ((counters[index].mode & 0x80)) {
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ret = counters[index].count + ((cpuRegs.cycle - counters[index].sCycle) / counters[index].rate);
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}else{
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ret = counters[index].count;
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}
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// SysPrintf("rcntRcount[%d] %x\n", index, ret);
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return (u16)ret;
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}
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u32 rcntCycle(int index) {
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if ((counters[index].mode & 0x80)) {
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return counters[index].count + ((cpuRegs.cycle - counters[index].sCycle) / counters[index].rate);
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}else{
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return counters[index].count;
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}
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}
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int rcntFreeze(gzFile f, int Mode) {
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gzfreezel(counters);
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gzfreeze(&nextCounter, sizeof(nextCounter));
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gzfreeze(&nextsCounter, sizeof(nextsCounter));
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return 0;
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}
|
|
|