mirror of https://github.com/PCSX2/pcsx2.git
319 lines
7.8 KiB
C
319 lines
7.8 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdio.h>
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#include "Common.h"
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#include "R5900.h"
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#include "InterTables.h"
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extern BOOL bExecBIOS;
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void COP0() {
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Int_COP0PrintTable[_Rs_]();
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}
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void COP0_BC0() {
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#ifdef COP0_LOG
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COP0_LOG("%s\n", disR5900F(cpuRegs.code, cpuRegs.pc));
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#endif
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Int_COP0BC0PrintTable[(cpuRegs.code >> 16) & 0x03]();
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}
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void COP0_Func() {
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#ifdef COP0_LOG
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COP0_LOG("%s\n", disR5900F(cpuRegs.code, cpuRegs.pc));
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#endif
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Int_COP0C0PrintTable[_Funct_]();
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}
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void COP0_Unknown() {
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#ifdef CPU_LOG
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CPU_LOG("COP0 Unknown opcode called\n");
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#endif
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}
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void UpdateCP0Status() {
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u32 value = cpuRegs.CP0.n.Status.val;
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if (value & 0x06 ||
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(value & 0x18) == 0) { // Kernel Mode (KSU = 0 | EXL = 1 | ERL = 1)*/
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memSetKernelMode(); // Kernel memory always
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} else { // User Mode
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memSetUserMode();
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}
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if ((cpuRegs.CP0.n.Status.val & 0x10007) == 0x10001)cpuTestHwInts();
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}
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void WriteCP0Status(u32 value) {
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cpuRegs.CP0.n.Status.val = value;
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UpdateCP0Status();
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}
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extern u32 s_iLastCOP0Cycle;
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void MFC0() {
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if (!_Rt_) return;
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#ifdef COP0_LOG
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if (_Rd_ != 9) { COP0_LOG("%s\n", disR5900F(cpuRegs.code, cpuRegs.pc)); }
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#endif
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if( _Rd_ == 9 ) {
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// update
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cpuRegs.CP0.n.Count += cpuRegs.cycle-s_iLastCOP0Cycle;
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s_iLastCOP0Cycle = cpuRegs.cycle;
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}
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cpuRegs.GPR.r[_Rt_].UD[0] = (s64)cpuRegs.CP0.r[_Rd_];
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}
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void MTC0() {
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#ifdef COP0_LOG
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COP0_LOG("%s\n", disR5900F(cpuRegs.code, cpuRegs.pc));
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#endif
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switch (_Rd_) {
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case 12: WriteCP0Status(cpuRegs.GPR.r[_Rt_].UL[0]); break;
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case 9: s_iLastCOP0Cycle = cpuRegs.cycle; cpuRegs.CP0.r[9] = cpuRegs.GPR.r[_Rt_].UL[0]; break;
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default: cpuRegs.CP0.r[_Rd_] = cpuRegs.GPR.r[_Rt_].UL[0]; break;
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}
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}
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int CPCOND0() {
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if(((psHu16(DMAC_STAT) & psHu16(DMAC_PCR)) & 0x3ff) == (psHu16(DMAC_PCR) & 0x3ff)) return 1;
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else return 0;
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}
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//#define CPCOND0 1
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#define BC0(cond) \
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if (CPCOND0() cond) { \
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intDoBranch(_BranchTarget_); \
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}
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void BC0F() {
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BC0(== 0);
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}
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void BC0T() {
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BC0(== 1);
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}
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#define BC0L(cond) \
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if (CPCOND0() cond) { \
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intDoBranch(_BranchTarget_); \
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} else cpuRegs.pc+= 4;
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void BC0FL() {
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BC0L(== 0);
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}
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void BC0TL() {
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BC0L(== 1);
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}
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void TLBR() {
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#ifdef CPU_LOG
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/* CPU_LOG("COP0_TLBR %d:%x,%x,%x,%x\n",
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cpuRegs.CP0.n.Random, cpuRegs.CP0.n.PageMask, cpuRegs.CP0.n.EntryHi,
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cpuRegs.CP0.n.EntryLo0, cpuRegs.CP0.n.EntryLo1);*/
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#endif
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int i = cpuRegs.CP0.n.Index&0x1f;
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// if( !bExecBIOS )
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// __Log("TLBR %d\n", cpuRegs.CP0.n.Index&0x1f);
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SysPrintf("COP0_TLBR\n");
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cpuRegs.CP0.n.PageMask = tlb[i].PageMask;
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cpuRegs.CP0.n.EntryHi = tlb[i].EntryHi&~(tlb[i].PageMask|0x1f00);
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cpuRegs.CP0.n.EntryLo0 = (tlb[i].EntryLo0&~1)|((tlb[i].EntryHi>>12)&1);
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cpuRegs.CP0.n.EntryLo1 =(tlb[i].EntryLo1&~1)|((tlb[i].EntryHi>>12)&1);
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}
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void ClearTLB(int i) {
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u32 mask, addr;
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u32 saddr, eaddr;
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if (tlb[i].EntryLo0 & 0x2) {
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mask = ((~tlb[i].Mask) << 1) & 0xfffff;
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saddr = tlb[i].VPN2 >> 12;
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eaddr = saddr + tlb[i].Mask + 1;
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for (addr=saddr; addr<eaddr; addr++) {
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if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
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memClearPageAddr(addr << 12);
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Cpu->Clear(addr << 12, 1);
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}
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}
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}
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if (tlb[i].EntryLo1 & 0x2) {
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mask = ((~tlb[i].Mask) << 1) & 0xfffff;
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saddr = (tlb[i].VPN2 >> 12) + tlb[i].Mask + 1;
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eaddr = saddr + tlb[i].Mask + 1;
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for (addr=saddr; addr<eaddr; addr++) {
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if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
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memClearPageAddr(addr << 12);
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Cpu->Clear(addr << 12, 1);
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}
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}
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}
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}
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void WriteTLB(int i) {
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u32 mask, addr;
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u32 saddr, eaddr;
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tlb[i].PageMask = cpuRegs.CP0.n.PageMask;
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tlb[i].EntryHi = cpuRegs.CP0.n.EntryHi;
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tlb[i].EntryLo0 = cpuRegs.CP0.n.EntryLo0;
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tlb[i].EntryLo1 = cpuRegs.CP0.n.EntryLo1;
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tlb[i].Mask = (cpuRegs.CP0.n.PageMask >> 13) & 0xfff;
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tlb[i].nMask = (~tlb[i].Mask) & 0xfff;
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tlb[i].VPN2 = ((cpuRegs.CP0.n.EntryHi >> 13) & (~tlb[i].Mask)) << 13;
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tlb[i].ASID = cpuRegs.CP0.n.EntryHi & 0xfff;
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tlb[i].G = cpuRegs.CP0.n.EntryLo0 & cpuRegs.CP0.n.EntryLo1 & 0x1;
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tlb[i].PFN0 = (((cpuRegs.CP0.n.EntryLo0 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12;
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tlb[i].PFN0|= (0x80000000);
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tlb[i].PFN1 = (((cpuRegs.CP0.n.EntryLo1 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12;
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tlb[i].PFN1|= (0x80000000);
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if (tlb[i].VPN2 == 0x70000000) return;
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if (tlb[i].EntryLo0 & 0x2) {
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mask = ((~tlb[i].Mask) << 1) & 0xfffff;
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saddr = tlb[i].VPN2 >> 12;
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eaddr = saddr + tlb[i].Mask + 1;
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for (addr=saddr; addr<eaddr; addr++) {
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if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
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memSetPageAddr(addr << 12, tlb[i].PFN0 + ((addr - saddr) << 12));
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Cpu->Clear(addr << 12, 1);
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}
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}
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}
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if (tlb[i].EntryLo1 & 0x2) {
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mask = ((~tlb[i].Mask) << 1) & 0xfffff;
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saddr = (tlb[i].VPN2 >> 12) + tlb[i].Mask + 1;
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eaddr = saddr + tlb[i].Mask + 1;
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for (addr=saddr; addr<eaddr; addr++) {
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if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
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memSetPageAddr(addr << 12, tlb[i].PFN1 + ((addr - saddr) << 12));
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Cpu->Clear(addr << 12, 1);
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}
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}
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}
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}
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void TLBWI() {
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int j = cpuRegs.CP0.n.Index & 0x3f;
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if (j > 48) return;
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#ifdef CPU_LOG
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/* CPU_LOG("COP0_TLBWI %d:%x,%x,%x,%x\n",
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cpuRegs.CP0.n.Index, cpuRegs.CP0.n.PageMask, cpuRegs.CP0.n.EntryHi,
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cpuRegs.CP0.n.EntryLo0, cpuRegs.CP0.n.EntryLo1);*/
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#endif
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// if( !bExecBIOS )
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// __Log("TLBWI %d\n", j);
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ClearTLB(j);
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WriteTLB(j);
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}
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void TLBWR() {
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int j = cpuRegs.CP0.n.Random & 0x3f;
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if (j > 48) return;
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#ifdef CPU_LOG
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/* CPU_LOG("COP0_TLBWR %d:%x,%x,%x,%x\n",
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cpuRegs.CP0.n.Random, cpuRegs.CP0.n.PageMask, cpuRegs.CP0.n.EntryHi,
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cpuRegs.CP0.n.EntryLo0, cpuRegs.CP0.n.EntryLo1);*/
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#endif
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// if( !bExecBIOS )
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// __Log("TLBWR %d\n", j);
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ClearTLB(j);
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WriteTLB(j);
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}
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void TLBP() {
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int i;
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union {
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struct {
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u32 VPN2:19;
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u32 VPN2X:2;
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u32 G:3;
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u32 ASID:8;
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} s;
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u32 u;
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} EntryHi32;
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if( !bExecBIOS )
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__Log("TLBP %x\n", cpuRegs.CP0.n.EntryHi);
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EntryHi32.u=cpuRegs.CP0.n.EntryHi;
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cpuRegs.CP0.n.Index=0xFFFFFFFF;
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for(i=0;i<48;i++){
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if(tlb[i].VPN2==((~tlb[i].Mask)&(EntryHi32.s.VPN2))
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&&((tlb[i].G&1)||((tlb[i].ASID & 0xff) == EntryHi32.s.ASID))) {
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cpuRegs.CP0.n.Index=i;
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break;
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}
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}
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if(cpuRegs.CP0.n.Index == 0xFFFFFFFF) cpuRegs.CP0.n.Index = 0x80000000;
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}
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void ERET() {
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if (cpuRegs.CP0.n.Status.b.ERL) {
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cpuRegs.pc = cpuRegs.CP0.n.ErrorEPC;
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cpuRegs.CP0.n.Status.b.ERL = 0;
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} else {
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cpuRegs.pc = cpuRegs.CP0.n.EPC;
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cpuRegs.CP0.n.Status.b.EXL = 0;
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}
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UpdateCP0Status();
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intSetBranch();
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}
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void DI() {
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if (cpuRegs.CP0.n.Status.b._EDI || cpuRegs.CP0.n.Status.b.EXL ||
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cpuRegs.CP0.n.Status.b.ERL || (cpuRegs.CP0.n.Status.b.KSU == 0)) {
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cpuRegs.CP0.n.Status.b.EIE = 0;
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UpdateCP0Status();
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}
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}
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void EI() {
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if (cpuRegs.CP0.n.Status.b._EDI || cpuRegs.CP0.n.Status.b.EXL ||
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cpuRegs.CP0.n.Status.b.ERL || (cpuRegs.CP0.n.Status.b.KSU == 0)) {
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cpuRegs.CP0.n.Status.b.EIE = 1;
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UpdateCP0Status();
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}
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}
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