mirror of https://github.com/PCSX2/pcsx2.git
227 lines
10 KiB
C++
227 lines
10 KiB
C++
// SPDX-FileCopyrightText: 2002-2024 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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#pragma once
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namespace x86Emitter
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{
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// --------------------------------------------------------------------------------------
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// xImplSimd_Shuffle
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// --------------------------------------------------------------------------------------
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struct xImplSimd_Shuffle
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{
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inline void _selector_assertion_check(u8 selector) const;
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void PS(const xRegisterSSE& to, const xRegisterSSE& from, u8 selector) const;
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void PS(const xRegisterSSE& to, const xIndirectVoid& from, u8 selector) const;
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void PD(const xRegisterSSE& to, const xRegisterSSE& from, u8 selector) const;
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void PD(const xRegisterSSE& to, const xIndirectVoid& from, u8 selector) const;
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};
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// --------------------------------------------------------------------------------------
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// xImplSimd_PShuffle
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// --------------------------------------------------------------------------------------
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struct xImplSimd_PShuffle
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{
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// Copies doublewords from src and inserts them into dest at dword locations selected
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// with the order operand (8 bit immediate).
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const xImplSimd_DestRegImmSSE D;
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// Copies words from the low quadword of src and inserts them into the low quadword
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// of dest at word locations selected with the order operand (8 bit immediate).
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// The high quadword of src is copied to the high quadword of dest.
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const xImplSimd_DestRegImmSSE LW;
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// Copies words from the high quadword of src and inserts them into the high quadword
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// of dest at word locations selected with the order operand (8 bit immediate).
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// The low quadword of src is copied to the low quadword of dest.
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const xImplSimd_DestRegImmSSE HW;
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// [sSSE-3] Performs in-place shuffles of bytes in dest according to the shuffle
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// control mask in src. If the most significant bit (bit[7]) of each byte of the
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// shuffle control mask is set, then constant zero is written in the result byte.
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// Each byte in the shuffle control mask forms an index to permute the corresponding
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// byte in dest. The value of each index is the least significant 4 bits (128-bit
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// operation) or 3 bits (64-bit operation) of the shuffle control byte.
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//
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const xImplSimd_DestRegEither B;
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// below is my test bed for a new system, free of subclasses. Was supposed to improve intellisense
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// but it doesn't (makes it worse). Will try again in MSVC 2010. --air
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#if 0
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// Copies words from src and inserts them into dest at word locations selected with
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// the order operand (8 bit immediate).
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// Copies doublewords from src and inserts them into dest at dword locations selected
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// with the order operand (8 bit immediate).
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void D( const xRegisterSSE& to, const xRegisterSSE& from, u8 imm ) const { xOpWrite0F( 0x66, 0x70, to, from, imm ); }
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void D( const xRegisterSSE& to, const xIndirectVoid& from, u8 imm ) const { xOpWrite0F( 0x66, 0x70, to, from, imm ); }
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// Copies words from the low quadword of src and inserts them into the low quadword
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// of dest at word locations selected with the order operand (8 bit immediate).
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// The high quadword of src is copied to the high quadword of dest.
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void LW( const xRegisterSSE& to, const xRegisterSSE& from, u8 imm ) const { xOpWrite0F( 0xf2, 0x70, to, from, imm ); }
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void LW( const xRegisterSSE& to, const xIndirectVoid& from, u8 imm ) const { xOpWrite0F( 0xf2, 0x70, to, from, imm ); }
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// Copies words from the high quadword of src and inserts them into the high quadword
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// of dest at word locations selected with the order operand (8 bit immediate).
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// The low quadword of src is copied to the low quadword of dest.
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void HW( const xRegisterSSE& to, const xRegisterSSE& from, u8 imm ) const { xOpWrite0F( 0xf3, 0x70, to, from, imm ); }
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void HW( const xRegisterSSE& to, const xIndirectVoid& from, u8 imm ) const { xOpWrite0F( 0xf3, 0x70, to, from, imm ); }
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// [sSSE-3] Performs in-place shuffles of bytes in dest according to the shuffle
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// control mask in src. If the most significant bit (bit[7]) of each byte of the
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// shuffle control mask is set, then constant zero is written in the result byte.
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// Each byte in the shuffle control mask forms an index to permute the corresponding
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// byte in dest. The value of each index is the least significant 4 bits (128-bit
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// operation) or 3 bits (64-bit operation) of the shuffle control byte.
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//
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void B( const xRegisterSSE& to, const xRegisterSSE& from ) const { OpWriteSSE( 0x66, 0x0038 ); }
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void B( const xRegisterSSE& to, const xIndirectVoid& from ) const { OpWriteSSE( 0x66, 0x0038 ); }
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#endif
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};
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// --------------------------------------------------------------------------------------
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// SimdImpl_PUnpack
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// --------------------------------------------------------------------------------------
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struct SimdImpl_PUnpack
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{
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// Unpack and interleave low-order bytes from src and dest into dest.
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const xImplSimd_DestRegEither LBW;
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// Unpack and interleave low-order words from src and dest into dest.
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const xImplSimd_DestRegEither LWD;
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// Unpack and interleave low-order doublewords from src and dest into dest.
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const xImplSimd_DestRegEither LDQ;
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// Unpack and interleave low-order quadwords from src and dest into dest.
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const xImplSimd_DestRegSSE LQDQ;
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// Unpack and interleave high-order bytes from src and dest into dest.
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const xImplSimd_DestRegEither HBW;
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// Unpack and interleave high-order words from src and dest into dest.
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const xImplSimd_DestRegEither HWD;
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// Unpack and interleave high-order doublewords from src and dest into dest.
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const xImplSimd_DestRegEither HDQ;
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// Unpack and interleave high-order quadwords from src and dest into dest.
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const xImplSimd_DestRegSSE HQDQ;
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};
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// --------------------------------------------------------------------------------------
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// SimdImpl_Pack
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// --------------------------------------------------------------------------------------
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// Pack with Signed or Unsigned Saturation
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//
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struct SimdImpl_Pack
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{
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// Converts packed signed word integers from src and dest into packed signed
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// byte integers in dest, using signed saturation.
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const xImplSimd_DestRegEither SSWB;
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// Converts packed signed dword integers from src and dest into packed signed
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// word integers in dest, using signed saturation.
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const xImplSimd_DestRegEither SSDW;
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// Converts packed unsigned word integers from src and dest into packed unsigned
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// byte integers in dest, using unsigned saturation.
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const xImplSimd_DestRegEither USWB;
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// [SSE-4.1] Converts packed unsigned dword integers from src and dest into packed
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// unsigned word integers in dest, using signed saturation.
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const xImplSimd_DestRegSSE USDW;
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};
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// --------------------------------------------------------------------------------------
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// SimdImpl_Unpack
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// --------------------------------------------------------------------------------------
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struct xImplSimd_Unpack
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{
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// Unpacks the high doubleword [single-precision] values from src and dest into
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// dest, such that the result of dest looks like this:
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// dest[0] <- dest[2]
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// dest[1] <- src[2]
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// dest[2] <- dest[3]
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// dest[3] <- src[3]
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//
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const xImplSimd_DestRegSSE HPS;
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// Unpacks the high quadword [double-precision] values from src and dest into
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// dest, such that the result of dest looks like this:
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// dest.lo <- dest.hi
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// dest.hi <- src.hi
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//
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const xImplSimd_DestRegSSE HPD;
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// Unpacks the low doubleword [single-precision] values from src and dest into
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// dest, such that the result of dest looks like this:
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// dest[3] <- src[1]
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// dest[2] <- dest[1]
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// dest[1] <- src[0]
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// dest[0] <- dest[0]
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//
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const xImplSimd_DestRegSSE LPS;
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// Unpacks the low quadword [double-precision] values from src and dest into
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// dest, effectively moving the low portion of src into the upper portion of dest.
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// The result of dest is loaded as such:
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// dest.hi <- src.lo
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// dest.lo <- dest.lo [remains unchanged!]
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//
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const xImplSimd_DestRegSSE LPD;
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};
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// --------------------------------------------------------------------------------------
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// SimdImpl_PInsert
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// --------------------------------------------------------------------------------------
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// PINSRW/B/D [all but Word form are SSE4.1 only!]
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//
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struct xImplSimd_PInsert
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{
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void B(const xRegisterSSE& to, const xRegister32& from, u8 imm8) const;
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void B(const xRegisterSSE& to, const xIndirect32& from, u8 imm8) const;
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void W(const xRegisterSSE& to, const xRegister32& from, u8 imm8) const;
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void W(const xRegisterSSE& to, const xIndirect32& from, u8 imm8) const;
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void D(const xRegisterSSE& to, const xRegister32& from, u8 imm8) const;
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void D(const xRegisterSSE& to, const xIndirect32& from, u8 imm8) const;
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void Q(const xRegisterSSE& to, const xRegister64& from, u8 imm8) const;
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void Q(const xRegisterSSE& to, const xIndirect64& from, u8 imm8) const;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// PEXTRW/B/D [all but Word form are SSE4.1 only!]
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//
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// Note: Word form's indirect memory form is only available in SSE4.1.
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//
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struct SimdImpl_PExtract
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{
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// [SSE-4.1] Copies the byte element specified by imm8 from src to dest. The upper bits
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// of dest are zero-extended (cleared). This can be used to extract any single packed
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// byte value from src into an x86 32 bit register.
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void B(const xRegister32& to, const xRegisterSSE& from, u8 imm8) const;
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void B(const xIndirect32& dest, const xRegisterSSE& from, u8 imm8) const;
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// Copies the word element specified by imm8 from src to dest. The upper bits
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// of dest are zero-extended (cleared). This can be used to extract any single packed
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// word value from src into an x86 32 bit register.
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//
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// [SSE-4.1] Note: Indirect memory forms of this instruction are an SSE-4.1 extension!
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//
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void W(const xRegister32& to, const xRegisterSSE& from, u8 imm8) const;
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void W(const xIndirect32& dest, const xRegisterSSE& from, u8 imm8) const;
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// [SSE-4.1] Copies the dword element specified by imm8 from src to dest. This can be
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// used to extract any single packed dword value from src into an x86 32 bit register.
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void D(const xRegister32& to, const xRegisterSSE& from, u8 imm8) const;
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void D(const xIndirect32& dest, const xRegisterSSE& from, u8 imm8) const;
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// Insert a qword integer value from r/m64 into the xmm1 at the destination element specified by imm8.
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void Q(const xRegister64& to, const xRegisterSSE& from, u8 imm8) const;
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void Q(const xIndirect64& dest, const xRegisterSSE& from, u8 imm8) const;
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};
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} // namespace x86Emitter
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