mirror of https://github.com/PCSX2/pcsx2.git
305 lines
12 KiB
C++
305 lines
12 KiB
C++
// SPDX-FileCopyrightText: 2002-2024 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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#pragma once
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namespace x86Emitter
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{
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// --------------------------------------------------------------------------------------
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// _SimdShiftHelper
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// --------------------------------------------------------------------------------------
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struct _SimdShiftHelper
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{
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u8 Prefix;
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u16 Opcode;
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u16 OpcodeImm;
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u8 Modcode;
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void operator()(const xRegisterSSE& to, const xRegisterSSE& from) const;
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void operator()(const xRegisterSSE& to, const xIndirectVoid& from) const;
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void operator()(const xRegisterSSE& to, u8 imm8) const;
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};
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// --------------------------------------------------------------------------------------
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// xImplSimd_Shift / xImplSimd_ShiftWithoutQ
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// --------------------------------------------------------------------------------------
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// Used for PSRA, which lacks the Q form.
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//
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struct xImplSimd_ShiftWithoutQ
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{
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const _SimdShiftHelper W;
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const _SimdShiftHelper D;
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};
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// Implements PSRL and PSLL
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//
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struct xImplSimd_Shift
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{
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const _SimdShiftHelper W;
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const _SimdShiftHelper D;
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const _SimdShiftHelper Q;
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void DQ(const xRegisterSSE& to, u8 imm8) const;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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struct xImplSimd_AddSub
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{
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const xImplSimd_DestRegEither B;
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const xImplSimd_DestRegEither W;
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const xImplSimd_DestRegEither D;
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const xImplSimd_DestRegEither Q;
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// Add/Sub packed signed byte [8bit] integers from src into dest, and saturate the results.
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const xImplSimd_DestRegEither SB;
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// Add/Sub packed signed word [16bit] integers from src into dest, and saturate the results.
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const xImplSimd_DestRegEither SW;
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// Add/Sub packed unsigned byte [8bit] integers from src into dest, and saturate the results.
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const xImplSimd_DestRegEither USB;
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// Add/Sub packed unsigned word [16bit] integers from src into dest, and saturate the results.
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const xImplSimd_DestRegEither USW;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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struct xImplSimd_PMul
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{
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const xImplSimd_DestRegEither LW;
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const xImplSimd_DestRegEither HW;
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const xImplSimd_DestRegEither HUW;
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const xImplSimd_DestRegEither UDQ;
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// [SSE-3] PMULHRSW multiplies vertically each signed 16-bit integer from dest with the
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// corresponding signed 16-bit integer of source, producing intermediate signed 32-bit
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// integers. Each intermediate 32-bit integer is truncated to the 18 most significant
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// bits. Rounding is always performed by adding 1 to the least significant bit of the
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// 18-bit intermediate result. The final result is obtained by selecting the 16 bits
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// immediately to the right of the most significant bit of each 18-bit intermediate
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// result and packed to the destination operand.
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//
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// Both operands can be MMX or XMM registers. Source can be register or memory.
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//
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const xImplSimd_DestRegEither HRSW;
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// [SSE-4.1] Multiply the packed dword signed integers in dest with src, and store
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// the low 32 bits of each product in xmm1.
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const xImplSimd_DestRegSSE LD;
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// [SSE-4.1] Multiply the packed signed dword integers in dest with src.
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const xImplSimd_DestRegSSE DQ;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// For instructions that have PS/SS form only (most commonly reciprocal Sqrt functions)
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//
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struct xImplSimd_rSqrt
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{
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const xImplSimd_DestRegSSE PS;
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const xImplSimd_DestRegSSE SS;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// SQRT has PS/SS/SD forms, but not the PD form.
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//
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struct xImplSimd_Sqrt
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{
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const xImplSimd_DestRegSSE PS;
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const xImplSimd_DestRegSSE SS;
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const xImplSimd_DestRegSSE SD;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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struct xImplSimd_AndNot
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{
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const xImplSimd_DestRegSSE PS;
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const xImplSimd_DestRegSSE PD;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// Packed absolute value. [sSSE3 only]
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//
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struct xImplSimd_PAbsolute
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{
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// [sSSE-3] Computes the absolute value of bytes in the src, and stores the result
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// in dest, as UNSIGNED.
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const xImplSimd_DestRegEither B;
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// [sSSE-3] Computes the absolute value of word in the src, and stores the result
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// in dest, as UNSIGNED.
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const xImplSimd_DestRegEither W;
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// [sSSE-3] Computes the absolute value of doublewords in the src, and stores the
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// result in dest, as UNSIGNED.
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const xImplSimd_DestRegEither D;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// Packed Sign [sSSE3 only] - Negate/zero/preserve packed integers in dest depending on the
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// corresponding sign in src.
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//
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struct xImplSimd_PSign
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{
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// [sSSE-3] negates each byte element of dest if the signed integer value of the
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// corresponding data element in src is less than zero. If the signed integer value
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// of a data element in src is positive, the corresponding data element in dest is
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// unchanged. If a data element in src is zero, the corresponding data element in
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// dest is set to zero.
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const xImplSimd_DestRegEither B;
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// [sSSE-3] negates each word element of dest if the signed integer value of the
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// corresponding data element in src is less than zero. If the signed integer value
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// of a data element in src is positive, the corresponding data element in dest is
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// unchanged. If a data element in src is zero, the corresponding data element in
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// dest is set to zero.
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const xImplSimd_DestRegEither W;
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// [sSSE-3] negates each doubleword element of dest if the signed integer value
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// of the corresponding data element in src is less than zero. If the signed integer
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// value of a data element in src is positive, the corresponding data element in dest
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// is unchanged. If a data element in src is zero, the corresponding data element in
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// dest is set to zero.
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const xImplSimd_DestRegEither D;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// Packed Multiply and Add!!
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//
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struct xImplSimd_PMultAdd
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{
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// Multiplies the individual signed words of dest by the corresponding signed words
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// of src, producing temporary signed, doubleword results. The adjacent doubleword
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// results are then summed and stored in the destination operand.
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//
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// DEST[31:0] = ( DEST[15:0] * SRC[15:0]) + (DEST[31:16] * SRC[31:16] );
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// DEST[63:32] = ( DEST[47:32] * SRC[47:32]) + (DEST[63:48] * SRC[63:48] );
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// [.. repeat in the case of XMM src/dest operands ..]
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//
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const xImplSimd_DestRegEither WD;
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// [sSSE-3] multiplies vertically each unsigned byte of dest with the corresponding
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// signed byte of src, producing intermediate signed 16-bit integers. Each adjacent
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// pair of signed words is added and the saturated result is packed to dest.
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// For example, the lowest-order bytes (bits 7-0) in src and dest are multiplied
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// and the intermediate signed word result is added with the corresponding
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// intermediate result from the 2nd lowest-order bytes (bits 15-8) of the operands;
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// the sign-saturated result is stored in the lowest word of dest (bits 15-0).
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// The same operation is performed on the other pairs of adjacent bytes.
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//
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// In Coder Speak:
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// DEST[15-0] = SaturateToSignedWord( SRC[15-8] * DEST[15-8] + SRC[7-0] * DEST[7-0] );
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// DEST[31-16] = SaturateToSignedWord( SRC[31-24] * DEST[31-24] + SRC[23-16] * DEST[23-16] );
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// [.. repeat for each 16 bits up to 64 (mmx) or 128 (xmm) ..]
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//
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const xImplSimd_DestRegEither UBSW;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// Packed Horizontal Add [SSE3 only]
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//
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struct xImplSimd_HorizAdd
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{
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// [SSE-3] Horizontal Add of Packed Data. A three step process:
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// * Adds the single-precision floating-point values in the first and second dwords of
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// dest and stores the result in the first dword of dest.
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// * Adds single-precision floating-point values in the third and fourth dword of dest
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// stores the result in the second dword of dest.
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// * Adds single-precision floating-point values in the first and second dword of *src*
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// and stores the result in the third dword of dest.
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const xImplSimd_DestRegSSE PS;
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// [SSE-3] Horizontal Add of Packed Data. A two step process:
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// * Adds the double-precision floating-point values in the high and low quadwords of
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// dest and stores the result in the low quadword of dest.
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// * Adds the double-precision floating-point values in the high and low quadwords of
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// *src* stores the result in the high quadword of dest.
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const xImplSimd_DestRegSSE PD;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// DotProduct calculation (SSE4.1 only!)
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//
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struct xImplSimd_DotProduct
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{
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// [SSE-4.1] Conditionally multiplies the packed single precision floating-point
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// values in dest with the packed single-precision floats in src depending on a
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// mask extracted from the high 4 bits of the immediate byte. If a condition mask
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// bit in Imm8[7:4] is zero, the corresponding multiplication is replaced by a value
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// of 0.0. The four resulting single-precision values are summed into an inter-
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// mediate result.
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//
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// The intermediate result is conditionally broadcasted to the destination using a
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// broadcast mask specified by bits [3:0] of the immediate byte. If a broadcast
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// mask bit is 1, the intermediate result is copied to the corresponding dword
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// element in dest. If a broadcast mask bit is zero, the corresponding element in
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// the destination is set to zero.
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//
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xImplSimd_DestRegImmSSE PS;
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// [SSE-4.1]
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xImplSimd_DestRegImmSSE PD;
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// Rounds floating point values (packed or single scalar) by an arbitrary rounding mode.
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// (SSE4.1 only!)
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struct xImplSimd_Round
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{
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// [SSE-4.1] Rounds the 4 packed single-precision src values and stores them in dest.
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//
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// Imm8 specifies control fields for the rounding operation:
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// Bit 3 - processor behavior for a precision exception (0: normal, 1: inexact)
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// Bit 2 - If enabled, use MXCSR.RC, else use RC specified in bits 1:0 of this Imm8.
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// Bits 1:0 - Specifies a rounding mode for this instruction only.
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//
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// Rounding Mode Reference:
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// 0 - Nearest, 1 - Negative Infinity, 2 - Positive infinity, 3 - Truncate.
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//
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const xImplSimd_DestRegImmSSE PS;
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// [SSE-4.1] Rounds the 2 packed double-precision src values and stores them in dest.
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//
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// Imm8 specifies control fields for the rounding operation:
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// Bit 3 - processor behavior for a precision exception (0: normal, 1: inexact)
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// Bit 2 - If enabled, use MXCSR.RC, else use RC specified in bits 1:0 of this Imm8.
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// Bits 1:0 - Specifies a rounding mode for this instruction only.
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//
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// Rounding Mode Reference:
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// 0 - Nearest, 1 - Negative Infinity, 2 - Positive infinity, 3 - Truncate.
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//
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const xImplSimd_DestRegImmSSE PD;
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// [SSE-4.1] Rounds the single-precision src value and stores in dest.
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//
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// Imm8 specifies control fields for the rounding operation:
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// Bit 3 - processor behavior for a precision exception (0: normal, 1: inexact)
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// Bit 2 - If enabled, use MXCSR.RC, else use RC specified in bits 1:0 of this Imm8.
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// Bits 1:0 - Specifies a rounding mode for this instruction only.
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//
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// Rounding Mode Reference:
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// 0 - Nearest, 1 - Negative Infinity, 2 - Positive infinity, 3 - Truncate.
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//
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const xImplSimd_DestRegImmSSE SS;
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// [SSE-4.1] Rounds the double-precision src value and stores in dest.
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//
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// Imm8 specifies control fields for the rounding operation:
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// Bit 3 - processor behavior for a precision exception (0: normal, 1: inexact)
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// Bit 2 - If enabled, use MXCSR.RC, else use RC specified in bits 1:0 of this Imm8.
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// Bits 1:0 - Specifies a rounding mode for this instruction only.
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//
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// Rounding Mode Reference:
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// 0 - Nearest, 1 - Negative Infinity, 2 - Positive infinity, 3 - Truncate.
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//
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const xImplSimd_DestRegImmSSE SD;
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};
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} // End namespace x86Emitter
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