mirror of https://github.com/PCSX2/pcsx2.git
260 lines
9.8 KiB
C++
260 lines
9.8 KiB
C++
// SPDX-FileCopyrightText: 2002-2024 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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/*
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* ix86 core v0.9.1
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*
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* Original Authors (v0.6.2 and prior):
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* linuzappz <linuzappz@pcsx.net>
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* alexey silinov
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* goldfinger
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* zerofrog(@gmail.com)
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*
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* Authors of v0.9.1:
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* Jake.Stine(@gmail.com)
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* cottonvibes(@gmail.com)
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* sudonim(1@gmail.com)
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*/
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#include "common/emitter/internal.h"
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#include "common/emitter/implement/helpers.h"
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namespace x86Emitter
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{
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// =====================================================================================================
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// Group 1 Instructions - ADD, SUB, ADC, etc.
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// =====================================================================================================
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// Note on "[Indirect],Imm" forms : use int as the source operand since it's "reasonably inert" from a
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// compiler perspective. (using uint tends to make the compiler try and fail to match signed immediates
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// with one of the other overloads).
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static void _g1_IndirectImm(G1Type InstType, const xIndirect64orLess& sibdest, int imm)
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{
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if (sibdest.Is8BitOp())
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{
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xOpWrite(sibdest.GetPrefix16(), 0x80, InstType, sibdest, 1);
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xWrite<s8>(imm);
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}
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else
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{
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u8 opcode = is_s8(imm) ? 0x83 : 0x81;
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xOpWrite(sibdest.GetPrefix16(), opcode, InstType, sibdest, is_s8(imm) ? 1 : sibdest.GetImmSize());
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if (is_s8(imm))
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xWrite<s8>(imm);
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else
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sibdest.xWriteImm(imm);
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}
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}
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void _g1_EmitOp(G1Type InstType, const xRegisterInt& to, const xRegisterInt& from)
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{
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pxAssert(to.GetOperandSize() == from.GetOperandSize());
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u8 opcode = (to.Is8BitOp() ? 0 : 1) | (InstType << 3);
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xOpWrite(to.GetPrefix16(), opcode, from, to);
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}
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static void _g1_EmitOp(G1Type InstType, const xIndirectVoid& sibdest, const xRegisterInt& from)
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{
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u8 opcode = (from.Is8BitOp() ? 0 : 1) | (InstType << 3);
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xOpWrite(from.GetPrefix16(), opcode, from, sibdest);
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}
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static void _g1_EmitOp(G1Type InstType, const xRegisterInt& to, const xIndirectVoid& sibsrc)
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{
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u8 opcode = (to.Is8BitOp() ? 2 : 3) | (InstType << 3);
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xOpWrite(to.GetPrefix16(), opcode, to, sibsrc);
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}
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static void _g1_EmitOp(G1Type InstType, const xRegisterInt& to, int imm)
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{
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if (!to.Is8BitOp() && is_s8(imm))
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{
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xOpWrite(to.GetPrefix16(), 0x83, InstType, to);
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xWrite<s8>(imm);
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}
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else
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{
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if (to.IsAccumulator())
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{
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u8 opcode = (to.Is8BitOp() ? 4 : 5) | (InstType << 3);
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xOpAccWrite(to.GetPrefix16(), opcode, InstType, to);
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}
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else
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{
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u8 opcode = to.Is8BitOp() ? 0x80 : 0x81;
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xOpWrite(to.GetPrefix16(), opcode, InstType, to);
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}
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to.xWriteImm(imm);
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}
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}
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#define ImplementGroup1(g1type, insttype) \
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void g1type::operator()(const xRegisterInt& to, const xRegisterInt& from) const { _g1_EmitOp(insttype, to, from); } \
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void g1type::operator()(const xIndirectVoid& to, const xRegisterInt& from) const { _g1_EmitOp(insttype, to, from); } \
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void g1type::operator()(const xRegisterInt& to, const xIndirectVoid& from) const { _g1_EmitOp(insttype, to, from); } \
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void g1type::operator()(const xRegisterInt& to, int imm) const { _g1_EmitOp(insttype, to, imm); } \
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void g1type::operator()(const xIndirect64orLess& sibdest, int imm) const { _g1_IndirectImm(insttype, sibdest, imm); }
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ImplementGroup1(xImpl_Group1, InstType)
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ImplementGroup1(xImpl_G1Logic, InstType)
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ImplementGroup1(xImpl_G1Arith, InstType)
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ImplementGroup1(xImpl_G1Compare, G1Type_CMP)
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const xImpl_G1Logic xAND = {G1Type_AND, {0x00, 0x54}, {0x66, 0x54}};
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const xImpl_G1Logic xOR = {G1Type_OR, {0x00, 0x56}, {0x66, 0x56}};
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const xImpl_G1Logic xXOR = {G1Type_XOR, {0x00, 0x57}, {0x66, 0x57}};
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const xImpl_G1Arith xADD = {G1Type_ADD, {0x00, 0x58}, {0x66, 0x58}, {0xf3, 0x58}, {0xf2, 0x58}};
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const xImpl_G1Arith xSUB = {G1Type_SUB, {0x00, 0x5c}, {0x66, 0x5c}, {0xf3, 0x5c}, {0xf2, 0x5c}};
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const xImpl_G1Compare xCMP = {{0x00, 0xc2}, {0x66, 0xc2}, {0xf3, 0xc2}, {0xf2, 0xc2}};
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const xImpl_Group1 xADC = {G1Type_ADC};
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const xImpl_Group1 xSBB = {G1Type_SBB};
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// =====================================================================================================
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// Group 2 Instructions - SHR, SHL, etc.
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// =====================================================================================================
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void xImpl_Group2::operator()(const xRegisterInt& to, const xRegisterCL& /* from */) const
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{
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xOpWrite(to.GetPrefix16(), to.Is8BitOp() ? 0xd2 : 0xd3, InstType, to);
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}
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void xImpl_Group2::operator()(const xRegisterInt& to, u8 imm) const
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{
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if (imm == 0)
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return;
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if (imm == 1)
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{
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// special encoding of 1's
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xOpWrite(to.GetPrefix16(), to.Is8BitOp() ? 0xd0 : 0xd1, InstType, to);
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}
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else
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{
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xOpWrite(to.GetPrefix16(), to.Is8BitOp() ? 0xc0 : 0xc1, InstType, to);
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xWrite8(imm);
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}
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}
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void xImpl_Group2::operator()(const xIndirect64orLess& sibdest, const xRegisterCL& /* from */) const
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{
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xOpWrite(sibdest.GetPrefix16(), sibdest.Is8BitOp() ? 0xd2 : 0xd3, InstType, sibdest);
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}
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void xImpl_Group2::operator()(const xIndirect64orLess& sibdest, u8 imm) const
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{
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if (imm == 0)
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return;
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if (imm == 1)
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{
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// special encoding of 1's
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xOpWrite(sibdest.GetPrefix16(), sibdest.Is8BitOp() ? 0xd0 : 0xd1, InstType, sibdest);
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}
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else
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{
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xOpWrite(sibdest.GetPrefix16(), sibdest.Is8BitOp() ? 0xc0 : 0xc1, InstType, sibdest, 1);
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xWrite8(imm);
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}
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}
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const xImpl_Group2 xROL = {G2Type_ROL};
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const xImpl_Group2 xROR = {G2Type_ROR};
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const xImpl_Group2 xRCL = {G2Type_RCL};
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const xImpl_Group2 xRCR = {G2Type_RCR};
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const xImpl_Group2 xSHL = {G2Type_SHL};
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const xImpl_Group2 xSHR = {G2Type_SHR};
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const xImpl_Group2 xSAR = {G2Type_SAR};
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// =====================================================================================================
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// Group 3 Instructions - NOT, NEG, MUL, DIV
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// =====================================================================================================
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static void _g3_EmitOp(G3Type InstType, const xRegisterInt& from)
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{
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xOpWrite(from.GetPrefix16(), from.Is8BitOp() ? 0xf6 : 0xf7, InstType, from);
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}
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static void _g3_EmitOp(G3Type InstType, const xIndirect64orLess& from)
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{
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xOpWrite(from.GetPrefix16(), from.Is8BitOp() ? 0xf6 : 0xf7, InstType, from);
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}
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void xImpl_Group3::operator()(const xRegisterInt& from) const { _g3_EmitOp(InstType, from); }
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void xImpl_Group3::operator()(const xIndirect64orLess& from) const { _g3_EmitOp(InstType, from); }
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void xImpl_iDiv::operator()(const xRegisterInt& from) const { _g3_EmitOp(G3Type_iDIV, from); }
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void xImpl_iDiv::operator()(const xIndirect64orLess& from) const { _g3_EmitOp(G3Type_iDIV, from); }
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template <typename SrcType>
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static void _imul_ImmStyle(const xRegisterInt& param1, const SrcType& param2, int imm)
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{
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pxAssert(param1.GetOperandSize() == param2.GetOperandSize());
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xOpWrite0F(param1.GetPrefix16(), is_s8(imm) ? 0x6b : 0x69, param1, param2, is_s8(imm) ? 1 : param1.GetImmSize());
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if (is_s8(imm))
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xWrite8((u8)imm);
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else
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param1.xWriteImm(imm);
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}
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void xImpl_iMul::operator()(const xRegisterInt& from) const { _g3_EmitOp(G3Type_iMUL, from); }
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void xImpl_iMul::operator()(const xIndirect64orLess& from) const { _g3_EmitOp(G3Type_iMUL, from); }
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void xImpl_iMul::operator()(const xRegister32& to, const xRegister32& from) const { xOpWrite0F(0xaf, to, from); }
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void xImpl_iMul::operator()(const xRegister32& to, const xIndirectVoid& src) const { xOpWrite0F(0xaf, to, src); }
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void xImpl_iMul::operator()(const xRegister16& to, const xRegister16& from) const { xOpWrite0F(0x66, 0xaf, to, from); }
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void xImpl_iMul::operator()(const xRegister16& to, const xIndirectVoid& src) const { xOpWrite0F(0x66, 0xaf, to, src); }
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void xImpl_iMul::operator()(const xRegister32& to, const xRegister32& from, s32 imm) const { _imul_ImmStyle(to, from, imm); }
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void xImpl_iMul::operator()(const xRegister32& to, const xIndirectVoid& from, s32 imm) const { _imul_ImmStyle(to, from, imm); }
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void xImpl_iMul::operator()(const xRegister16& to, const xRegister16& from, s16 imm) const { _imul_ImmStyle(to, from, imm); }
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void xImpl_iMul::operator()(const xRegister16& to, const xIndirectVoid& from, s16 imm) const { _imul_ImmStyle(to, from, imm); }
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const xImpl_Group3 xNOT = {G3Type_NOT};
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const xImpl_Group3 xNEG = {G3Type_NEG};
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const xImpl_Group3 xUMUL = {G3Type_MUL};
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const xImpl_Group3 xUDIV = {G3Type_DIV};
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const xImpl_iDiv xDIV = {{0x00, 0x5e}, {0x66, 0x5e}, {0xf3, 0x5e}, {0xf2, 0x5e}};
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const xImpl_iMul xMUL = {{0x00, 0x59}, {0x66, 0x59}, {0xf3, 0x59}, {0xf2, 0x59}};
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// =====================================================================================================
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// Group 8 Instructions
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// =====================================================================================================
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void xImpl_Group8::operator()(const xRegister16or32or64& bitbase, const xRegister16or32or64& bitoffset) const
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{
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pxAssert(bitbase->GetOperandSize() == bitoffset->GetOperandSize());
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xOpWrite0F(bitbase->GetPrefix16(), 0xa3 | (InstType << 3), bitbase, bitoffset);
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}
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void xImpl_Group8::operator()(const xIndirect64& bitbase, u8 bitoffset) const { xOpWrite0F(0xba, InstType, bitbase, bitoffset); }
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void xImpl_Group8::operator()(const xIndirect32& bitbase, u8 bitoffset) const { xOpWrite0F(0xba, InstType, bitbase, bitoffset); }
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void xImpl_Group8::operator()(const xIndirect16& bitbase, u8 bitoffset) const { xOpWrite0F(0x66, 0xba, InstType, bitbase, bitoffset); }
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void xImpl_Group8::operator()(const xRegister16or32or64& bitbase, u8 bitoffset) const
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{
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xOpWrite0F(bitbase->GetPrefix16(), 0xba, InstType, bitbase, bitoffset);
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}
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void xImpl_Group8::operator()(const xIndirectVoid& bitbase, const xRegister16or32or64& bitoffset) const
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{
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xOpWrite0F(bitoffset->GetPrefix16(), 0xa3 | (InstType << 3), bitoffset, bitbase);
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}
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const xImpl_Group8 xBT = {G8Type_BT};
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const xImpl_Group8 xBTR = {G8Type_BTR};
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const xImpl_Group8 xBTS = {G8Type_BTS};
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const xImpl_Group8 xBTC = {G8Type_BTC};
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} // End namespace x86Emitter
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