mirror of https://github.com/PCSX2/pcsx2.git
lol i forgot to add the renamed iCOP0 files :D
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@608 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
70854f099e
commit
febe42c059
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@ -0,0 +1,445 @@
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/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2008 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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// Important Note to Future Developers:
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// None of the COP0 instructions are really critical performance items,
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// so don't waste time converting any more them into recompiled code
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// unless it can make them nicely compact. Calling the C versions will
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// suffice.
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#include "iCOP0.h"
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namespace Interp = R5900::Interpreter::OpcodeImpl::COP0;
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namespace Dynarec {
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namespace R5900 {
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// R5900 branch hepler!
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// Recompiles code for a branch test and/or skip, complete with delay slot
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// handling. Note, for "likely" branches use iDoBranchImm_Likely instead, which
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// handles delay slots differently.
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// Parameters:
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// jmpSkip - This parameter is the result of the appropriate J32 instruction
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// (usually JZ32 or JNZ32).
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static void recDoBranchImm( u32* jmpSkip, bool isLikely = false )
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{
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// All R5900 branches use this format:
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const u32 branchTo = (s32)_Imm_ * 4 + pc;
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// First up is the Branch Taken Path : Save the recompiler's state, compile the
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// DelaySlot, and issue a BranchTest insertion. The state is reloaded below for
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// the "did not branch" path (maintains consts, register allocations, and other optimizations).
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SaveBranchState();
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recompileNextInstruction(1);
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SetBranchImm(branchTo);
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// Jump target when the branch is *not* taken, skips the branchtest code
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// insertion above.
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x86SetJ32(jmpSkip);
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// if it's a likely branch then we'll need to skip the delay slot here, since
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// MIPS cancels the delay slot instruction when branches aren't taken.
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if( !isLikely ) pc -= 4; // instruction rewinde for delay slot ,if non-likely.
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LoadBranchState();
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recompileNextInstruction(1);
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SetBranchImm(pc);
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}
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static void recDoBranchImm_Likely( u32* jmpSkip )
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{
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recDoBranchImm( jmpSkip, true );
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}
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namespace OpcodeImpl {
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namespace COP0 {
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/*********************************************************
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* COP0 opcodes *
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* *
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*********************************************************/
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// emits "setup" code for a COP0 branch test. The instruction immediately following
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// this should be a conditional Jump -- JZ or JNZ normally.
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static void _setupBranchTest()
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{
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_eeFlushAllUnused();
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// COP0 branch conditionals are based on the following equation:
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// (((psHu16(DMAC_STAT) & psHu16(DMAC_PCR)) & 0x3ff) == (psHu16(DMAC_PCR) & 0x3ff))
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// BC0F checks if the statement is false, BC0T checks if the statement is true.
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// note: We only want to compare the 16 bit values of DMAC_STAT and PCR.
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// But using 32-bit loads here is ok (and faster), because we mask off
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// everything except the lower 10 bits away.
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MOV32MtoR( EAX, (uptr)&psHu32(DMAC_STAT) );
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MOV32MtoR( ECX, (uptr)&psHu32(DMAC_PCR) );
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AND32ItoR( EAX, 0x3ff ); // masks off all but lower 10 bits.
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AND32ItoR( ECX, 0x3ff );
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CMP32RtoR( EAX, ECX );
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}
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void recBC0F()
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{
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_setupBranchTest();
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recDoBranchImm(JNZ32(0));
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}
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void recBC0T()
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{
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_setupBranchTest();
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recDoBranchImm(JZ32(0));
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}
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void recBC0FL()
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{
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_setupBranchTest();
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recDoBranchImm_Likely(JNZ32(0));
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}
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void recBC0TL()
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{
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_setupBranchTest();
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recDoBranchImm_Likely(JZ32(0));
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}
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void recTLBR() { recCall( Interp::TLBR, -1 ); }
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void recTLBP() { recCall( Interp::TLBP, -1 ); }
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void recTLBWI() { recCall( Interp::TLBWI, -1 ); }
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void recTLBWR() { recCall( Interp::TLBWR, -1 ); }
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void recERET()
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{
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recBranchCall( Interp::ERET );
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}
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void recEI()
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{
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// must branch after enabling interrupts, so that anything
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// pending gets triggered properly.
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recBranchCall( Interp::EI );
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}
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void recDI()
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{
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// No need to branch after disabling interrupts...
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iFlushCall(0);
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MOV32MtoR( EAX, (uptr)&cpuRegs.cycle );
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MOV32RtoM( (uptr)&g_nextBranchCycle, EAX );
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CALLFunc( (uptr)Interp::DI );
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}
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#ifndef CP0_RECOMPILE
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REC_SYS( MFC0 );
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REC_SYS( MTC0 );
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#else
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void recMFC0( void )
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{
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int mmreg;
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if ( ! _Rt_ ) return;
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if( _Rd_ == 9 ) {
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MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
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MOV32RtoR(EAX,ECX);
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SUB32MtoR(EAX, (uptr)&s_iLastCOP0Cycle);
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ADD32RtoM((uptr)&cpuRegs.CP0.n.Count, EAX);
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MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
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MOV32MtoR( EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ] );
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_deleteEEreg(_Rt_, 0);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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if(EEINST_ISLIVE1(_Rt_)) {
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CDQ();
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
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}
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else EEINST_RESETHASLIVE1(_Rt_);
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return;
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}
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if( _Rd_ == 25 ) {
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_deleteEEreg(_Rt_, 0);
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switch(_Imm_ & 0x3F){
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case 0:
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pccr);
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break;
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case 1:
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// check if needs to be incremented
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MOV32MtoR(ECX, (uptr)&cpuRegs.PERF.n.pccr);
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pcr0);
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AND32ItoR(ECX, 0x800003E0);
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CMP32ItoR(ECX, 0x80000020);
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j8Ptr[0] = JNE8(0);
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MOV32MtoR(EDX, (uptr)&cpuRegs.cycle);
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SUB32MtoR(EAX, (uptr)&s_iLastPERFCycle[0]);
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ADD32RtoR(EAX, EDX);
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MOV32RtoM((uptr)&s_iLastPERFCycle[0], EDX);
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MOV32RtoM((uptr)&cpuRegs.PERF.n.pcr0, EAX);
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x86SetJ8(j8Ptr[0]);
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break;
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case 3:
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// check if needs to be incremented
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MOV32MtoR(ECX, (uptr)&cpuRegs.PERF.n.pccr);
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pcr1);
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AND32ItoR(ECX, 0x800F8000);
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CMP32ItoR(ECX, 0x80008000);
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j8Ptr[0] = JNE8(0);
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MOV32MtoR(EDX, (uptr)&cpuRegs.cycle);
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SUB32MtoR(EAX, (uptr)&s_iLastPERFCycle[1]);
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ADD32RtoR(EAX, EDX);
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MOV32RtoM((uptr)&s_iLastPERFCycle[1], EDX);
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MOV32RtoM((uptr)&cpuRegs.PERF.n.pcr1, EAX);
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x86SetJ8(j8Ptr[0]);
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break;
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}
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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if(EEINST_ISLIVE1(_Rt_)) {
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CDQ();
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
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}
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else EEINST_RESETHASLIVE1(_Rt_);
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#ifdef PCSX2_DEVBUILD
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COP0_LOG("MFC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
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cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);
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#endif
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return;
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}
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else if( _Rd_ == 24){
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COP0_LOG("MFC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
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return;
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}
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_eeOnWriteReg(_Rt_, 1);
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if( EEINST_ISLIVE1(_Rt_) ) {
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_deleteEEreg(_Rt_, 0);
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MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
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CDQ();
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0], EAX);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
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}
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else {
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EEINST_RESETHASLIVE1(_Rt_);
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if( (mmreg = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_WRITE)) >= 0 ) {
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|
MOVDMtoMMX(mmreg, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
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SetMMXstate();
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}
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else if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ)) >= 0) {
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||||||
|
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||||||
|
if( EEINST_ISLIVE2(_Rt_) ) {
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||||||
|
if( xmmregs[mmreg].mode & MODE_WRITE ) {
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|
SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[_Rt_].UL[2], mmreg);
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|
}
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|
xmmregs[mmreg].inuse = 0;
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|
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||||||
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MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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|
}
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else {
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SSE_MOVLPS_M64_to_XMM(mmreg, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
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|
}
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|
}
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|
else {
|
||||||
|
MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
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|
if(_Rd_ == 12) AND32ItoR(EAX, 0xf0c79c1f);
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||||||
|
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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||||||
|
if(EEINST_ISLIVE1(_Rt_)) {
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|
CDQ();
|
||||||
|
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
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||||||
|
}
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||||||
|
else {
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||||||
|
EEINST_RESETHASLIVE1(_Rt_);
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||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
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void updatePCCR()
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||||||
|
{
|
||||||
|
// read the old pccr and update pcr0/1
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pccr);
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|
MOV32RtoR(EDX, EAX);
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MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
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|
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||||||
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AND32ItoR(EAX, 0x800003E0);
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CMP32ItoR(EAX, 0x80000020);
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j8Ptr[0] = JNE8(0);
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||||||
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MOV32MtoR(EAX, (uptr)&s_iLastPERFCycle[0]);
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||||||
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ADD32RtoM((uptr)&cpuRegs.PERF.n.pcr0, ECX);
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SUB32RtoM((uptr)&cpuRegs.PERF.n.pcr0, EAX);
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|
x86SetJ8(j8Ptr[0]);
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||||||
|
|
||||||
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AND32ItoR(EDX, 0x800F8000);
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CMP32ItoR(EDX, 0x80008000);
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||||||
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j8Ptr[0] = JNE8(0);
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||||||
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MOV32MtoR(EAX, (uptr)&s_iLastPERFCycle[1]);
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ADD32RtoM((uptr)&cpuRegs.PERF.n.pcr1, ECX);
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||||||
|
SUB32RtoM((uptr)&cpuRegs.PERF.n.pcr1, EAX);
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||||||
|
x86SetJ8(j8Ptr[0]);
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||||||
|
}
|
||||||
|
|
||||||
|
void recMTC0()
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||||||
|
{
|
||||||
|
if( GPR_IS_CONST1(_Rt_) ) {
|
||||||
|
switch (_Rd_) {
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||||||
|
case 12:
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||||||
|
iFlushCall(FLUSH_NODESTROY);
|
||||||
|
//_flushCachedRegs(); //NOTE: necessary?
|
||||||
|
_callFunctionArg1((uptr)WriteCP0Status, MEM_CONSTTAG, g_cpuConstRegs[_Rt_].UL[0]);
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||||||
|
break;
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||||||
|
case 9:
|
||||||
|
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
|
||||||
|
MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
|
||||||
|
MOV32ItoM((uptr)&cpuRegs.CP0.r[9], g_cpuConstRegs[_Rt_].UL[0]);
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||||||
|
break;
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||||||
|
case 25:
|
||||||
|
COP0_LOG("MTC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
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||||||
|
cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);
|
||||||
|
switch(_Imm_ & 0x3F){
|
||||||
|
case 0:
|
||||||
|
|
||||||
|
updatePCCR();
|
||||||
|
MOV32ItoM((uptr)&cpuRegs.PERF.n.pccr, g_cpuConstRegs[_Rt_].UL[0]);
|
||||||
|
|
||||||
|
// update the cycles
|
||||||
|
MOV32RtoM((uptr)&s_iLastPERFCycle[0], ECX);
|
||||||
|
MOV32RtoM((uptr)&s_iLastPERFCycle[1], ECX);
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
MOV32MtoR(EAX, (uptr)&cpuRegs.cycle);
|
||||||
|
MOV32ItoM((uptr)&cpuRegs.PERF.n.pcr0, g_cpuConstRegs[_Rt_].UL[0]);
|
||||||
|
MOV32RtoM((uptr)&s_iLastPERFCycle[0], EAX);
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
MOV32MtoR(EAX, (uptr)&cpuRegs.cycle);
|
||||||
|
MOV32ItoM((uptr)&cpuRegs.PERF.n.pcr1, g_cpuConstRegs[_Rt_].UL[0]);
|
||||||
|
MOV32RtoM((uptr)&s_iLastPERFCycle[1], EAX);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 24:
|
||||||
|
COP0_LOG("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
MOV32ItoM((uptr)&cpuRegs.CP0.r[_Rd_], g_cpuConstRegs[_Rt_].UL[0]);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
switch (_Rd_) {
|
||||||
|
case 12:
|
||||||
|
iFlushCall(FLUSH_NODESTROY);
|
||||||
|
//_flushCachedRegs(); //NOTE: necessary?
|
||||||
|
_callFunctionArg1((uptr)WriteCP0Status, MEM_GPRTAG|_Rt_, 0);
|
||||||
|
break;
|
||||||
|
case 9:
|
||||||
|
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
|
||||||
|
_eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[9], _Rt_);
|
||||||
|
MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
|
||||||
|
break;
|
||||||
|
case 25:
|
||||||
|
COP0_LOG("MTC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
|
||||||
|
cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);
|
||||||
|
switch(_Imm_ & 0x3F){
|
||||||
|
case 0:
|
||||||
|
updatePCCR();
|
||||||
|
_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_);
|
||||||
|
|
||||||
|
// update the cycles
|
||||||
|
MOV32RtoM((uptr)&s_iLastPERFCycle[0], ECX);
|
||||||
|
MOV32RtoM((uptr)&s_iLastPERFCycle[1], ECX);
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
|
||||||
|
_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr0, _Rt_);
|
||||||
|
MOV32RtoM((uptr)&s_iLastPERFCycle[0], ECX);
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
|
||||||
|
_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr1, _Rt_);
|
||||||
|
MOV32RtoM((uptr)&s_iLastPERFCycle[1], ECX);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 24:
|
||||||
|
COP0_LOG("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
_eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[_Rd_], _Rt_);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*void rec(COP0) {
|
||||||
|
}
|
||||||
|
|
||||||
|
void rec(BC0F) {
|
||||||
|
}
|
||||||
|
|
||||||
|
void rec(BC0T) {
|
||||||
|
}
|
||||||
|
|
||||||
|
void rec(BC0FL) {
|
||||||
|
}
|
||||||
|
|
||||||
|
void rec(BC0TL) {
|
||||||
|
}
|
||||||
|
|
||||||
|
void rec(TLBR) {
|
||||||
|
}
|
||||||
|
|
||||||
|
void rec(TLBWI) {
|
||||||
|
}
|
||||||
|
|
||||||
|
void rec(TLBWR) {
|
||||||
|
}
|
||||||
|
|
||||||
|
void rec(TLBP) {
|
||||||
|
}*/
|
||||||
|
|
||||||
|
}}}}
|
||||||
|
|
@ -0,0 +1,47 @@
|
||||||
|
/* Pcsx2 - Pc Ps2 Emulator
|
||||||
|
* Copyright (C) 2002-2008 Pcsx2 Team
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __iCOP0_H__
|
||||||
|
#define __iCOP0_H__
|
||||||
|
|
||||||
|
/*********************************************************
|
||||||
|
* COP0 opcodes *
|
||||||
|
* *
|
||||||
|
*********************************************************/
|
||||||
|
|
||||||
|
namespace Dynarec {
|
||||||
|
namespace R5900 {
|
||||||
|
namespace OpcodeImpl {
|
||||||
|
namespace COP0
|
||||||
|
{
|
||||||
|
void recMFC0( void );
|
||||||
|
void recMTC0( void );
|
||||||
|
void recBC0F( void );
|
||||||
|
void recBC0T( void );
|
||||||
|
void recBC0FL( void );
|
||||||
|
void recBC0TL( void );
|
||||||
|
void recTLBR( void );
|
||||||
|
void recTLBWI( void );
|
||||||
|
void recTLBWR( void );
|
||||||
|
void recTLBP( void );
|
||||||
|
void recERET( void );
|
||||||
|
void recDI( void );
|
||||||
|
void recEI( void );
|
||||||
|
|
||||||
|
}}}}
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue