mirror of https://github.com/PCSX2/pcsx2.git
newVif: fixed some bugs with mask/mode modes. i had forgotten that mVUmergeRegs() modifies the source reg's vectors, so data was being corrupted and breaking some games (sse4.1 users didn't have this problem).
This revision correctly fixes .hack GU Rebirth. At this point we don't know any games newVif breaks compared to the old vif code. If you know any please leave a comment. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2447 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -26,6 +26,18 @@
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static __pagealigned u8 nVifUpkExec[__pagesize*4];
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// Merges xmm vectors without modifying source reg
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void mergeVectors(int dest, int src, int temp, int xyzw) {
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if (x86caps.hasStreamingSIMD4Extensions || (xyzw==15)
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|| (xyzw==12) || (xyzw==11) || (xyzw==8) || (xyzw==3)) {
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mVUmergeRegs(dest, src, xyzw);
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}
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else {
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SSE_MOVAPS_XMM_to_XMM(temp, src);
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mVUmergeRegs(dest, temp, xyzw);
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}
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}
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// =====================================================================================================
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// VifUnpackSSE_Base Section
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// =====================================================================================================
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@ -26,6 +26,8 @@ using namespace x86Emitter;
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#if newVif
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extern void mergeVectors(int dest, int src, int temp, int xyzw);
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// --------------------------------------------------------------------------------------
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// VifUnpackSSE_Base
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// --------------------------------------------------------------------------------------
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@ -111,9 +111,10 @@ _f void VifUnpackSSE_Dynarec::SetMasks(int cS) const {
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void VifUnpackSSE_Dynarec::doMaskWrite(const xRegisterSSE& regX) const {
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pxAssumeDev(regX.Id <= 1, "Reg Overflow! XMM2 thru XMM6 are reserved for masking.");
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int t = regX.Id ? 0 : 1; // Get Temp Reg
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int cc = aMin(vCL, 3);
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u32 m0 = (vB.mask >> (cc * 8)) & 0xff;
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u32 m1 = m0 & 0xaaaa;
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u32 m1 = m0 & 0xaa;
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u32 m2 =(~m1>>1) & m0;
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u32 m3 = (m1>>1) & ~m0;
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u32 m4 = (m1>>1) & m0;
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@ -121,18 +122,18 @@ void VifUnpackSSE_Dynarec::doMaskWrite(const xRegisterSSE& regX) const {
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makeMergeMask(m3);
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makeMergeMask(m4);
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if (doMask&&m4) { xMOVAPS(xmmTemp, ptr[dstIndirect]); } // Load Write Protect
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if (doMask&&m2) { mVUmergeRegs(regX.Id, xmmRow.Id, m2); } // Merge Row
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if (doMask&&m3) { mVUmergeRegs(regX.Id, xmmCol0.Id+cc, m3); } // Merge Col
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if (doMask&&m4) { mVUmergeRegs(regX.Id, xmmTemp.Id, m4); } // Merge Write Protect
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if (doMask&&m2) { mergeVectors(regX.Id, xmmRow.Id, t, m2); } // Merge Row
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if (doMask&&m3) { mergeVectors(regX.Id, xmmCol0.Id+cc, t, m3); } // Merge Col
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if (doMask&&m4) { mergeVectors(regX.Id, xmmTemp.Id, t, m4); } // Merge Write Protect
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if (doMode) {
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u32 m5 = (~m1>>1) & ~m0;
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if (!doMask) m5 = 0xf;
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else makeMergeMask(m5);
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if (m5 < 0xf) {
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xPXOR(xmmTemp, xmmTemp);
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mVUmergeRegs(xmmTemp.Id, xmmRow.Id, m5);
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mergeVectors(xmmTemp.Id, xmmRow.Id, t, m5);
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xPADD.D(regX, xmmTemp);
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if (doMode==2) mVUmergeRegs(xmmRow.Id, regX.Id, m5);
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if (doMode==2) mergeVectors(xmmRow.Id, regX.Id, t, m5);
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}
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else if (m5 == 0xf) {
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xPADD.D(regX, xmmRow);
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@ -141,7 +141,8 @@ int nVifUnpack(int idx, u8* data) {
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}
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if (ret == v.vif->tag.size) { // Full Transfer
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dVifUnpack(idx, data, size, isFill);
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if (newVifDynaRec) dVifUnpack(idx, data, size, isFill);
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else _nVifUnpack(idx, data, size, isFill);
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vif->tag.size = 0;
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vif->cmd = 0;
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}
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