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microVU: FIX FINAL FANTASY X HAIR!!!111!!!1!! (Enthusiasm at rama's request. Thank him for being noisy enough about this to get it seriously looked at.) 

Negative zeroes were being treated as positive for the purpose of setting flags, which the documentation was ambiguous about.  Testing with real hardware confirmed that negative zeroes are still negative.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2818 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
sudonim1 2010-04-07 00:12:35 +00:00
parent 81c2318fea
commit fa8d5b1d79
1 changed files with 2 additions and 3 deletions
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pcsx2/x86/microVU_Upper.inl
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@ -46,11 +46,10 @@ static void mVUupdateFlags(mV, int reg, int regT1 = -1, int regT2 = -1, bool mod
//-------------------------Check for Signed flags------------------------------
// The following code makes sure the Signed Bit isn't set with Negative Zero
SSE_XORPS_XMM_to_XMM (regT1, regT1); // Clear regT2
SSE_MOVMSKPS_XMM_to_R32(mReg, regT2); // Move the Sign Bits of the t2reg
SSE_XORPS_XMM_to_XMM (regT1, regT1); // Clear regT1
SSE_CMPEQPS_XMM_to_XMM (regT1, regT2); // Set all F's if each vector is zero
SSE_MOVMSKPS_XMM_to_R32(gprT2, regT1); // Used for Zero Flag Calculation
SSE_ANDNPS_XMM_to_XMM (regT1, regT2); // Used for Sign Flag Calculation
SSE_MOVMSKPS_XMM_to_R32(mReg, regT1); // Move the Sign Bits of the t1reg
AND32ItoR(mReg, AND_XYZW); // Grab "Is Signed" bits from the previous calculation
SHL32ItoR(mReg, 4 + ADD_XYZW);