mirror of https://github.com/PCSX2/pcsx2.git
VIF: Some optimizations for the VIF Rec, some small clean-up/optimizations for VIF itself.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5368 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
refraction
parent
68a833f4e7
commit
f19c0b7ca9
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@ -257,12 +257,14 @@ static __fi void _vifCode_MPG(int idx, u32 addr, const u32 *data, int size) {
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vu1Thread.WriteMicroMem(addr, (u8*)data, size*4);
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return;
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}
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if (memcmp_mmx(VUx.Micro + addr, data, size*4)) {
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//The compare is pretty much a waste of time, likelyhood is that the program isnt there, thats why its copying it.
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//Faster without.
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//if (memcmp_mmx(VUx.Micro + addr, data, size*4)) {
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// Clear VU memory before writing!
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if (!idx) CpuVU0->Clear(addr, size*4);
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else CpuVU1->Clear(addr, size*4);
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memcpy_fast(VUx.Micro + addr, data, size*4);
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}
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memcpy_aligned(VUx.Micro + addr, data, size*4); //from tests, memcpy is 1fps faster on Grandia 3 than memcpy_fast
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//}
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}
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vifOp(vifCode_MPG) {
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@ -381,14 +383,6 @@ vifOp(vifCode_Nop) {
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pass1 {
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GetVifX.cmd = 0;
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GetVifX.pass = 0;
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/*if(idx && vif1ch.chcr.STR == true)
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{
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//Some games use a huge stream of NOPS to wait for a GIF packet to start, alas the way PCSX2 works it never starts
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//So the mask can go on before the packet continues, causing desync.
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if(((data[1] >> 24) & 0x7f) == 0x6) //Look in to the future and see if we have a mask path 3 command (NFSU)
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GetVifX.vifstalled = true; //Stall if we do to get the timing right.
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}*/
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}
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pass3 { VifCodeLog("Nop"); }
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return 1;
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@ -22,34 +22,12 @@
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// VifCode Transfer Interpreter (Vif0/Vif1)
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//------------------------------------------------------------------
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// Doesn't stall if the next vifCode is the Mark command
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_vifT bool runMark(u32* &data) {
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if (((vifXRegs.code >> 24) & 0x7f) == 0x7) {
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//DevCon.WriteLn("Vif%d: Running Mark with I-bit", idx);
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return 1; // No Stall?
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}
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return 1; // Stall
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}
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// Returns 1 if i-bit && finished vifcode && i-bit not masked
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_vifT bool analyzeIbit(u32* &data, int iBit) {
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vifStruct& vifX = GetVifX;
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if (iBit && !vifX.cmd && !vifXRegs.err.MII) {
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//DevCon.WriteLn("Vif I-Bit IRQ");
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vifX.irq++;
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if(CHECK_VIF1STALLHACK) return 0;
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else return 1;
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}
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return 0;
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}
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// Interprets packet
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_vifT void vifTransferLoop(u32* &data) {
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vifStruct& vifX = GetVifX;
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u32& pSize = vifX.vifpacketsize;
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int iBit = vifX.cmd >> 7;
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int ret = 0;
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vifXRegs.stat.VPS |= VPS_TRANSFERRING;
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@ -58,11 +36,19 @@ _vifT void vifTransferLoop(u32* &data) {
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while (pSize > 0 && !vifX.vifstalled) {
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if(!vifX.cmd) { // Get new VifCode
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if(!vifXRegs.err.MII)
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{
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if(vifX.irq && !CHECK_VIF1STALLHACK)
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break;
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vifX.irq = data[0] >> 31;
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}
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vifXRegs.code = data[0];
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vifX.cmd = data[0] >> 24;
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iBit = data[0] >> 31;
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//VIF_LOG("New VifCMD %x tagsize %x", vifX.cmd, vifX.tag.size);
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if (IsDevBuild && SysTrace.EE.VIFcode.IsActive()) {
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// Pass 2 means "log it"
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@ -73,10 +59,7 @@ _vifT void vifTransferLoop(u32* &data) {
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ret = vifCmdHandler[idx][vifX.cmd & 0x7f](vifX.pass, data);
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data += ret;
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pSize -= ret;
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if (analyzeIbit<idx>(data, iBit)) break;
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}
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if (pSize) vifX.vifstalled = true;
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}
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_vifT static __fi bool vifTransfer(u32 *data, int size, bool TTE) {
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@ -75,12 +75,14 @@ __fi void VifUnpackSSE_Dynarec::SetMasks(int cS) const {
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const int idx = v.idx;
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const vifStruct& vif = MTVU_VifX;
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u32 m0 = vB.mask;
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u32 m1 = m0 & 0xaaaaaaaa;
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u32 m2 =(~m1>>1) & m0;
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u32 m3 = (m1>>1) & ~m0;
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if((m2&&doMask)||doMode) { xMOVAPS(xmmRow, ptr128[&vif.MaskRow]); }
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//This could have ended up copying the row when there was no row to write.1810080
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u32 m0 = vB.mask; //The actual mask example 0x03020100
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u32 m3 = ((m0 & 0xaaaaaaaa)>>1) & ~m0; //all the upper bits, so our example 0x01010000 & 0xFCFDFEFF = 0x00010000 just the cols (shifted right for maskmerge)
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u32 m2 = (m0 & 0x55555555) & (~m0>>1); // 0x1000100 & 0xFE7EFF7F = 0x00000100 Just the row
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if((m2&&doMask)||doMode) { xMOVAPS(xmmRow, ptr128[&vif.MaskRow]); MSKPATH3_LOG("Moving row");}
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if (m3&&doMask) {
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MSKPATH3_LOG("Merging Cols");
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xMOVAPS(xmmCol0, ptr128[&vif.MaskCol]);
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if ((cS>=2) && (m3&0x0000ff00)) xPSHUF.D(xmmCol1, xmmCol0, _v1);
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if ((cS>=3) && (m3&0x00ff0000)) xPSHUF.D(xmmCol2, xmmCol0, _v2);
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@ -92,33 +94,37 @@ __fi void VifUnpackSSE_Dynarec::SetMasks(int cS) const {
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void VifUnpackSSE_Dynarec::doMaskWrite(const xRegisterSSE& regX) const {
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pxAssertDev(regX.Id <= 1, "Reg Overflow! XMM2 thru XMM6 are reserved for masking.");
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xRegisterSSE t = regX == xmm0 ? xmm1 : xmm0; // Get Temp Reg
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int cc = aMin(vCL, 3);
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u32 m0 = (vB.mask >> (cc * 8)) & 0xff;
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u32 m1 = m0 & 0xaa;
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u32 m2 =(~m1>>1) & m0;
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u32 m3 = (m1>>1) & ~m0;
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u32 m4 = (m1>>1) & m0;
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u32 m0 = (vB.mask >> (cc * 8)) & 0xff; //The actual mask example 0xE4 (protect, col, row, clear)
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u32 m3 = ((m0 & 0xaa)>>1) & ~m0; //all the upper bits (cols shifted right) cancelling out any write protects 0x10
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u32 m2 = (m0 & 0x55) & (~m0>>1); // all the lower bits (rows)cancelling out any write protects 0x04
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u32 m4 = (m0 & ~((m3<<1) | m2)) & 0x55; // = 0xC0 & 0x55 = 0x40 (for merge mask)
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makeMergeMask(m2);
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makeMergeMask(m3);
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makeMergeMask(m4);
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if (doMask&&m4) { xMOVAPS(xmmTemp, ptr[dstIndirect]); } // Load Write Protect
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if (doMask&&m2) { mergeVectors(regX, xmmRow, t, m2); } // Merge MaskRow
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if (doMask&&m3) { mergeVectors(regX, xRegisterSSE(xmmCol0.Id+cc), t, m3); } // Merge MaskCol
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if (doMask&&m4) { mergeVectors(regX, xmmTemp, t, m4); } // Merge Write Protect
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if (doMask&&m2) { mergeVectors(regX, xmmRow, xmmTemp, m2); } // Merge MaskRow
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if (doMask&&m3) { mergeVectors(regX, xRegisterSSE(xmmCol0.Id+cc), xmmTemp, m3); } // Merge MaskCol
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if (doMask&&m4) { xMOVAPS(xmmTemp, ptr[dstIndirect]);
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mergeVectors(regX, xmmTemp, xmmTemp, m4); } // Merge Write Protect
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if (doMode) {
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u32 m5 = (~m1>>1) & ~m0;
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u32 m5 = ~(m2|m3|m4) & 0xf;
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if (!doMask) m5 = 0xf;
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else makeMergeMask(m5);
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if (m5 < 0xf) {
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if (m5 < 0xf)
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{
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xPXOR(xmmTemp, xmmTemp);
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mergeVectors(xmmTemp, xmmRow, t, m5);
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mergeVectors(xmmTemp, xmmRow, xmmTemp, m5);
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xPADD.D(regX, xmmTemp);
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if (doMode==2) mergeVectors(xmmRow, regX, t, m5);
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if (doMode==2) mergeVectors(xmmRow, regX, xmmTemp, m5);
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}
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else if (m5 == 0xf) {
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else
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{
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xPADD.D(regX, xmmRow);
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if (doMode==2) xMOVAPS(xmmRow, regX);
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if (doMode==2){ xMOVAPS(xmmRow, regX); }
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}
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}
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xMOVAPS(ptr32[dstIndirect], regX);
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@ -127,6 +133,7 @@ void VifUnpackSSE_Dynarec::doMaskWrite(const xRegisterSSE& regX) const {
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void VifUnpackSSE_Dynarec::writeBackRow() const {
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const int idx = v.idx;
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xMOVAPS(ptr128[&(MTVU_VifX.MaskRow)], xmmRow);
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DevCon.WriteLn("nVif: writing back row reg! [doMode = 2]");
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// ToDo: Do we need to write back to vifregs.rX too!? :/
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}
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@ -143,9 +150,39 @@ static void ShiftDisplacementWindow( xAddressVoid& addr, const xRegister32& modR
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addImm += 0xf0;
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addr -= 0xf0;
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}
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if(addImm) xADD(modReg, addImm);
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if(addImm) { xADD(modReg, addImm); }
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}
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void VifUnpackSSE_Dynarec::ModUnpack( int upknum, bool PostOp )
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{
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switch( upknum )
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{
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case 0:
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case 1:
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case 2: UnpkNoOfIterations = 4; if(PostOp == true) { UnpkLoopIteration++; UnpkLoopIteration = UnpkLoopIteration % UnpkNoOfIterations; } break;
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case 4:
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case 5:
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case 6: UnpkNoOfIterations = 2; if(PostOp == true) { UnpkLoopIteration++; UnpkLoopIteration = UnpkLoopIteration % UnpkNoOfIterations; } break;
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case 8: break;
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case 9: break;
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case 10: break;
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case 12: break;
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case 13: break;
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case 14: break;
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case 15: break;
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case 3:
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case 7:
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case 11:
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pxFailRel( wxsFormat( L"Vpu/Vif - Invalid Unpack! [%d]", upknum ) );
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break;
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}
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}
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void VifUnpackSSE_Dynarec::CompileRoutine() {
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const int upkNum = vB.upkType & 0xf;
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const u8& vift = nVifT[upkNum];
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@ -155,29 +192,32 @@ void VifUnpackSSE_Dynarec::CompileRoutine() {
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uint vNum = vB.num ? vB.num : 256;
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doMode = (upkNum == 0xf) ? 0 : doMode; // V4_5 has no mode feature.
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MSKPATH3_LOG("Compiling new block, unpack number %x, mode %x, masking %x, vNum %x", upkNum, doMode, doMask, vNum);
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pxAssume(vCL == 0);
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UnpkLoopIteration = 0;
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// Value passed determines # of col regs we need to load
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SetMasks(isFill ? blockSize : cycleSize);
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while (vNum) {
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ShiftDisplacementWindow( srcIndirect, edx );
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ShiftDisplacementWindow( dstIndirect, ecx );
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if(UnpkNoOfIterations == 0)
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ShiftDisplacementWindow( srcIndirect, edx ); //Don't need to do this otherwise as we arent reading the source.
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if (vCL < cycleSize) {
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ModUnpack(upkNum, false);
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xUnpack(upkNum);
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xMovDest();
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ModUnpack(upkNum, true);
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dstIndirect += 16;
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srcIndirect += vift;
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if( IsUnmaskedOp() ) {
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++destReg;
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++workReg;
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}
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vNum--;
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if (++vCL == blockSize) vCL = 0;
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}
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@ -189,11 +229,6 @@ void VifUnpackSSE_Dynarec::CompileRoutine() {
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dstIndirect += 16;
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if( IsUnmaskedOp() ) {
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++destReg;
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++workReg;
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}
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vNum--;
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if (++vCL == blockSize) vCL = 0;
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}
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@ -256,7 +291,7 @@ _vifT static __ri bool dVifExecuteUnpack(const u8* data, bool isFill)
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((nVifrecCall)b->startPtr)((uptr)dest, (uptr)data);
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}
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else {
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//DevCon.WriteLn("Running Interpreter Block");
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DevCon.WriteLn("Running Interpreter Block");
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_nVifUnpack(idx, data, vifRegs.mode, isFill);
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}
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return true;
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@ -117,7 +117,7 @@ _vifT int nVifUnpack(const u8* data) {
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if (ret == vif.tag.size) { // Full Transfer
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if (v.bSize) { // Last transfer was partial
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memcpy_fast(&v.buffer[v.bSize], data, size);
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memcpy_aligned(&v.buffer[v.bSize], data, size);
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v.bSize += size;
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size = v.bSize;
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data = v.buffer;
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@ -140,7 +140,7 @@ _vifT int nVifUnpack(const u8* data) {
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v.bSize = 0;
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}
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else { // Partial Transfer
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memcpy_fast(&v.buffer[v.bSize], data, size);
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memcpy_aligned(&v.buffer[v.bSize], data, size);
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v.bSize += size;
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vif.tag.size -= ret;
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@ -25,7 +25,6 @@
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//static __pagealigned u8 nVifUpkExec[__pagesize*4];
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static RecompiledCodeReserve* nVifUpkExec = NULL;
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// Merges xmm vectors without modifying source reg
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void mergeVectors(xRegisterSSE dest, xRegisterSSE src, xRegisterSSE temp, int xyzw) {
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if (x86caps.hasStreamingSIMD4Extensions || (xyzw==15)
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@ -33,7 +32,7 @@ void mergeVectors(xRegisterSSE dest, xRegisterSSE src, xRegisterSSE temp, int xy
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mVUmergeRegs(dest, src, xyzw);
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}
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else {
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xMOVAPS(temp, src);
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if(temp != src) xMOVAPS(temp, src); //Sometimes we don't care if the source is modified and is temp reg.
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mVUmergeRegs(dest, temp, xyzw);
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}
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}
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@ -61,7 +60,7 @@ void VifUnpackSSE_Base::xShiftR(const xRegisterSSE& regX, int n) const {
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void VifUnpackSSE_Base::xPMOVXX8(const xRegisterSSE& regX) const {
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if (usn) xPMOVZX.BD(regX, ptr32[srcIndirect]);
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else xPMOVSX.BD(regX, ptr32[srcIndirect]);
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else xPMOVSX.BD(regX, ptr32[srcIndirect]);
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}
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void VifUnpackSSE_Base::xPMOVXX16(const xRegisterSSE& regX) const {
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@ -70,37 +69,87 @@ void VifUnpackSSE_Base::xPMOVXX16(const xRegisterSSE& regX) const {
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}
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void VifUnpackSSE_Base::xUPK_S_32() const {
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xMOV32 (workReg, ptr32[srcIndirect]);
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xPSHUF.D (destReg, workReg, _v0);
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switch(UnpkLoopIteration)
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{
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case 0:
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xMOV128 (workReg, ptr32[srcIndirect]);
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xPSHUF.D (destReg, workReg, _v0);
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break;
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case 1:
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xPSHUF.D (destReg, workReg, _v1);
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break;
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case 2:
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xPSHUF.D (destReg, workReg, _v2);
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break;
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case 3:
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xPSHUF.D (destReg, workReg, _v3);
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break;
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}
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}
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void VifUnpackSSE_Base::xUPK_S_16() const {
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if (x86caps.hasStreamingSIMD4Extensions)
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if (!x86caps.hasStreamingSIMD4Extensions)
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{
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xPMOVXX16 (workReg);
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xMOV16 (workReg, ptr32[srcIndirect]);
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xPUNPCK.LWD(workReg, workReg);
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xShiftR (workReg, 16);
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xPSHUF.D (destReg, workReg, _v0);
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return;
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}
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else
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{
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xMOV16 (workReg, ptr32[srcIndirect]);
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xPUNPCK.LWD(workReg, workReg);
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xShiftR (workReg, 16);
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switch(UnpkLoopIteration)
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{
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case 0:
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xPMOVXX16 (workReg);
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xPSHUF.D (destReg, workReg, _v0);
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break;
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case 1:
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xPSHUF.D (destReg, workReg, _v1);
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break;
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case 2:
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xPSHUF.D (destReg, workReg, _v2);
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break;
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case 3:
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xPSHUF.D (destReg, workReg, _v3);
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break;
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}
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xPSHUF.D (destReg, workReg, _v0);
|
||||
|
||||
}
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_S_8() const {
|
||||
if (x86caps.hasStreamingSIMD4Extensions)
|
||||
{
|
||||
xPMOVXX8 (workReg);
|
||||
}
|
||||
else
|
||||
|
||||
if (!x86caps.hasStreamingSIMD4Extensions)
|
||||
{
|
||||
xMOV8 (workReg, ptr32[srcIndirect]);
|
||||
xPUNPCK.LBW(workReg, workReg);
|
||||
xPUNPCK.LWD(workReg, workReg);
|
||||
xShiftR (workReg, 24);
|
||||
|
||||
xPSHUF.D (destReg, workReg, _v0);
|
||||
return;
|
||||
}
|
||||
xPSHUF.D (destReg, workReg, _v0);
|
||||
|
||||
switch(UnpkLoopIteration)
|
||||
{
|
||||
case 0:
|
||||
xPMOVXX8 (workReg);
|
||||
xPSHUF.D (destReg, workReg, _v0);
|
||||
break;
|
||||
case 1:
|
||||
xPSHUF.D (destReg, workReg, _v1);
|
||||
break;
|
||||
case 2:
|
||||
xPSHUF.D (destReg, workReg, _v2);
|
||||
break;
|
||||
case 3:
|
||||
xPSHUF.D (destReg, workReg, _v3);
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
// The V2 + V3 unpacks have freaky behaviour, the manual claims "indeterminate".
|
||||
|
|
@ -109,44 +158,75 @@ void VifUnpackSSE_Base::xUPK_S_8() const {
|
|||
// I have commented after each shuffle to show what data is going where - Ref
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_V2_32() const {
|
||||
xMOV64 (destReg, ptr32[srcIndirect]);
|
||||
xPSHUF.D (destReg, destReg, 0x44); //v1v0v1v0
|
||||
|
||||
if(UnpkLoopIteration == 0)
|
||||
{
|
||||
xMOV128 (workReg, ptr32[srcIndirect]);
|
||||
xPSHUF.D (destReg, workReg, 0x44); //v1v0v1v0
|
||||
}
|
||||
else
|
||||
{
|
||||
xPSHUF.D (destReg, workReg, 0xEE); //v3v2v3v2
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_V2_16() const {
|
||||
if (x86caps.hasStreamingSIMD4Extensions)
|
||||
|
||||
if(UnpkLoopIteration == 0 || !x86caps.hasStreamingSIMD4Extensions)
|
||||
{
|
||||
xPMOVXX16 (destReg);
|
||||
if (x86caps.hasStreamingSIMD4Extensions)
|
||||
{
|
||||
xPMOVXX16 (workReg);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
xMOV32 (workReg, ptr32[srcIndirect]);
|
||||
xPUNPCK.LWD(workReg, workReg);
|
||||
xShiftR (workReg, 16);
|
||||
}
|
||||
xPSHUF.D (destReg, workReg, 0x44); //v1v0v1v0
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
xMOV32 (destReg, ptr32[srcIndirect]);
|
||||
xPUNPCK.LWD(destReg, destReg);
|
||||
xShiftR (destReg, 16);
|
||||
xPSHUF.D (destReg, workReg, 0xEE); //v3v2v3v2
|
||||
}
|
||||
xPSHUF.D (destReg, destReg, 0x44); //v1v0v1v0
|
||||
|
||||
|
||||
}
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_V2_8() const {
|
||||
if (x86caps.hasStreamingSIMD4Extensions)
|
||||
|
||||
if(UnpkLoopIteration == 0 || !x86caps.hasStreamingSIMD4Extensions)
|
||||
{
|
||||
xPMOVXX8 (destReg);
|
||||
if (x86caps.hasStreamingSIMD4Extensions)
|
||||
{
|
||||
xPMOVXX8 (workReg);
|
||||
}
|
||||
else
|
||||
{
|
||||
xMOV16 (workReg, ptr32[srcIndirect]);
|
||||
xPUNPCK.LBW(workReg, workReg);
|
||||
xPUNPCK.LWD(workReg, workReg);
|
||||
xShiftR (workReg, 24);
|
||||
}
|
||||
xPSHUF.D (destReg, workReg, 0x44); //v1v0v1v0
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
xMOV16 (destReg, ptr32[srcIndirect]);
|
||||
xPUNPCK.LBW(destReg, destReg);
|
||||
xPUNPCK.LWD(destReg, destReg);
|
||||
xShiftR (destReg, 24);
|
||||
xPSHUF.D (destReg, workReg, 0xEE); //v3v2v3v2
|
||||
}
|
||||
xPSHUF.D (destReg, destReg, 0x44); //v1v0v1v0
|
||||
|
||||
}
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_V3_32() const {
|
||||
|
||||
xMOV128 (destReg, ptr128[srcIndirect]);
|
||||
}
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_V3_16() const {
|
||||
|
||||
if (x86caps.hasStreamingSIMD4Extensions)
|
||||
{
|
||||
xPMOVXX16 (destReg);
|
||||
|
|
@ -160,6 +240,7 @@ void VifUnpackSSE_Base::xUPK_V3_16() const {
|
|||
}
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_V3_8() const {
|
||||
|
||||
if (x86caps.hasStreamingSIMD4Extensions)
|
||||
{
|
||||
xPMOVXX8 (destReg);
|
||||
|
|
@ -174,10 +255,12 @@ void VifUnpackSSE_Base::xUPK_V3_8() const {
|
|||
}
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_V4_32() const {
|
||||
|
||||
xMOV128 (destReg, ptr32[srcIndirect]);
|
||||
}
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_V4_16() const {
|
||||
|
||||
if (x86caps.hasStreamingSIMD4Extensions)
|
||||
{
|
||||
xPMOVXX16 (destReg);
|
||||
|
|
@ -191,6 +274,7 @@ void VifUnpackSSE_Base::xUPK_V4_16() const {
|
|||
}
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_V4_8() const {
|
||||
|
||||
if (x86caps.hasStreamingSIMD4Extensions)
|
||||
{
|
||||
xPMOVXX8 (destReg);
|
||||
|
|
@ -205,6 +289,7 @@ void VifUnpackSSE_Base::xUPK_V4_8() const {
|
|||
}
|
||||
|
||||
void VifUnpackSSE_Base::xUPK_V4_5() const {
|
||||
|
||||
xMOV16 (workReg, ptr32[srcIndirect]);
|
||||
xPSHUF.D (workReg, workReg, _v0);
|
||||
xPSLL.D (workReg, 3); // ABG|R5.000
|
||||
|
|
|
|||
|
|
@ -34,12 +34,15 @@ class VifUnpackSSE_Base
|
|||
public:
|
||||
bool usn; // unsigned flag
|
||||
bool doMask; // masking write enable flag
|
||||
int UnpkLoopIteration;
|
||||
int UnpkNoOfIterations;
|
||||
|
||||
|
||||
protected:
|
||||
xAddressVoid dstIndirect;
|
||||
xAddressVoid srcIndirect;
|
||||
xRegisterSSE workReg;
|
||||
xRegisterSSE destReg;
|
||||
xRegisterSSE destReg;
|
||||
|
||||
public:
|
||||
VifUnpackSSE_Base();
|
||||
|
|
@ -105,7 +108,7 @@ class VifUnpackSSE_Dynarec : public VifUnpackSSE_Base
|
|||
public:
|
||||
bool isFill;
|
||||
int doMode; // two bit value representing... something!
|
||||
|
||||
|
||||
protected:
|
||||
const nVifStruct& v; // vif0 or vif1
|
||||
const nVifBlock& vB; // some pre-collected data from VifStruct
|
||||
|
|
@ -126,7 +129,9 @@ public:
|
|||
|
||||
virtual bool IsUnmaskedOp() const{ return !doMode && !doMask; }
|
||||
|
||||
void ModUnpack( int upknum, bool PostOp );
|
||||
void CompileRoutine();
|
||||
|
||||
|
||||
protected:
|
||||
virtual void doMaskWrite(const xRegisterSSE& regX) const;
|
||||
|
|
|
|||
Loading…
Reference in New Issue