mirror of https://github.com/PCSX2/pcsx2.git
microVU: tweaking/testing some stuff...
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1574 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
37675b6c49
commit
f058728f09
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@ -27,16 +27,18 @@
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#define SHIFT_XYZW(gprReg) { if (_XYZW_SS && modXYZW && !_W) { SHL32ItoR(gprReg, ADD_XYZW); } }
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// Note: If modXYZW is true, then it adjusts XYZW for Single Scalar operations
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microVUt(void) mVUupdateFlags(mV, int reg, int regT1, bool modXYZW = 1) {
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int sReg, mReg = gprT1, xyzw = _X_Y_Z_W, regT1b = 0;
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microVUt(void) mVUupdateFlags(mV, int reg, int regT1 = -1, int regT2 = -1, bool modXYZW = 1) {
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int sReg, mReg = gprT1, xyzw = _X_Y_Z_W, regT1b = 0, regT2b = 0;
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static const u16 flipMask[16] = {0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15};
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//SysPrintf("Status = %d; Mac = %d\n", sFLAG.doFlag, mFLAG.doFlag);
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if (mVUsFlagHack) { sFLAG.doFlag = 0; }
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if (!sFLAG.doFlag && !mFLAG.doFlag) { return; }
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if (!(!mFLAG.doFlag || (_XYZW_SS && modXYZW))) {
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SSE2_PSHUFD_XMM_to_XMM(reg, reg, 0x1B); // Flip wzyx to xyzw
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if (regT2 < 0) { regT2 = mVU->regAlloc->allocReg(); regT2b = 1; }
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SSE2_PSHUFD_XMM_to_XMM(regT2, reg, 0x1B); // Flip wzyx to xyzw
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}
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else regT2 = reg;
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if (sFLAG.doFlag) {
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getFlagReg(sReg, sFLAG.write); // Set sReg to valid GPR by Cur Flag Instance
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mVUallocSFLAGa(sReg, sFLAG.lastWrite); // Get Prev Status Flag
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@ -48,9 +50,9 @@ microVUt(void) mVUupdateFlags(mV, int reg, int regT1, bool modXYZW = 1) {
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// The following code makes sure the Signed Bit isn't set with Negative Zero
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SSE_XORPS_XMM_to_XMM (regT1, regT1); // Clear regT2
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SSE_CMPEQPS_XMM_to_XMM (regT1, reg); // Set all F's if each vector is zero
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SSE_CMPEQPS_XMM_to_XMM (regT1, regT2); // Set all F's if each vector is zero
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SSE_MOVMSKPS_XMM_to_R32(gprT2, regT1); // Used for Zero Flag Calculation
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SSE_ANDNPS_XMM_to_XMM (regT1, reg); // Used for Sign Flag Calculation
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SSE_ANDNPS_XMM_to_XMM (regT1, regT2); // Used for Sign Flag Calculation
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SSE_MOVMSKPS_XMM_to_R32(mReg, regT1); // Move the Sign Bits of the t1reg
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AND32ItoR(mReg, AND_XYZW); // Grab "Is Signed" bits from the previous calculation
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@ -64,9 +66,6 @@ microVUt(void) mVUupdateFlags(mV, int reg, int regT1, bool modXYZW = 1) {
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//-------------------------Write back flags------------------------------
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if (!(!mFLAG.doFlag || (_XYZW_SS && modXYZW))) {
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SSE2_PSHUFD_XMM_to_XMM(reg, reg, 0x1B); // Flip wzyx to xyzw
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}
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if (mFLAG.doFlag) mVUallocMFLAGb(mVU, mReg, mFLAG.write); // Set Mac Flag
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if (sFLAG.doFlag) {
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OR32RtoR (sReg, mReg);
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@ -76,6 +75,7 @@ microVUt(void) mVUupdateFlags(mV, int reg, int regT1, bool modXYZW = 1) {
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}
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}
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if (regT1b) mVU->regAlloc->clearNeeded(regT1);
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if (regT2b) mVU->regAlloc->clearNeeded(regT2);
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}
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//------------------------------------------------------------------
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@ -122,11 +122,10 @@ void setupPass1(microVU* mVU, int opCase, bool isACC, bool noFlagUpdate) {
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void setupFtReg(microVU* mVU, int& Ft, int opCase) {
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opCase1 { Ft = mVU->regAlloc->allocReg(_Ft_); }
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opCase2 {
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if (!_XYZW_SS) {
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Ft = mVU->regAlloc->allocReg(_Ft_, 0, 0xf);
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mVUunpack_xyzw(Ft, Ft, _bc_);
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}
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else Ft = mVU->regAlloc->allocReg(_Ft_);
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int tempFt = mVU->regAlloc->allocReg(_Ft_);
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Ft = mVU->regAlloc->allocReg();
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mVUunpack_xyzw(Ft, tempFt, _bc_);
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mVU->regAlloc->clearNeeded(tempFt);
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}
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opCase3 { Ft = mVU->regAlloc->allocReg(); getIreg(Ft, 1); }
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opCase4 { Ft = mVU->regAlloc->allocReg(); getQreg(Ft); }
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@ -147,23 +146,21 @@ void mVU_FMACa(microVU* mVU, int recPass, int opCase, int opType, bool isACC, co
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else { Fs = mVU->regAlloc->allocReg(_Fs_, _Fd_, _X_Y_Z_W); }
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS((1 << (3 - _bc_)))); } }
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opCase2 { if (opType == 2) { mVUclamp1(Fs, -1, _X_Y_Z_W); } } // Clamp Needed for alot of games (TOTA, DoM, etc...)
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if (_XYZW_SS) SSE_SS[opType](mVU, Fs, Ft, -1, -1);
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else SSE_PS[opType](mVU, Fs, Ft, -1, -1);
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS((1 << (3 - _bc_)))); } }
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if (isACC) {
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if (_XYZW_SS) SSE_MOVSS_XMM_to_XMM(ACC, Fs);
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else mVUmergeRegs(ACC, Fs, _X_Y_Z_W);
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mVUupdateFlags(mVU, ACC, Fs);
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mVUupdateFlags(mVU, ACC, Fs, ((opCase==2) ? Ft : -1));
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if (_XYZW_SS && _X_Y_Z_W != 8) SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleSS(_X_Y_Z_W));
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mVU->regAlloc->clearNeeded(ACC);
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}
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else mVUupdateFlags(mVU, Fs, (((opCase==2)&&(!_XYZW_SS)) ? Ft : -1));
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else mVUupdateFlags(mVU, Fs, ((opCase==2) ? Ft : -1));
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mVU->regAlloc->clearNeeded(Fs); // Always Clear Written Reg First
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mVU->regAlloc->clearNeeded(Ft);
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@ -183,19 +180,17 @@ void mVU_FMACb(microVU* mVU, int recPass, int opCase, int opType, const char* op
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if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleSS(_X_Y_Z_W)); }
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS((1 << (3 - _bc_)))); } }
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opCase2 { if (opType == 2) { mVUclamp1(Fs, -1, _X_Y_Z_W); } } // Clamp Needed for alot of games (TOTA, DoM, etc...)
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if (_XYZW_SS) SSE_SS[2](mVU, Fs, Ft, -1, -1);
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else SSE_PS[2](mVU, Fs, Ft, -1, -1);
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS((1 << (3 - _bc_)))); } }
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if (_XYZW_SS || _X_Y_Z_W == 0xf) {
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if (_XYZW_SS) SSE_SS[opType](mVU, ACC, Fs, -1, -1);
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else SSE_PS[opType](mVU, ACC, Fs, -1, -1);
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mVUupdateFlags(mVU, ACC, Fs);
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mVUupdateFlags(mVU, ACC, Fs, ((opCase==2) ? Ft : -1));
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if (_XYZW_SS && _X_Y_Z_W != 8) SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleSS(_X_Y_Z_W));
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}
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else {
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@ -225,17 +220,15 @@ void mVU_FMACc(microVU* mVU, int recPass, int opCase, const char* opName) {
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if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleSS(_X_Y_Z_W)); }
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS((1 << (3 - _bc_)))); } }
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opCase2 { mVUclamp1(Fs, -1, _X_Y_Z_W); } // Clamp Needed for alot of games (TOTA, DoM, etc...)
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if (_XYZW_SS) { SSE_SS[2](mVU, Fs, Ft, -1, -1); SSE_SS[0](mVU, Fs, ACC, -1, -1); }
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else { SSE_PS[2](mVU, Fs, Ft, -1, -1); SSE_PS[0](mVU, Fs, ACC, -1, -1); }
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mVUupdateFlags(mVU, Fs, -1);
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if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleSS(_X_Y_Z_W)); }
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS((1 << (3 - _bc_)))); } }
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mVUupdateFlags(mVU, Fs, ((opCase==2) ? Ft : -1));
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mVU->regAlloc->clearNeeded(Fs); // Always Clear Written Reg First
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mVU->regAlloc->clearNeeded(Ft);
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@ -255,15 +248,13 @@ void mVU_FMACd(microVU* mVU, int recPass, int opCase, const char* opName) {
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Fd = mVU->regAlloc->allocReg(32, _Fd_, _X_Y_Z_W);
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS((1 << (3 - _bc_)))); } }
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if (_XYZW_SS) { SSE_SS[2](mVU, Fs, Ft, -1, -1); SSE_SS[1](mVU, Fd, Fs, -1, -1); }
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else { SSE_PS[2](mVU, Fs, Ft, -1, -1); SSE_PS[1](mVU, Fd, Fs, -1, -1); }
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mVUupdateFlags(mVU, Fd, Fs);
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleSS((1 << (3 - _bc_)))); } }
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mVUupdateFlags(mVU, Fd, Fs, ((opCase==2) ? Ft : -1));
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mVU->regAlloc->clearNeeded(Fd); // Always Clear Written Reg First
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mVU->regAlloc->clearNeeded(Ft);
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@ -294,10 +285,9 @@ mVUop(mVU_OPMULA) {
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SSE2_PSHUFD_XMM_to_XMM(Fs, Fs, 0xC9); // WXZY
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SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, 0xD2); // WYXZ
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SSE_MULPS_XMM_to_XMM(Fs, Ft);
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mVUupdateFlags(mVU, Fs, Ft);
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mVU->regAlloc->clearNeeded(Fs);
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mVU->regAlloc->clearNeeded(Ft);
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mVUupdateFlags(mVU, Fs);
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mVU->regAlloc->clearNeeded(Fs);
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}
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pass3 { mVUlog("OPMULA"); mVUlogACC(); mVUlogFt(); }
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}
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@ -314,11 +304,11 @@ mVUop(mVU_OPMSUB) {
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SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, 0xD2); // WYXZ
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SSE_MULPS_XMM_to_XMM(Fs, Ft);
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SSE_SUBPS_XMM_to_XMM(ACC, Fs);
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mVUupdateFlags(mVU, ACC, Fs);
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mVU->regAlloc->clearNeeded(ACC);
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mVU->regAlloc->clearNeeded(Fs);
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mVU->regAlloc->clearNeeded(Ft);
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mVUupdateFlags(mVU, ACC);
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mVU->regAlloc->clearNeeded(ACC);
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}
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pass3 { mVUlog("OPMSUB"); mVUlogFd(); mVUlogFt(); }
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}
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