mirror of https://github.com/PCSX2/pcsx2.git
Minor EE Cache emulation changes (No fixes)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4609 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
refraction
parent
e615fe1c08
commit
efe1e665ee
100
pcsx2/Cache.cpp
100
pcsx2/Cache.cpp
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@ -39,41 +39,31 @@ int getFreeCache(u32 mem, int mode, int * way ) {
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u32 hand=(u8)vmv;
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u32 paddr=ppf-hand+0x80000000;
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if((cpuRegs.CP0.n.Config & 0x10000) == 0) DevCon.Warning("Cache off!");
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if((cpuRegs.CP0.n.Config & 0x10000) == 0) CACHE_LOG("Cache off!");
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if ((pCache[i].tag[0] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[i].tag[0] & VALID_FLAG))
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{
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*way = 0;
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if(pCache[i].tag[0] & LOCK_FLAG) DevCon.Warning("Index %x Way %x Locked!!", i, 0);
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if(pCache[i].tag[0] & LOCK_FLAG) CACHE_LOG("Index %x Way %x Locked!!", i, 0);
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return i;
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}
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else if((pCache[i].tag[1] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[i].tag[1] & VALID_FLAG))
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{
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*way = 1;
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if(pCache[i].tag[1] & LOCK_FLAG) DevCon.Warning("Index %x Way %x Locked!!", i, 1);
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if(pCache[i].tag[1] & LOCK_FLAG) CACHE_LOG("Index %x Way %x Locked!!", i, 1);
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return i;
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}
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number = ((pCache[i].tag[0]>>4) & 1) ^ ((pCache[i].tag[1]>>4) & 1);
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number = (((pCache[i].tag[0]) & LRF_FLAG) ^ ((pCache[i].tag[1]) & LRF_FLAG)) >> 4;
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ppf = (ppf & ~0x3F) ;
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if((pCache[i].tag[number] & (DIRTY_FLAG|VALID_FLAG)) == (DIRTY_FLAG|VALID_FLAG)) // Dirty
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if((pCache[i].tag[number] & (DIRTY_FLAG|VALID_FLAG)) == (DIRTY_FLAG|VALID_FLAG)) // Dirty Write
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{
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s32 oldppf = (pCache[i].tag[number] & ~0xf0000fff) + (mem & 0xFC0) + 0x20000000;
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CACHE_LOG("Dirty cache fill! PPF %x", oldppf);
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*reinterpret_cast<mem64_t*>(oldppf) = pCache[i].data[number][0].b8._u64[0];
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*reinterpret_cast<mem64_t*>(oldppf+8) = pCache[i].data[number][0].b8._u64[1];
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*reinterpret_cast<mem64_t*>(oldppf+16) = pCache[i].data[number][1].b8._u64[0];
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*reinterpret_cast<mem64_t*>(oldppf+24) = pCache[i].data[number][1].b8._u64[1];
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*reinterpret_cast<mem64_t*>(oldppf+32) = pCache[i].data[number][2].b8._u64[0];
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*reinterpret_cast<mem64_t*>(oldppf+40) = pCache[i].data[number][2].b8._u64[1];
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*reinterpret_cast<mem64_t*>(oldppf+48) = pCache[i].data[number][3].b8._u64[0];
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*reinterpret_cast<mem64_t*>(oldppf+56) = pCache[i].data[number][3].b8._u64[1];
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pCache[i].tag[number] &= ~DIRTY_FLAG;
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//Perform a cache miss.
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return -1;
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}
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@ -96,7 +86,6 @@ int getFreeCache(u32 mem, int mode, int * way ) {
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else
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pCache[i].tag[number] |= LRF_FLAG;
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return i;
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}
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@ -106,6 +95,14 @@ void writeCache8(u32 mem, u8 value) {
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//u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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//s32 ppf=(mem+vmv) & ~0x3f;
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i = getFreeCache(mem,1,&number);
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if(i == -1)
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{
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u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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s32 ppf=mem+vmv;
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*reinterpret_cast<mem8_t*>(ppf) = value;
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return;
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}
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CACHE_LOG("writeCache8 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
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pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
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pCache[i].data[number][(mem>>4) & 0x3].b8._u8[(mem&0xf)] = value;
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@ -116,6 +113,13 @@ void writeCache16(u32 mem, u16 value) {
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//u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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//s32 ppf=(mem+vmv) & ~0x3f;
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i = getFreeCache(mem,1,&number);
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if(i == -1)
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{
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u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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s32 ppf=mem+vmv;
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*reinterpret_cast<mem16_t*>(ppf) = value;
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return;
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}
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CACHE_LOG("writeCache16 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
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pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
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pCache[i].data[number][(mem>>4) & 0x3].b8._u16[(mem&0xf)>>1] = value;
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@ -126,6 +130,13 @@ void writeCache32(u32 mem, u32 value) {
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//u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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//s32 ppf=(mem+vmv) & ~0x3f;
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i = getFreeCache(mem,1,&number);
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if(i == -1)
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{
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u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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s32 ppf=mem+vmv;
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*reinterpret_cast<mem32_t*>(ppf) = value;
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return;
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}
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CACHE_LOG("writeCache32 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
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pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
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pCache[i].data[number][(mem>>4) & 0x3].b8._u32[(mem&0xf)>>2] = value;
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@ -136,6 +147,13 @@ void writeCache64(u32 mem, const u64 value) {
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//u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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//s32 ppf=(mem+vmv) & ~0x3f;
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i = getFreeCache(mem,1,&number);
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if(i == -1)
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{
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u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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s32 ppf=mem+vmv;
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*reinterpret_cast<mem64_t*>(ppf) = value;
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return;
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}
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CACHE_LOG("writeCache64 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
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pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
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pCache[i].data[number][(mem>>4) & 0x3].b8._u64[(mem&0xf)>>3] = value;
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@ -146,6 +164,14 @@ void writeCache128(u32 mem, const mem128_t* value){
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//u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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//s32 ppf=(mem+vmv) & ~0x3f;
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i = getFreeCache(mem,1,&number);
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if(i == -1)
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{
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u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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s32 ppf=mem+vmv;
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*reinterpret_cast<mem64_t*>(ppf) = value->lo;
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*reinterpret_cast<mem64_t*>(ppf+8) = value->hi;
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return;
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}
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CACHE_LOG("writeCache128 %8.8x adding to %d way %x tag %x vallo = %x_%x valhi = %x_%x", mem, i, number, pCache[i].tag[number], value->lo, value->hi);
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pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
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pCache[i].data[number][(mem>>4) & 0x3].b8._u64[0] = value->lo;
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@ -157,7 +183,12 @@ u8 readCache8(u32 mem) {
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i = getFreeCache(mem,0,&number);
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CACHE_LOG("readCache %8.8x from %d, way %d QW %x u8 part %x Really Reading %x", mem, i,number, (mem >> 4) & 0x3, (mem&0xf)>>2, (u32)pCache[i].data[number][(mem >> 4) & 0x3].b8._u8[(mem&0xf)]);
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if(i == -1)
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{
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u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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s32 ppf=mem+vmv;
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return *(u8*)ppf;
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}
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return pCache[i].data[number][(mem >> 4) & 0x3].b8._u8[(mem&0xf)];
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}
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@ -167,6 +198,13 @@ u16 readCache16(u32 mem) {
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i = getFreeCache(mem,0,&number);
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CACHE_LOG("readCache %8.8x from %d, way %d QW %x u16 part %x Really Reading %x", mem, i,number, (mem >> 4) & 0x3, (mem&0xf)>>2, (u32)pCache[i].data[number][(mem >> 4) & 0x3].b8._u16[(mem&0xf)>>1]);
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if(i == -1)
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{
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u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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s32 ppf=mem+vmv;
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return *(u16*)ppf;
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}
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return pCache[i].data[number][(mem >> 4) & 0x3].b8._u16[(mem&0xf)>>1];
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}
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@ -175,7 +213,12 @@ u32 readCache32(u32 mem) {
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i = getFreeCache(mem,0,&number);
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CACHE_LOG("readCache %8.8x from %d, way %d QW %x u32 part %x Really Reading %x", mem, i,number, (mem >> 4) & 0x3, (mem&0xf)>>2, (u32)pCache[i].data[number][(mem >> 4) & 0x3].b8._u32[(mem&0xf)>>2]);
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if(i == -1)
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{
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u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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s32 ppf=mem+vmv;
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return *(u32*)ppf;
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}
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return pCache[i].data[number][(mem >> 4) & 0x3].b8._u32[(mem&0xf)>>2];
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}
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@ -184,7 +227,12 @@ u64 readCache64(u32 mem) {
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i = getFreeCache(mem,0,&number);
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CACHE_LOG("readCache %8.8x from %d, way %d QW %x u64 part %x Really Reading %x_%x", mem, i,number, (mem >> 4) & 0x3, (mem&0xf)>>2, pCache[i].data[number][(mem >> 4) & 0x3].b8._u64[(mem&0xf)>>3]);
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if(i == -1)
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{
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u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
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s32 ppf=mem+vmv;
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return *(u64*)ppf;
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}
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return pCache[i].data[number][(mem >> 4) & 0x3].b8._u64[(mem&0xf)>>3];
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}
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@ -199,7 +247,7 @@ void CACHE() {
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u32 addr;
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addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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// DevCon.Warning("cpuRegs.GPR.r[_Rs_].UL[0] = %x, IMM = %x RT = %x", cpuRegs.GPR.r[_Rs_].UL[0], _Imm_, _Rt_);
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// CACHE_LOG("cpuRegs.GPR.r[_Rs_].UL[0] = %x, IMM = %x RT = %x", cpuRegs.GPR.r[_Rs_].UL[0], _Imm_, _Rt_);
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switch (_Rt_)
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{
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case 0x1a: //DHIN (Data Cache Hit Invalidate)
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@ -298,7 +346,7 @@ void CACHE() {
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{
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int index = (addr >> 6) & 0x3F;
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int way = 0;
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u32 pfnaddr = (pCache[index].tag[way] & ~0xf0000fff) | (addr & 0xfc0);
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u32 pfnaddr = (pCache[index].tag[way] & ~0x80000fff) | (addr & 0xfc0);
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u32 vmv=vtlbdata.vmap[pfnaddr>>VTLB_PAGE_BITS];
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s32 ppf=(pfnaddr+vmv) & ~0x3F;
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u32 hand=(u8)vmv;
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@ -404,7 +452,7 @@ void CACHE() {
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{
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int index = (addr >> 6) & 0x3F;
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int way = addr & 0x1;
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u32 pfnaddr = (pCache[index].tag[way] & ~0xf0000fff) + (addr & 0xFC0);
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u32 pfnaddr = (pCache[index].tag[way] & ~0x80000fff) + (addr & 0xFC0);
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u32 vmv=vtlbdata.vmap[pfnaddr >>VTLB_PAGE_BITS];
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s32 ppf=pfnaddr+vmv;
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u32 hand=(u8)vmv;
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@ -413,7 +461,7 @@ void CACHE() {
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CACHE_LOG("CACHE DXWBIN addr %x, index %d, way %d, Flags %x Paddr %x tag %x",addr,index,way,pCache[index].tag[way] & 0x78, paddr, pCache[index].tag[way]);
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if((pCache[index].tag[way] & (DIRTY_FLAG|VALID_FLAG)) == (DIRTY_FLAG|VALID_FLAG)) // Dirty
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{
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ppf = (ppf & 0x0fffffff) + 0x20000000;
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ppf = (ppf & 0x7fffffff);
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CACHE_LOG("DXWBIN Dirty WriteBack! PPF %x", ppf);
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*reinterpret_cast<mem64_t*>(ppf) = pCache[index].data[way][0].b8._u64[0];
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@ -450,7 +498,7 @@ void CACHE() {
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break;
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}
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default:
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CACHE_LOG("Cache mode %x not impemented", _Rt_);
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DevCon.Warning("Cache mode %x not impemented", _Rt_);
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break;
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}
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}
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@ -68,11 +68,19 @@ __inline int CheckCache(u32 addr)
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for(int i = 1; i < 48; i++)
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{
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if (((tlb[i].EntryLo1 & 0x38) >> 3) == 0x3 || ((tlb[i].EntryLo0 & 0x38) >> 3) == 0x3) {
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if (((tlb[i].EntryLo1 & 0x38) >> 3) == 0x3) {
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mask = tlb[i].PageMask;
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if ((addr >= tlb[i].PFN1) && (addr <= tlb[i].PFN1 + mask)) {
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//DevCon.Warning("Yay! Cache check cache addr=%x, mask=%x, addr+mask=%x, VPN2=%x PFN0=%x", addr, mask, (addr & mask), tlb[i].VPN2, tlb[i].PFN0);
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return true;
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}
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}
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if (((tlb[i].EntryLo0 & 0x38) >> 3) == 0x3) {
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mask = tlb[i].PageMask;
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if ((addr >= tlb[i].PFN0) && (addr <= tlb[i].PFN0 + mask)) {
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//DevCon.Warning("Yay! Cache check cache addr=%x, mask=%x, addr+mask=%x, VPN2=%x", addr, mask, (addr & mask), tlb[i].VPN2);
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//DevCon.Warning("Yay! Cache check cache addr=%x, mask=%x, addr+mask=%x, VPN2=%x PFN0=%x", addr, mask, (addr & mask), tlb[i].VPN2, tlb[i].PFN0);
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return true;
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}
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}
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