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pcsx2
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Initial work on getting further with PSX mode. Because the PSX rules! 

All work done by Refraction, I'm just the commit guy for this.

Note: Missing Visual Studio 2012 / 2010 project files and Linux makefile additions.
Note2: PSX games don't work yet :p

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5921 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
ramapcsx2.code 2014-03-06 23:00:09 +00:00
parent fb13a502d2
commit ef27358a82
18 changed files with 332 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
pcsx2/CDVD/CdRom.h
View File

@ -77,6 +77,7 @@ struct cdrStruct
int Init;
u8 IrqMask; // psxdev: Added on initial psx work, not referenced since. Is it needed?
u8 Irq;
u32 eCycle;

4
pcsx2/Config.h
View File

@ -546,3 +546,7 @@ TraceLogFilters& SetTraceConfig();
// games. Note: currently PS1 games will error out even without this
// commented, so this is for development purposes only.
#define ENABLE_LOADING_PS1_GAMES 0
// Change to 1 for console logs of SIF, GPU (PS1 mode) and MDEC (PS1 mode).
// These do spam a lot though!
#define PSX_EXTRALOGS 0

2
pcsx2/Hw.h
View File

@ -329,6 +329,8 @@ enum EERegisterAddresses
SBUS_F240 = 0x1000F240,
SBUS_F250 = 0x1000F250,
SBUS_F260 = 0x1000F260,
SBUS_F300 = 0x1000F300,
SBUS_F380 = 0x1000F380,
MCH_RICM = 0x1000F430,
MCH_DRD = 0x1000F440,

82
pcsx2/HwRead.cpp
View File

@ -17,7 +17,7 @@
#include "PrecompiledHeader.h"
#include "Common.h"
#include "Hardware.h"
#include "IopCommon.h"
#include "ps2/HwInternal.h"
#include "ps2/eeHwTraceLog.inl"
@ -31,6 +31,7 @@ static __fi void IntCHackCheck()
if( diff > 0 ) cpuRegs.cycle = g_nextEventCycle;
}
int shift = 0;
static const uint HwF_VerboseConLog = 1<<0;
static const uint HwF_IntcStatHack = 1<<1; // used for Reads only.
@ -91,9 +92,50 @@ mem32_t __fastcall _hwRead32(u32 mem)
return psHu32(INTC_STAT);
}
//if ((mem & 0x1000f200) == 0x1000f200)
// Console.Error("SBUS");
if ((mem & 0x1000ff00) == 0x1000f300)
{
int ret = 0;
u32 sif2fifosize = min(sif2.fifo.size, 7);
switch (mem & 0xf0)
{
case 0x00:
ret = psxHu32(0x1f801814);
break;
case 0x80:
#if PSX_EXTRALOGS
DevCon.Warning("FIFO Size %x", sif2fifosize);
#endif
ret = psHu32(mem) | (sif2fifosize << 16);
if (sif2.fifo.size > 0) ret |= 0x80000000;
break;
case 0xc0:
ReadFifoSingleWord();
ret = psHu32(mem);
break;
case 0xe0:
//ret = 0xa000e1ec;
if (sif2.fifo.size > 0)
{
ReadFifoSingleWord();
ret = psHu32(mem);
}
else ret = 0;
break;
}
#if PSX_EXTRALOGS
DevCon.Warning("SBUS read %x value sending %x", mem, ret);
#endif
return ret;
}
/*if ((mem & 0x1000ff00) == 0x1000f200)
{
if((mem & 0xffff) != 0xf230)DevCon.Warning("SBUS read %x value sending %x", mem, psHu32(mem));
}*/
switch( mem )
{
case SIO_ISR:
@ -245,6 +287,20 @@ static void _hwRead64(u32 mem, mem64_t* result )
_hwRead128<page>(mem & ~0x0f, &out128);
*result = out128._u64[wordpart];
}
return;
case 0x0F:
if ((mem & 0xffffff00) == 0x1000f300)
{
DevCon.Warning("64bit read from %x wibble", mem);
if (mem == 0x1000f3E0)
{
ReadFifoSingleWord();
*result = psHu32(0x1000f3E0);
ReadFifoSingleWord();
*result |= (u64)psHu32(0x1000f3E0) << 32;
}
}
return;
}
@ -288,7 +344,25 @@ void __fastcall _hwRead128(u32 mem, mem128_t* result )
// indeterminate state. The actual behavior probably isn't important.
ZeroQWC( result );
break;
case 0x0F:
if ((mem & 0xffffff00) == 0x1000f300)
{
DevCon.Warning("128bit read from %x wibble", mem);
if (mem == 0x1000f3E0)
{
ReadFifoSingleWord();
result->lo = psHu32(0x1000f3E0);
ReadFifoSingleWord();
result->lo |= (u64)psHu32(0x1000f3E0) << 32;
ReadFifoSingleWord();
result->hi = psHu32(0x1000f3E0);
ReadFifoSingleWord();
result->hi |= (u64)psHu32(0x1000f3E0) << 32;
}
}
break;
default:
_hwRead64<page>( mem, &result->lo );
result->hi = 0;

50
pcsx2/HwWrite.cpp
View File

@ -18,7 +18,7 @@
#include "Common.h"
#include "Hardware.h"
#include "Gif_Unit.h"
#include "IopCommon.h"
#include "ps2/HwInternal.h"
#include "ps2/eeHwTraceLog.inl"
@ -44,7 +44,10 @@ void __fastcall _hwWrite32( u32 mem, u32 value )
// All unknown registers on the EE are "reserved" as discarded writes and indeterminate
// reads. Bus error is only generated for registers outside the first 16k of mapped
// register space (which is handled by the VTLB mapping, so no need for checks here).
#if PSX_EXTRALOGS
if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("32bit Write to SIF Register %x value %x", mem, value);
//if ((mem & 0x1000ff00) == 0x1000f200) DevCon.Warning("Write to SIF Register %x value %x", mem, value);
#endif
switch (page)
{
case 0x00: if (!rcntWrite32<0x00>(mem, value)) return; break;
@ -180,6 +183,34 @@ void __fastcall _hwWrite32( u32 mem, u32 value )
psHu32(mem) = 0;
return;
mcase(SBUS_F300) :
psxHu32(0x1f801814) = value;
/*
if (sif2.fifo.size == 0) psxHu32(0x1f801814) |= 0x4000000;
switch ((psxHu32(HW_PS1_GPU_STATUS) >> 29) & 0x3)
{
case 0x0:
//DevCon.Warning("Set DMA Mode OFF");
psxHu32(HW_PS1_GPU_STATUS) &= ~0x2000000;
break;
case 0x1:
//DevCon.Warning("Set DMA Mode FIFO");
psxHu32(HW_PS1_GPU_STATUS) |= 0x2000000;
break;
case 0x2:
//DevCon.Warning("Set DMA Mode CPU->GPU");
psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x10000000) >> 3);
break;
case 0x3:
//DevCon.Warning("Set DMA Mode GPUREAD->CPU");
psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x8000000) >> 2);
break;
}*/
//psHu32(mem) = 0;
return;
mcase(SBUS_F380) :
psHu32(mem) = value;
return;
mcase(MCH_RICM)://MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5
if ((((value >> 16) & 0xFFF) == 0x21) && (((value >> 6) & 0xF) == 1) && (((psHu32(0xf440) >> 7) & 1) == 0))//INIT & SRP=0
rdram_sdevid = 0; // if SIO repeater is cleared, reset sdevid
@ -221,6 +252,9 @@ void __fastcall hwWrite32( u32 mem, u32 value )
template< uint page >
void __fastcall _hwWrite8(u32 mem, u8 value)
{
#if PSX_EXTRALOGS
if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("8bit Write to SIF Register %x value %x wibble", mem, value);
#endif
iswitch (mem)
icase(SIO_TXFIFO)
{
@ -276,7 +310,9 @@ template< uint page >
void __fastcall _hwWrite16(u32 mem, u16 value)
{
pxAssume( (mem & 0x01) == 0 );
#if PSX_EXTRALOGS
if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("16bit Write to SIF Register %x wibble", mem);
#endif
switch(mem & ~3)
{
case DMAC_STAT:
@ -310,7 +346,9 @@ void __fastcall _hwWrite64( u32 mem, const mem64_t* srcval )
// * FIFOs have 128 bit registers that are probably zero-fill.
// * All other registers likely disregard the upper 32-bits and simply act as normal
// 32-bit writes.
#if PSX_EXTRALOGS
if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("64bit Write to SIF Register %x wibble", mem);
#endif
switch (page)
{
case 0x02:
@ -355,7 +393,9 @@ void __fastcall _hwWrite128(u32 mem, const mem128_t* srcval)
// FIFOs are the only "legal" 128 bit registers. Handle them first.
// all other registers fall back on the 64-bit handler (and from there
// most of them fall back to the 32-bit handler).
#if PSX_EXTRALOGS
if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("128bit Write to SIF Register %x wibble", mem);
#endif
switch (page)
{
case 0x04:

2
pcsx2/IopCommon.h
View File

@ -27,7 +27,7 @@
#include "IopBios.h"
#include "IopCounters.h"
#include "IopSio2.h"
#include "Gte.h"
static const s64 PSXCLK = 36864000; /* 36.864 Mhz */
//#define PSXCLK 9216000 /* 36.864 Mhz */
//#define PSXCLK 186864000 /* 36.864 Mhz */

8
pcsx2/IopDma.cpp
View File

@ -134,8 +134,12 @@ void spu2DMA7Irq()
#ifndef DISABLE_PSX_GPU_DMAS
void psxDma2(u32 madr, u32 bcr, u32 chcr) // GPU
{
HW_DMA2_CHCR &= ~0x01000000;
psxDmaInterrupt(2);
DevCon.Warning("SIF2 IOP CHCR = %x MADR = %x BCR = %x first 16bits %x", chcr, madr, bcr, iopMemRead16(madr));
sif2.iop.busy = true;
sif2.iop.end = false;
//SIF2Dma();
dmaSIF2();
}
void psxDma6(u32 madr, u32 bcr, u32 chcr)

3
pcsx2/IopHw.h
View File

@ -257,6 +257,8 @@ static dma_mbc& hw_dma12 = (dma_mbc&) iopHw[0x1550];
#define HW_DMA2_MADR (psxHu32(0x10a0)) // GPU DMA
#define HW_DMA2_BCR (psxHu32(0x10a4))
#define HW_DMA2_BCR_L16 (psxHu16(0x10a4))
#define HW_DMA2_BCR_H16 (psxHu16(0x10a6))
#define HW_DMA2_CHCR (psxHu32(0x10a8))
#define HW_DMA2_TADR (psxHu32(0x10ac))
@ -309,6 +311,7 @@ static dma_mbc& hw_dma12 = (dma_mbc&) iopHw[0x1550];
enum IopEventId
{
IopEvt_SIFhack = 1 // The SIF likes to fall asleep and never wake up. This sends intermittent SBUS flags to rewake it.
, IopEvt_SIF2 = 2
, IopEvt_Cdvd = 5 // General Cdvd commands (Seek, Standby, Break, etc)
, IopEvt_SIF0 = 9
, IopEvt_SIF1 = 10

6
pcsx2/IopMem.cpp
View File

@ -386,6 +386,9 @@ void __fastcall iopMemWrite16(u32 mem, u16 value)
psHu32(SBUS_F260) = 0;
return;
}
#if PSX_EXTRALOGS
DevCon.Warning("IOP 16 Write to %x value %x", mem, value);
#endif
psxSu16(mem) = value; return;
}
if (t == 0x1F90) {
@ -469,6 +472,9 @@ void __fastcall iopMemWrite32(u32 mem, u32 value)
return;
}
#if PSX_EXTRALOGS
DevCon.Warning("IOP 32 Write to %x value %x", mem, value);
#endif
psxSu32(mem) = value;
// wtf? why were we writing to the EE's sif space? Commenting this out doesn't

1
pcsx2/R3000A.cpp
View File

@ -170,6 +170,7 @@ static __fi void _psxTestInterrupts()
{
IopTestEvent(IopEvt_SIF0, sif0Interrupt); // SIF0
IopTestEvent(IopEvt_SIF1, sif1Interrupt); // SIF1
IopTestEvent(IopEvt_SIF2, sif2Interrupt); // SIF2
#ifndef SIO_INLINE_IRQS
IopTestEvent(IopEvt_SIO, sioInterrupt);
#endif

32
pcsx2/R3000AOpcodeTables.cpp
View File

@ -290,6 +290,7 @@ void psxCFC0() { if (!_Rt_) return; _rRt_ = (int)_rFs_; }
void psxMTC0() { _rFs_ = _u32(_rRt_); }
void psxCTC0() { _rFs_ = _u32(_rRt_); }
void psxCTC2() { _c2dRd_ = _u32(_rRt_); };
/*********************************************************
* Unknown instruction (would generate an exception) *
* Format: ? *
@ -318,15 +319,16 @@ void psxBASIC() {
psxCP2BSC[_Rs_]();
}
void (*psxBSC[64])() = {
psxSPECIAL, psxREGIMM, psxJ , psxJAL , psxBEQ , psxBNE , psxBLEZ, psxBGTZ,
psxADDI , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI ,
psxCOP0 , psxNULL , psxCOP2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
psxNULL , psxNULL , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
psxLB , psxLH , psxLWL , psxLW , psxLBU , psxLHU , psxLWR , psxNULL,
psxSB , psxSH , psxSWL , psxSW , psxNULL, psxNULL, psxSWR , psxNULL,
psxNULL , psxNULL , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
psxNULL , psxNULL , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL
psxSPECIAL, psxREGIMM, psxJ , psxJAL , psxBEQ , psxBNE , psxBLEZ, psxBGTZ, //7
psxADDI , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI , //15
psxCOP0 , psxNULL , psxCOP2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, //23
psxNULL , psxNULL , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, //31
psxLB , psxLH , psxLWL , psxLW , psxLBU , psxLHU , psxLWR , psxNULL, //39
psxSB , psxSH , psxSWL , psxSW , psxNULL, psxNULL, psxSWR , psxNULL, //47
psxNULL , psxNULL , gteLWC2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, //55
psxNULL , psxNULL , gteSWC2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL //63
};
@ -356,18 +358,18 @@ void (*psxCP0[32])() = {
};
void (*psxCP2[64])() = {
psxBASIC, psxNULL , psxNULL , psxNULL, psxNULL, psxNULL , psxNULL, psxNULL, // 00
psxNULL , psxNULL , psxNULL , psxNULL, psxNULL , psxNULL , psxNULL , psxNULL, // 08
psxNULL , psxNULL, psxNULL, psxNULL, psxNULL , psxNULL , psxNULL , psxNULL, // 10
psxNULL , psxNULL , psxNULL , psxNULL, psxNULL , psxNULL , psxNULL , psxNULL, // 18
psxNULL , psxNULL , psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, // 20
psxNULL , psxNULL , psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, // 28
psxBASIC, gteRTPS, psxNULL , psxNULL, psxNULL, psxNULL , gteNCLIP, psxNULL, // 00
psxNULL , psxNULL , psxNULL , psxNULL, gteOP, psxNULL , psxNULL , psxNULL, // 08
gteDPCS, gteINTPL, gteMVMVA, gteNCDS, gteCDP, psxNULL , gteNCDT, psxNULL, // 10
psxNULL , psxNULL , psxNULL , gteNCCS, gteCC, psxNULL , gteNCS, psxNULL, // 18
gteNCT, psxNULL , psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, // 20
gteSQR, gteDCPL, gteDPCT, psxNULL, psxNULL, gteAVSZ3, gteAVSZ4, psxNULL, // 28
psxNULL , psxNULL , psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, // 30
psxNULL , psxNULL , psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL // 38
};
void (*psxCP2BSC[32])() = {
psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
gteMFC2, psxNULL, gteCFC2, psxNULL, gteMTC2, psxNULL, gteCTC2, psxNULL,
psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL

14
pcsx2/Sif.h
View File

@ -18,6 +18,9 @@
static const int FIFO_SIF_W = 128;
// psxdev: was here on the initial psx merge
//static u32 sif2fifostat = (u32&)eeHw[0xf380];
// Despite its name, this is actually the IOP's DMAtag, which itself also contains
// the EE's DMAtag in its upper 64 bits. Note that only the lower 24 bits of 'data' is
// the IOP's chain transfer address (loaded into MADR). Bits 30 and 31 are transfer stop
@ -119,12 +122,13 @@ struct _sif
sif_iop iop;
};
extern _sif sif0, sif1;
extern _sif sif0, sif1, sif2;
extern void sifInit();
extern void SIF0Dma();
extern void SIF1Dma();
extern void SIF2Dma();
extern void dmaSIF0();
extern void dmaSIF1();
@ -132,17 +136,25 @@ extern void dmaSIF2();
extern void EEsif0Interrupt();
extern void EEsif1Interrupt();
extern void EEsif2Interrupt();
extern void sif0Interrupt();
extern void sif1Interrupt();
extern void sif2Interrupt();
extern bool ReadFifoSingleWord();
extern bool WriteFifoSingleWord();
#define sif0data sif0.iop.data.data
#define sif1data sif1.iop.data.data
#define sif2data sif2.iop.data.data
#define sif0words sif0.iop.data.words
#define sif1words sif1.iop.data.words
#define sif2words sif2.iop.data.words
#define sif0tag DMA_TAG(sif0data)
#define sif1tag DMA_TAG(sif1data)
#define sif2tag DMA_TAG(sif2data)
#endif /* __SIF_H__ */

50
pcsx2/ps2/Iop/IopHwRead.cpp
View File

@ -16,7 +16,7 @@
#include "PrecompiledHeader.h"
#include "IopHw_Internal.h"
#include "Sif.h"
#include "Sio.h"
#include "CDVD/CdRom.h"
@ -222,6 +222,8 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
}
else
{
u32 sif2fifosize = sif2.fifo.size;
switch( masked_addr )
{
// ------------------------------------------------------------------------
@ -295,22 +297,60 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
// ------------------------------------------------------------------------
// Legacy GPU emulation
//
mcase (HW_PS1_GPU_DATA):
mcase(0x1f8010ac) :
ret = psxHu32(addr);
DevCon.Warning("SIF2 IOP TADR?? read");
break;
mcase(HW_PS1_GPU_DATA) :
ret = psxHu32(addr);
DevCon.Warning("GPU Data Read %x", ret);
break;
mcase (HW_PS1_GPU_STATUS):
ret = psxHu32(addr);
mcase(HW_PS1_GPU_STATUS) :
//ret = psxHu32(addr);
/*if (sif2fifosize == 0x8) psxHu32(0x1f801814) &= ~(3 << 25);
else psxHu32(0x1f801814) |= (3 << 25);*/
/*switch ((psxHu32(HW_PS1_GPU_STATUS) >> 29) & 0x3)
{
case 0x0:
//DevCon.Warning("Set DMA Mode OFF");
psxHu32(HW_PS1_GPU_STATUS) &= ~0x2000000;
break;
case 0x1:
//DevCon.Warning("Set DMA Mode FIFO");
psxHu32(HW_PS1_GPU_STATUS) |= 0x2000000;
break;
case 0x2:
//DevCon.Warning("Set DMA Mode CPU->GPU");
psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x10000000) >> 3);
break;
case 0x3:
//DevCon.Warning("Set DMA Mode GPUREAD->CPU");
psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x8000000) >> 2);
break;
}*/
ret = psxHu32(addr); //Idle & Ready to recieve command.
//psxHu32(addr) = psHu32(0x1000f300);
#if PSX_EXTRALOGS
DevCon.Warning("GPU Status Read %x Sif fifo size %x", ret, sif2fifosize);
#endif
//ret = -1; // fake alive GPU :p
break;
mcase (0x1f801820): // MDEC
ret = psxHu32(addr);
#if PSX_EXTRALOGS
DevCon.Warning("MDEC 1820 Read %x", ret);
#endif
break;
mcase (0x1f801824): // MDEC
ret = psxHu32(addr);
#if PSX_EXTRALOGS
DevCon.Warning("MDEC 1824 Read %x", ret);
#endif
break;
// ------------------------------------------------------------------------

99
pcsx2/ps2/Iop/IopHwWrite.cpp
View File

@ -15,7 +15,7 @@
#include "PrecompiledHeader.h"
#include "IopHw_Internal.h"
#include "Sif.h"
#include "Sio.h"
#include "CDVD/CdRom.h"
@ -348,11 +348,16 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
mcase(0x1f801098): // DMA1 CHCR -- MDEC OUT [ignored]
DmaExec(1);
break;*/
mcase(0x1f8010ac):
DevCon.Warning("SIF2 IOP TADR?? write");
psxHu(addr) = val;
break;
mcase(0x1f8010a8): // DMA2 CHCR -- GPU [ignored]
mcase(0x1f8010a8) : // DMA2 CHCR -- GPU [ignored]
psxHu(addr) = val;
DmaExec(2);
break;*/
break;
mcase(0x1f8010b8): // DMA3 CHCR -- CDROM
psxHu(addr) = val;
@ -456,19 +461,101 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
// Legacy GPU emulation
//
mcase (HW_PS1_GPU_DATA):
psxHu(addr) = val; // guess
mcase(HW_PS1_GPU_DATA) :
DevCon.Warning("GPUDATA Write %x", val);
/*if (val == 0x00000000)
{
psxHu32(HW_PS1_GPU_STATUS) = 0x14802000;
}
else if (val == 0x01000000)
{
DevCon.Warning("GP0 FIFO Clear");
sif2.fifo.clear();
}
else
{*/
psxHu(HW_PS1_GPU_DATA) = val; // guess
WriteFifoSingleWord();
//}
//GPU_writeData(value); // really old code from PCSX? (rama)
break;
mcase (HW_PS1_GPU_STATUS):
psxHu(addr) = val; // guess
DevCon.Warning("GPUSTATUS Write Command %x Param %x", (u32)val >> 24, val & 0xffffff);
//psxHu(addr) = val; // guess
//psxHu(HW_PS1_GPU_STATUS) = val;
//WriteFifoSingleWord();
// psxHu(HW_PS1_GPU_DATA) = val; // guess
// WriteFifoSingleWord();
/*if (val == 0) //Reset
{
psxHu32(HW_PS1_GPU_STATUS) = 0x14802000;
}
else if (val == 0x10000007) //Get GPU version
{
//DevCon.Warning("Get Version");
psxHu(HW_PS1_GPU_DATA) = 2;
}
else if ((val & 0xff000000) == 0x04000000)
{
//psxHu32(HW_PS1_GPU_STATUS) = psxHu32(HW_PS1_GPU_STATUS) &= ~0x60000000;
psxHu32(HW_PS1_GPU_STATUS) |= (val & 0x3) << 29;
switch (val & 0x3)
{
case 0x0:
//DevCon.Warning("Set DMA Mode OFF");
psxHu32(HW_PS1_GPU_STATUS) &= ~0x2000000;
break;
case 0x1:
//DevCon.Warning("Set DMA Mode FIFO");
psxHu32(HW_PS1_GPU_STATUS) |= 0x2000000;
break;
case 0x2:
//DevCon.Warning("Set DMA Mode CPU->GPU");
psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x10000000) >> 3);
break;
case 0x3:
//DevCon.Warning("Set DMA Mode GPUREAD->CPU");
psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x8000000) >> 2);
break;
}
}
else if (val == 0x03000000)
{
// DevCon.Warning("Turn Display on");
psxHu32(HW_PS1_GPU_STATUS) &= ~(1 << 23);
}
else if ((val & 0xff000000) == 0x05000000)
{
DevCon.Warning("Start display area");
//psxHu32(HW_PS1_GPU_STATUS) |= 0x80000000;
//psxHu32(HW_PS1_GPU_STATUS) &= ~(1 << 26);
}
else if ((val & 0xff000000) == 0x08000000)
{
//DevCon.Warning("Display Mode");
psxHu32(HW_PS1_GPU_STATUS) &= ~0x7F4000;
psxHu32(HW_PS1_GPU_STATUS) |= (u32)(val & 0x3f) << 17;
psxHu32(HW_PS1_GPU_STATUS) |= (u32)(val & 0x40) << 10;
psxHu32(HW_PS1_GPU_STATUS) |= (u32)(val & 0x80) << 7;
//psxHu32(HW_PS1_GPU_STATUS) |= 0x80000000;
//psxHu32(HW_PS1_GPU_STATUS) &= ~(1 << 26);
}
else
{
//DevCon.Warning("Unknown GP1 Command");
}*/
//GPU_writeStatus(value); // really old code from PCSX? (rama)
break;
mcase (0x1f801820): // MDEC
DevCon.Warning("MDEX 1820 Write %x", val);
psxHu(addr) = val; // guess
//mdecWrite0(value); // really old code from PCSX? (rama)
break;
mcase (0x1f801824): // MDEC
DevCon.Warning("MDEX 1824 Write %x", val);
psxHu(addr) = val; // guess
//mdecWrite1(value); // really old code from PCSX? (rama)
break;

2
pcsx2/ps2/Iop/IopHw_Internal.h
View File

@ -133,7 +133,7 @@ static __ri const char* _ioplog_GetHwName( u32 addr, T val )
case 0x1f801574: return "DMA ICR2";
case 0x1f801576: return "DMA ICR2_hi";
case HW_CDR_DATA0: return "CDROM DATA0";
case HW_CDR_DATA0: return "CDROM DATA0 (Index/Status Reg)";
case HW_CDR_DATA1: return "CDROM DATA1";
case HW_CDR_DATA2: return "CDROM DATA2";
case HW_CDR_DATA3: return "CDROM DATA3";

3
pcsx2/windows/VCprojects/pcsx2_vs2013.vcxproj
View File

@ -416,6 +416,7 @@
<ClCompile Include="..\..\GameDatabase.cpp" />
<ClCompile Include="..\..\Gif_Logger.cpp" />
<ClCompile Include="..\..\Gif_Unit.cpp" />
<ClCompile Include="..\..\Gte.c" />
<ClCompile Include="..\..\gui\AppGameDatabase.cpp" />
<ClCompile Include="..\..\gui\AppUserMode.cpp" />
<ClCompile Include="..\..\gui\Debugger\BreakpointWindow.cpp" />
@ -439,6 +440,7 @@
</ClCompile>
<ClCompile Include="..\..\ps2\LegacyDmac.cpp" />
<ClCompile Include="..\..\ShiftJisToUnicode.cpp" />
<ClCompile Include="..\..\sif2.cpp" />
<ClCompile Include="..\..\Utilities\FileUtils.cpp" />
<ClCompile Include="..\..\Dump.cpp" />
<ClCompile Include="..\..\x86\iMisc.cpp" />
@ -699,6 +701,7 @@
<ClInclude Include="..\..\DebugTools\SymbolMap.h" />
<ClInclude Include="..\..\GameDatabase.h" />
<ClInclude Include="..\..\Gif_Unit.h" />
<ClInclude Include="..\..\Gte.h" />
<ClInclude Include="..\..\gui\AppGameDatabase.h" />
<ClInclude Include="..\..\gui\Debugger\BreakpointWindow.h" />
<ClInclude Include="..\..\gui\Debugger\CtrlDisassemblyView.h" />

12
pcsx2/windows/VCprojects/pcsx2_vs2013.vcxproj.filters
View File

@ -151,6 +151,9 @@
<Filter Include="AppHost\Debugger">
<UniqueIdentifier>{7a0a1104-f9ee-4cd1-aaba-f8267eba1658}</UniqueIdentifier>
</Filter>
<Filter Include="System\Ps2\Iop\PS1 Components">
<UniqueIdentifier>{a3b47bd4-8c55-4128-9cdf-e44ef4a5efab}</UniqueIdentifier>
</Filter>
</ItemGroup>
<ItemGroup>
<None Include="..\..\Utilities\folderdesc.txt">
@ -841,6 +844,12 @@
<ClCompile Include="..\..\gui\Debugger\BreakpointWindow.cpp">
<Filter>AppHost\Debugger</Filter>
</ClCompile>
<ClCompile Include="..\..\Gte.c">
<Filter>System\Ps2\Iop\PS1 Components</Filter>
</ClCompile>
<ClCompile Include="..\..\sif2.cpp">
<Filter>System\Ps2\EmotionEngine\DMAC\Sif</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="..\..\Patch.h">
@ -1246,6 +1255,9 @@
<ClInclude Include="..\..\gui\Debugger\BreakpointWindow.h">
<Filter>AppHost\Debugger</Filter>
</ClInclude>
<ClInclude Include="..\..\Gte.h">
<Filter>System\Ps2\Iop\PS1 Components</Filter>
</ClInclude>
</ItemGroup>
<ItemGroup>
<ResourceCompile Include="..\..\..\3rdparty\wxWidgets\include\wx\msw\wx.rc">

1
pcsx2/x86/ix86-32/iCore-32.cpp
View File

@ -172,6 +172,7 @@ void _flushConstReg(int reg)
MOV32ItoM((int)&cpuRegs.GPR.r[reg].UL[0], g_cpuConstRegs[reg].UL[0]);
MOV32ItoM((int)&cpuRegs.GPR.r[reg].UL[1], g_cpuConstRegs[reg].UL[1]);
g_cpuFlushedConstReg |= (1<<reg);
if (reg == 0) DevCon.Warning("Flushing r0!");
}
}