mirror of https://github.com/PCSX2/pcsx2.git
pcsx2:
- removed some obsolete 'iCWstate' code. microVU: - implemented more rec first pass stuff for the lower instructions. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@903 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
12cba61302
commit
ebcedccf23
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@ -362,7 +362,7 @@ void _recMove128MtoRmOffset(u32 offset, u32 from);
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extern int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift);
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extern _mmxregs mmxregs[MMXREGS], s_saveMMXregs[MMXREGS];
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extern u16 x86FpuState, iCWstate;
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extern u16 x86FpuState;
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extern void iDumpRegisters(u32 startpc, u32 temp);
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@ -23,39 +23,6 @@
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#include "iR5900.h"
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#include "iFPU.h"
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//------------------------------------------------------------------
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// Misc...
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//------------------------------------------------------------------
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//static u32 _mxcsr = 0x7F80;
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//static u32 _mxcsrs;
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static u32 fpucw = 0x007f;
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static u32 fpucws = 0;
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void SaveCW(int type) {
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if (iCWstate & type) return;
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if (type == 2) {
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// SSE_STMXCSR((uptr)&_mxcsrs);
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// SSE_LDMXCSR((uptr)&_mxcsr);
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} else {
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FNSTCW( (uptr)&fpucws );
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FLDCW( (uptr)&fpucw );
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}
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iCWstate|= type;
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}
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void LoadCW() {
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if (iCWstate == 0) return;
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if (iCWstate & 2) {
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//SSE_LDMXCSR((uptr)&_mxcsrs);
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}
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if (iCWstate & 1) {
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FLDCW( (uptr)&fpucws );
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}
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iCWstate = 0;
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}
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//------------------------------------------------------------------
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namespace R5900 {
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namespace Dynarec {
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@ -22,9 +22,6 @@
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namespace R5900 {
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namespace Dynarec {
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void SaveCW();
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void LoadCW();
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namespace OpcodeImpl {
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namespace COP1
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{
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@ -39,40 +39,7 @@
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//set I&D flags. also impacts other aspects of DIV/R/SQRT correctness
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#define FPU_FLAGS_ID 1
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//------------------------------------------------------------------
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// Misc...
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//------------------------------------------------------------------
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//static u32 _mxcsr = 0x7F80;
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//static u32 _mxcsrs;
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/*static u32 fpucw = 0x007f;
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static u32 fpucws = 0;
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void SaveCW(int type) {
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if (iCWstate & type) return;
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if (type == 2) {
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// SSE_STMXCSR((uptr)&_mxcsrs);
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// SSE_LDMXCSR((uptr)&_mxcsr);
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} else {
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FNSTCW( (uptr)&fpucws );
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FLDCW( (uptr)&fpucw );
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}
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iCWstate|= type;
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}
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void LoadCW() {
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if (iCWstate == 0) return;
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if (iCWstate & 2) {
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//SSE_LDMXCSR((uptr)&_mxcsrs);
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}
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if (iCWstate & 1) {
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FLDCW( (uptr)&fpucws );
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}
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iCWstate = 0;
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}
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*/
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#ifdef FPU_RECOMPILE
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//------------------------------------------------------------------
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@ -117,10 +117,6 @@ void iFlushCall(int flushtype);
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void recBranchCall( void (*func)() );
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void recCall( void (*func)(), int delreg );
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// these are defined in iFPU.cpp
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void LoadCW();
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void SaveCW(int type);
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extern void recExecute(); // same as recCpu.Execute(), but faster (can be inline'd)
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namespace R5900{
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@ -44,9 +44,8 @@ namespace VU0micro
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{
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SuperVUReset(0);
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// these shouldn't be needed, but shouldn't hurt anything either.
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// this shouldn't be needed, but shouldn't hurt anything either.
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x86FpuState = FPU_STATE;
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iCWstate = 0;
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}
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static void recStep()
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@ -85,7 +85,6 @@ namespace VU1micro
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// these shouldn't be needed, but shouldn't hurt anything either.
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x86FpuState = FPU_STATE;
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iCWstate = 0;
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}
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static void recStep()
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@ -33,7 +33,7 @@ using namespace std;
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extern u32 g_psxConstRegs[32];
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u16 x86FpuState, iCWstate;
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u16 x86FpuState;
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u16 g_mmxAllocCounter = 0;
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// X86 caching
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@ -92,7 +92,7 @@ static u32 s_nHasDelay = 0;
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// save states for branches
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GPR_reg64 s_saveConstRegs[32];
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static u16 s_savex86FpuState, s_saveiCWstate;
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static u16 s_savex86FpuState;
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static u32 s_saveHasConstReg = 0, s_saveFlushedConstReg = 0, s_saveRegHasLive1 = 0, s_saveRegHasSignExt = 0;
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static EEINST* s_psaveInstInfo = NULL;
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@ -587,7 +587,6 @@ void recResetEE( void )
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recPtr = recMem;
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recStackPtr = recStack;
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x86FpuState = FPU_STATE;
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iCWstate = 0;
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branch = 0;
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SetCPUState(Config.sseMXCSR, Config.sseVUMXCSR);
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@ -987,7 +986,6 @@ void SetBranchImm( u32 imm )
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void SaveBranchState()
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{
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s_savex86FpuState = x86FpuState;
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s_saveiCWstate = iCWstate;
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s_savenBlockCycles = s_nBlockCycles;
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memcpy(s_saveConstRegs, g_cpuConstRegs, sizeof(g_cpuConstRegs));
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s_saveHasConstReg = g_cpuHasConstReg;
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@ -1004,7 +1002,6 @@ void SaveBranchState()
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void LoadBranchState()
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{
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x86FpuState = s_savex86FpuState;
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iCWstate = s_saveiCWstate;
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s_nBlockCycles = s_savenBlockCycles;
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memcpy(g_cpuConstRegs, s_saveConstRegs, sizeof(g_cpuConstRegs));
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@ -1036,8 +1033,6 @@ void iFlushCall(int flushtype)
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if( flushtype & FLUSH_CACHED_REGS )
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_flushConstRegs();
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LoadCW();
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if (x86FpuState==MMX_STATE) {
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if (cpucaps.has3DNOWInstructionExtensions) FEMMS();
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else EMMS();
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@ -1406,7 +1401,6 @@ void recRecompile( const u32 startpc )
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s_nBlockCycles = 0;
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pc = startpc;
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x86FpuState = FPU_STATE;
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iCWstate = 0;
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g_cpuHasConstReg = g_cpuFlushedConstReg = 1;
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g_cpuPrevRegHasLive1 = g_cpuRegHasLive1 = 0xffffffff;
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g_cpuPrevRegHasSignExt = g_cpuRegHasSignExt = 0;
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@ -230,8 +230,6 @@ int recSetMemLocation(int regs, int imm, int mmreg, int msize, int j32)
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if ( imm != 0 ) ADD32ItoR( ECX, imm );
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LoadCW();
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#ifdef _DEBUG
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//CALLFunc((uptr)testaddrs);
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#endif
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@ -40,6 +40,8 @@ struct microTempRegInfo {
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u8 VFreg[2]; // Index of the VF reg
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u8 VI; // Holds cycle info for Id
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u8 VIreg; // Index of the VI reg
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u8 q; // Holds cycle info for Q reg
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u8 p; // Holds cycle info for P reg
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};
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template<u32 pSize>
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@ -49,9 +51,9 @@ struct microAllocInfo {
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u8 branch; // 0 = No Branch, 1 = Branch, 2 = Conditional Branch, 3 = Jump (JALR/JR)
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u8 divFlag; // 0 = Transfer DS/IS flags normally, 1 = Clear DS/IS Flags, > 1 = set DS/IS flags to bit 2::1 of divFlag
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u8 divFlagTimer; // Used to ensure divFlag's contents are merged at the appropriate time.
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u32 curPC; // Current PC
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u8 maxStall; // Helps in computing stalls (stores the max amount of cycles to stall for the current opcodes)
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u32 cycles; // Cycles for current block
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u32 maxStall; // Helps in computing stalls (stores the max amount of cycles to stall for the current opcodes)
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u32 curPC; // Current PC
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u32 info[pSize]; // bit 00 = Lower Instruction is NOP
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// bit 01
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// bit 02
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@ -27,8 +27,8 @@
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// FMAC1 - Normal FMAC Opcodes
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//------------------------------------------------------------------
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#define aReg(x) mVUallocInfo.regs.VF[x]
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#define bReg(x) mVUallocInfo.regsTemp.VFreg[0] = x; mVUallocInfo.regsTemp.VF[0]
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#define aReg(x) mVUregs.VF[x]
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#define bReg(x) mVUregsTemp.VFreg[0] = x; mVUregsTemp.VF[0]
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#define aMax(x, y) ((x > y) ? x : y)
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#define analyzeReg1(reg) { \
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@ -117,10 +117,30 @@ microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) {
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} \
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}
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microVUt(void) mVUanalyzeFDIV(int Fs, int Fsf, int Ft, int Ftf) {
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#define analyzeQreg(x) { mVUregsTemp.q = x; mVUstall = aMax(mVUstall, mVUregs.q); }
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#define analyzePreg(x) { mVUregsTemp.p = x; mVUstall = aMax(mVUstall, ((mVUregs.p) ? (mVUregs.p - 1) : 0)); }
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microVUt(void) mVUanalyzeFDIV(int Fs, int Fsf, int Ft, int Ftf, u8 xCycles) {
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microVU* mVU = mVUx;
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analyzeReg5(Fs, Fsf);
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analyzeReg5(Ft, Ftf);
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analyzeQreg(xCycles);
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}
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//------------------------------------------------------------------
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// EFU - EFU Opcodes
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//------------------------------------------------------------------
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microVUt(void) mVUanalyzeEFU1(int Fs, int Fsf, u8 xCycles) {
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microVU* mVU = mVUx;
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analyzeReg5(Fs, Fsf);
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analyzePreg(xCycles);
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}
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microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) {
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microVU* mVU = mVUx;
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analyzeReg1(Fs);
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analyzePreg(xCycles);
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}
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#endif //PCSX2_MICROVU
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@ -50,8 +50,10 @@ microVUt(void) mVUsetCycles() {
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microVU* mVU = mVUx;
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incCycles(mVUstall);
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mVUregs.VF[mVUregsTemp.VFreg[0]].reg = mVUregsTemp.VF[0].reg;
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mVUregs.VF[mVUregsTemp.VFreg[1]].reg = mVUregsTemp.VF[1].reg;
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mVUregs.VF[mVUregsTemp.VFreg[1]].reg =(mVUregsTemp.VFreg[0] == mVUregsTemp.VFreg[1]) ? (aMax(mVUregsTemp.VF[0].reg, mVUregsTemp.VF[1].reg)) : (mVUregsTemp.VF[1].reg);
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mVUregs.VI[mVUregsTemp.VIreg] = mVUregsTemp.VI;
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mVUregs.q = mVUregsTemp.q;
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mVUregs.p = mVUregsTemp.p;
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}
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microVUx(void) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState, u8* x86ptrStart) {
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@ -41,7 +41,7 @@
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microVUf(void) mVU_DIV() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeFDIV<vuIndex>(_Fs_, _Fsf_, _Ft_, _Ftf_); }
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if (!recPass) { mVUanalyzeFDIV<vuIndex>(_Fs_, _Fsf_, _Ft_, _Ftf_, 7); }
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else {
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u8 *ajmp, *bjmp, *cjmp, *djmp;
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getReg5(xmmFs, _Fs_, _Fsf_);
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@ -76,7 +76,7 @@ microVUf(void) mVU_DIV() {
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microVUf(void) mVU_SQRT() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeFDIV<vuIndex>(0, 0, _Ft_, _Ftf_); }
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if (!recPass) { mVUanalyzeFDIV<vuIndex>(0, 0, _Ft_, _Ftf_, 7); }
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else {
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u8 *ajmp;
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getReg5(xmmFt, _Ft_, _Ftf_);
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@ -93,7 +93,7 @@ microVUf(void) mVU_SQRT() {
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microVUf(void) mVU_RSQRT() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeFDIV<vuIndex>(_Fs_, _Fsf_, _Ft_, _Ftf_); }
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if (!recPass) { mVUanalyzeFDIV<vuIndex>(_Fs_, _Fsf_, _Ft_, _Ftf_, 13); }
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else {
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u8 *ajmp, *bjmp, *cjmp, *djmp;
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getReg5(xmmFs, _Fs_, _Fsf_);
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@ -158,7 +158,7 @@ microVUt(void) mVU_EATAN_() {
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microVUf(void) mVU_EATAN() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeEFU1<vuIndex>(_Fs_, _Fsf_, 54); }
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else {
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getReg5(xmmFs, _Fs_, _Fsf_);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
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@ -174,7 +174,7 @@ microVUf(void) mVU_EATAN() {
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microVUf(void) mVU_EATANxy() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeEFU2<vuIndex>(_Fs_, 54); }
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else {
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getReg6(xmmFt, _Fs_);
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SSE2_PSHUFD_XMM_to_XMM(xmmFs, xmmFt, 0x01);
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@ -191,7 +191,7 @@ microVUf(void) mVU_EATANxy() {
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microVUf(void) mVU_EATANxz() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeEFU2<vuIndex>(_Fs_, 54); }
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else {
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getReg6(xmmFt, _Fs_);
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SSE2_PSHUFD_XMM_to_XMM(xmmFs, xmmFt, 0x02);
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@ -215,7 +215,7 @@ microVUf(void) mVU_EATANxz() {
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microVUf(void) mVU_EEXP() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeEFU1<vuIndex>(_Fs_, _Fsf_, 44); }
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else {
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getReg5(xmmFs, _Fs_, _Fsf_);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
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@ -263,7 +263,7 @@ microVUt(void) mVU_sumXYZ() {
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microVUf(void) mVU_ELENG() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeEFU2<vuIndex>(_Fs_, 18); }
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else {
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getReg6(xmmFs, _Fs_);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
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@ -275,7 +275,7 @@ microVUf(void) mVU_ELENG() {
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microVUf(void) mVU_ERCPR() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeEFU1<vuIndex>(_Fs_, _Fsf_, 12); }
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else {
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getReg5(xmmFs, _Fs_, _Fsf_);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
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@ -289,7 +289,7 @@ microVUf(void) mVU_ERCPR() {
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microVUf(void) mVU_ERLENG() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeEFU2<vuIndex>(_Fs_, 24); }
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else {
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getReg6(xmmFs, _Fs_);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
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@ -304,7 +304,7 @@ microVUf(void) mVU_ERLENG() {
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microVUf(void) mVU_ERSADD() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeEFU2<vuIndex>(_Fs_, 18); }
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else {
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getReg6(xmmFs, _Fs_);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
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@ -319,7 +319,7 @@ microVUf(void) mVU_ERSADD() {
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microVUf(void) mVU_ERSQRT() {
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microVU* mVU = mVUx;
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if (!recPass) {}
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if (!recPass) { mVUanalyzeEFU1<vuIndex>(_Fs_, _Fsf_, 18); }
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else {
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getReg5(xmmFs, _Fs_, _Fsf_);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -333,7 +333,7 @@ microVUf(void) mVU_ERSQRT() {
|
|||
|
||||
microVUf(void) mVU_ESADD() {
|
||||
microVU* mVU = mVUx;
|
||||
if (!recPass) {}
|
||||
if (!recPass) { mVUanalyzeEFU2<vuIndex>(_Fs_, 11); }
|
||||
else {
|
||||
getReg6(xmmFs, _Fs_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -351,7 +351,7 @@ microVUf(void) mVU_ESADD() {
|
|||
|
||||
microVUf(void) mVU_ESIN() {
|
||||
microVU* mVU = mVUx;
|
||||
if (!recPass) {}
|
||||
if (!recPass) { mVUanalyzeEFU2<vuIndex>(_Fs_, 29); }
|
||||
else {
|
||||
getReg5(xmmFs, _Fs_, _Fsf_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -377,7 +377,7 @@ microVUf(void) mVU_ESIN() {
|
|||
|
||||
microVUf(void) mVU_ESQRT() {
|
||||
microVU* mVU = mVUx;
|
||||
if (!recPass) {}
|
||||
if (!recPass) { mVUanalyzeEFU1<vuIndex>(_Fs_, _Fsf_, 12); }
|
||||
else {
|
||||
getReg5(xmmFs, _Fs_, _Fsf_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -388,7 +388,7 @@ microVUf(void) mVU_ESQRT() {
|
|||
|
||||
microVUf(void) mVU_ESUM() {
|
||||
microVU* mVU = mVUx;
|
||||
if (!recPass) {}
|
||||
if (!recPass) { mVUanalyzeEFU2<vuIndex>(_Fs_, 12); }
|
||||
else {
|
||||
getReg6(xmmFs, _Fs_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
|
|||
|
|
@ -99,7 +99,7 @@ declareAllVariables
|
|||
#define _Mbit_ (1<<29)
|
||||
#define _Dbit_ (1<<28)
|
||||
#define _Tbit_ (1<<27)
|
||||
#define _MDTbit_ ( _Mbit_ | _Dbit_ | _Tbit_ )
|
||||
#define _MDTbit_ 0 //( _Mbit_ | _Dbit_ | _Tbit_ ) // ToDo: Implement this stuff...
|
||||
|
||||
#define getVUmem(x) (((vuIndex == 1) ? (x & 0x3ff) : ((x >= 0x400) ? (x & 0x43f) : (x & 0xff))) * 16)
|
||||
#define offsetSS ((_X) ? (0) : ((_Y) ? (4) : ((_Z) ? 8: 12)))
|
||||
|
|
|
|||
Loading…
Reference in New Issue