mirror of https://github.com/PCSX2/pcsx2.git
ee-fpu: upgrade the FPU to 3.0
properly return reserved register Fix FCR test :)
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@ -223,8 +223,12 @@ void C_LT() {
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}
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}
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void CFC1() {
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void CFC1() {
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if ( !_Rt_ || ( (_Fs_ != 0) && (_Fs_ != 31) ) ) return;
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if ( !_Rt_ ) return;
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)fpuRegs.fprc[_Fs_]; // force sign extension to 64 bit
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if (_Fs_ >= 16)
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)fpuRegs.fprc[31]; // force sign extension to 64 bit
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else
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)fpuRegs.fprc[0]; // force sign extension to 64 bit
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}
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}
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void CTC1() {
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void CTC1() {
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@ -13,7 +13,7 @@
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* If not, see <http://www.gnu.org/licenses/>.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#include "PrecompiledHeader.h"
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "Common.h"
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@ -72,7 +72,7 @@ void cpuReset()
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cpuRegs.CP0.n.Config = 0x440;
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cpuRegs.CP0.n.Config = 0x440;
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cpuRegs.CP0.n.Status.val= 0x70400004; //0x10900000 <-- wrong; // COP0 enabled | BEV = 1 | TS = 1
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cpuRegs.CP0.n.Status.val= 0x70400004; //0x10900000 <-- wrong; // COP0 enabled | BEV = 1 | TS = 1
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cpuRegs.CP0.n.PRid = 0x00002e20; // PRevID = Revision ID, same as R5900
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cpuRegs.CP0.n.PRid = 0x00002e20; // PRevID = Revision ID, same as R5900
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fpuRegs.fprc[0] = 0x00002e00; // fpu Revision..
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fpuRegs.fprc[0] = 0x00002e30; // fpu Revision..
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fpuRegs.fprc[31] = 0x01000001; // fpu Status/Control
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fpuRegs.fprc[31] = 0x01000001; // fpu Status/Control
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g_nextEventCycle = cpuRegs.cycle + 4;
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g_nextEventCycle = cpuRegs.cycle + 4;
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@ -82,7 +82,7 @@ void cpuReset()
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hwReset();
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hwReset();
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rcntInit();
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rcntInit();
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psxReset();
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psxReset();
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extern void Deci2Reset(); // lazy, no good header for it yet.
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extern void Deci2Reset(); // lazy, no good header for it yet.
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Deci2Reset();
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Deci2Reset();
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@ -114,15 +114,18 @@ static const __aligned16 u32 s_pos[4] = { 0x7fffffff, 0xffffffff, 0xffffffff, 0x
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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void recCFC1(void)
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void recCFC1(void)
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{
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{
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if ( !_Rt_ || ( (_Fs_ != 0) && (_Fs_ != 31) ) ) return;
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if ( !_Rt_ ) return;
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EE::Profiler.EmitOp(eeOpcode::CFC1);
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EE::Profiler.EmitOp(eeOpcode::CFC1);
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_eeOnWriteReg(_Rt_, 1);
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_eeOnWriteReg(_Rt_, 1);
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xMOV(eax, ptr[&fpuRegs.fprc[ _Fs_ ] ]);
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if (_Fs_ >= 16)
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xMOV(eax, ptr[&fpuRegs.fprc[31] ]);
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else
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xMOV(eax, ptr[&fpuRegs.fprc[0] ]);
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_deleteEEreg(_Rt_, 0);
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_deleteEEreg(_Rt_, 0);
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if (_Fs_ == 31)
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if (_Fs_ >= 16)
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{
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{
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xAND(eax, 0x0083c078); //remove always-zero bits
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xAND(eax, 0x0083c078); //remove always-zero bits
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xOR(eax, 0x01000001); //set always-one bits
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xOR(eax, 0x01000001); //set always-one bits
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@ -48,6 +48,8 @@ sub help {
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EnableVU1=disabled : Use VU1 interpreter
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EnableVU1=disabled : Use VU1 interpreter
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FPU.Roundmode=3 : EE FPU round mode
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FPU.Roundmode=3 : EE FPU round mode
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VU.Roundmode=3 : VU round mode
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VU.Roundmode=3 : VU round mode
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fpuExtraOverflow=enabled : Full EE FPU
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fpuFullMode=enabled : Full EE FPU
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EOS
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EOS
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print $msg;
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print $msg;
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@ -152,7 +154,6 @@ if ($o_regression or $o_bad) {
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$blacklist{"arithmetic"} = 1;
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$blacklist{"arithmetic"} = 1;
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$blacklist{"branchdelay"} = 1;
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$blacklist{"branchdelay"} = 1;
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$blacklist{"compare"} = 1;
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$blacklist{"compare"} = 1;
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$blacklist{"fcr"} = 1;
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$blacklist{"muldiv"} = 1;
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$blacklist{"muldiv"} = 1;
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$blacklist{"sqrt"} = 1;
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$blacklist{"sqrt"} = 1;
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# IOP
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# IOP
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