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x86emitter: sed/32orLess/64orLess/

This commit is contained in:
Gregory Hainaut 2016-01-17 00:29:19 +01:00
parent 395d43fd9c
commit e50e9a5e65
12 changed files with 35 additions and 35 deletions
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8
common/include/x86emitter/implement/group1.h
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@ -43,7 +43,7 @@ struct xImpl_Group1
void operator()( const xIndirectVoid& to, const xRegisterInt& from ) const; void operator()( const xIndirectVoid& to, const xRegisterInt& from ) const;
void operator()( const xRegisterInt& to, const xIndirectVoid& from ) const; void operator()( const xRegisterInt& to, const xIndirectVoid& from ) const;
void operator()( const xRegisterInt& to, int imm ) const; void operator()( const xRegisterInt& to, int imm ) const;
void operator()( const xIndirect32orLess& to, int imm ) const; void operator()( const xIndirect64orLess& to, int imm ) const;
#if 0 #if 0
// ------------------------------------------------------------------------ // ------------------------------------------------------------------------
@ -95,7 +95,7 @@ struct xImpl_G1Logic
void operator()( const xRegisterInt& to, const xIndirectVoid& from ) const; void operator()( const xRegisterInt& to, const xIndirectVoid& from ) const;
void operator()( const xRegisterInt& to, int imm ) const; void operator()( const xRegisterInt& to, int imm ) const;
void operator()( const xIndirect32orLess& to, int imm ) const; void operator()( const xIndirect64orLess& to, int imm ) const;
xImplSimd_DestRegSSE PS; // packed single precision xImplSimd_DestRegSSE PS; // packed single precision
xImplSimd_DestRegSSE PD; // packed double precision xImplSimd_DestRegSSE PD; // packed double precision
@ -114,7 +114,7 @@ struct xImpl_G1Arith
void operator()( const xRegisterInt& to, const xIndirectVoid& from ) const; void operator()( const xRegisterInt& to, const xIndirectVoid& from ) const;
void operator()( const xRegisterInt& to, int imm ) const; void operator()( const xRegisterInt& to, int imm ) const;
void operator()( const xIndirect32orLess& to, int imm ) const; void operator()( const xIndirect64orLess& to, int imm ) const;
xImplSimd_DestRegSSE PS; // packed single precision xImplSimd_DestRegSSE PS; // packed single precision
xImplSimd_DestRegSSE PD; // packed double precision xImplSimd_DestRegSSE PD; // packed double precision
@ -131,7 +131,7 @@ struct xImpl_G1Compare
void operator()( const xRegisterInt& to, const xIndirectVoid& from ) const; void operator()( const xRegisterInt& to, const xIndirectVoid& from ) const;
void operator()( const xRegisterInt& to, int imm ) const; void operator()( const xRegisterInt& to, int imm ) const;
void operator()( const xIndirect32orLess& to, int imm ) const; void operator()( const xIndirect64orLess& to, int imm ) const;
xImplSimd_DestSSE_CmpImm PS; xImplSimd_DestSSE_CmpImm PS;
xImplSimd_DestSSE_CmpImm PD; xImplSimd_DestSSE_CmpImm PD;

4
common/include/x86emitter/implement/group2.h
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@ -41,9 +41,9 @@ struct xImpl_Group2
G2Type InstType; G2Type InstType;
void operator()( const xRegisterInt& to, const xRegisterCL& from ) const; void operator()( const xRegisterInt& to, const xRegisterCL& from ) const;
void operator()( const xIndirect32orLess& to, const xRegisterCL& from ) const; void operator()( const xIndirect64orLess& to, const xRegisterCL& from ) const;
void operator()( const xRegisterInt& to, u8 imm ) const; void operator()( const xRegisterInt& to, u8 imm ) const;
void operator()( const xIndirect32orLess& to, u8 imm ) const; void operator()( const xIndirect64orLess& to, u8 imm ) const;
#if 0 #if 0
// ------------------------------------------------------------------------ // ------------------------------------------------------------------------

8
common/include/x86emitter/implement/group3.h
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@ -35,7 +35,7 @@ struct xImpl_Group3
G3Type InstType; G3Type InstType;
void operator()( const xRegisterInt& from ) const; void operator()( const xRegisterInt& from ) const;
void operator()( const xIndirect32orLess& from ) const; void operator()( const xIndirect64orLess& from ) const;
#if 0 #if 0
template< typename T > template< typename T >
@ -57,7 +57,7 @@ struct xImpl_MulDivBase
u16 OpcodeSSE; u16 OpcodeSSE;
void operator()( const xRegisterInt& from ) const; void operator()( const xRegisterInt& from ) const;
void operator()( const xIndirect32orLess& from ) const; void operator()( const xIndirect64orLess& from ) const;
const xImplSimd_DestRegSSE PS; const xImplSimd_DestRegSSE PS;
const xImplSimd_DestRegSSE PD; const xImplSimd_DestRegSSE PD;
@ -71,7 +71,7 @@ struct xImpl_MulDivBase
struct xImpl_iDiv struct xImpl_iDiv
{ {
void operator()( const xRegisterInt& from ) const; void operator()( const xRegisterInt& from ) const;
void operator()( const xIndirect32orLess& from ) const; void operator()( const xIndirect64orLess& from ) const;
const xImplSimd_DestRegSSE PS; const xImplSimd_DestRegSSE PS;
const xImplSimd_DestRegSSE PD; const xImplSimd_DestRegSSE PD;
@ -86,7 +86,7 @@ struct xImpl_iDiv
struct xImpl_iMul struct xImpl_iMul
{ {
void operator()( const xRegisterInt& from ) const; void operator()( const xRegisterInt& from ) const;
void operator()( const xIndirect32orLess& from ) const; void operator()( const xIndirect64orLess& from ) const;
// The following iMul-specific forms are valid for 16 and 32 bit register operands only! // The following iMul-specific forms are valid for 16 and 32 bit register operands only!

2
common/include/x86emitter/implement/incdec.h
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@ -28,7 +28,7 @@ struct xImpl_IncDec
bool isDec; bool isDec;
void operator()( const xRegisterInt& to ) const; void operator()( const xRegisterInt& to ) const;
void operator()( const xIndirect32orLess& to ) const; void operator()( const xIndirect64orLess& to ) const;
}; };
} // End namespace x86Emitter } // End namespace x86Emitter

2
common/include/x86emitter/implement/jmpcall.h
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@ -44,7 +44,7 @@ struct xImpl_JmpCall
bool isJmp; bool isJmp;
void operator()( const xRegisterInt& absreg ) const; void operator()( const xRegisterInt& absreg ) const;
void operator()( const xIndirect32orLess& src ) const; void operator()( const xIndirect64orLess& src ) const;
// Special form for calling functions. This form automatically resolves the // Special form for calling functions. This form automatically resolves the
// correct displacement based on the size of the instruction being generated. // correct displacement based on the size of the instruction being generated.

2
common/include/x86emitter/implement/movs.h
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@ -32,7 +32,7 @@ struct xImpl_Mov
void operator()( const xRegisterInt& to, const xRegisterInt& from ) const; void operator()( const xRegisterInt& to, const xRegisterInt& from ) const;
void operator()( const xIndirectVoid& dest, const xRegisterInt& from ) const; void operator()( const xIndirectVoid& dest, const xRegisterInt& from ) const;
void operator()( const xRegisterInt& to, const xIndirectVoid& src ) const; void operator()( const xRegisterInt& to, const xIndirectVoid& src ) const;
void operator()( const xIndirect32orLess& dest, int imm ) const; void operator()( const xIndirect64orLess& dest, int imm ) const;
void operator()( const xRegisterInt& to, int imm, bool preserve_flags=false ) const; void operator()( const xRegisterInt& to, int imm, bool preserve_flags=false ) const;
#if 0 #if 0

2
common/include/x86emitter/implement/test.h
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@ -26,7 +26,7 @@ namespace x86Emitter {
struct xImpl_Test struct xImpl_Test
{ {
void operator()( const xRegisterInt& to, const xRegisterInt& from ) const; void operator()( const xRegisterInt& to, const xRegisterInt& from ) const;
void operator()( const xIndirect32orLess& dest, int imm ) const; void operator()( const xIndirect64orLess& dest, int imm ) const;
void operator()( const xRegisterInt& to, int imm ) const; void operator()( const xRegisterInt& to, int imm ) const;
}; };

18
common/include/x86emitter/x86types.h
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@ -831,9 +831,9 @@ template< typename T > void xWrite( T val );
typedef xIndirect<u8> xIndirect8; typedef xIndirect<u8> xIndirect8;
// -------------------------------------------------------------------------------------- // --------------------------------------------------------------------------------------
// xIndirect32orLess - base class 64, 32, 16, and 8 bit operand types // xIndirect64orLess - base class 64, 32, 16, and 8 bit operand types
// -------------------------------------------------------------------------------------- // --------------------------------------------------------------------------------------
class xIndirect32orLess : public xIndirectVoid class xIndirect64orLess : public xIndirectVoid
{ {
typedef xIndirectVoid _parent; typedef xIndirectVoid _parent;
@ -841,18 +841,18 @@ template< typename T > void xWrite( T val );
uint m_OpSize; uint m_OpSize;
public: public:
xIndirect32orLess( const xIndirect8& src ) : _parent( src ) { m_OpSize = src.GetOperandSize(); } xIndirect64orLess( const xIndirect8& src ) : _parent( src ) { m_OpSize = src.GetOperandSize(); }
xIndirect32orLess( const xIndirect16& src ) : _parent( src ) { m_OpSize = src.GetOperandSize(); } xIndirect64orLess( const xIndirect16& src ) : _parent( src ) { m_OpSize = src.GetOperandSize(); }
xIndirect32orLess( const xIndirect32& src ) : _parent( src ) { m_OpSize = src.GetOperandSize(); } xIndirect64orLess( const xIndirect32& src ) : _parent( src ) { m_OpSize = src.GetOperandSize(); }
xIndirect32orLess( const xIndirect64& src ) : _parent( src ) { m_OpSize = src.GetOperandSize(); } xIndirect64orLess( const xIndirect64& src ) : _parent( src ) { m_OpSize = src.GetOperandSize(); }
uint GetOperandSize() const { return m_OpSize; } uint GetOperandSize() const { return m_OpSize; }
protected: protected:
//xIndirect32orLess( const xAddressVoid& src ) : _parent( src ) {} //xIndirect64orLess( const xAddressVoid& src ) : _parent( src ) {}
explicit xIndirect32orLess( s32 disp ) : _parent( disp ) {} explicit xIndirect64orLess( s32 disp ) : _parent( disp ) {}
xIndirect32orLess( xAddressReg base, xAddressReg index, int scale=0, s32 displacement=0 ) : xIndirect64orLess( xAddressReg base, xAddressReg index, int scale=0, s32 displacement=0 ) :
_parent( base, index, scale, displacement ) {} _parent( base, index, scale, displacement ) {}
}; };

16
common/src/x86emitter/groups.cpp
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@ -41,7 +41,7 @@ namespace x86Emitter {
// Note on "[Indirect],Imm" forms : use int as the source operand since it's "reasonably inert" from a // Note on "[Indirect],Imm" forms : use int as the source operand since it's "reasonably inert" from a
// compiler perspective. (using uint tends to make the compiler try and fail to match signed immediates // compiler perspective. (using uint tends to make the compiler try and fail to match signed immediates
// with one of the other overloads). // with one of the other overloads).
static void _g1_IndirectImm( G1Type InstType, const xIndirect32orLess& sibdest, int imm ) static void _g1_IndirectImm( G1Type InstType, const xIndirect64orLess& sibdest, int imm )
{ {
if( sibdest.Is8BitOp() ) if( sibdest.Is8BitOp() )
{ {
@ -110,7 +110,7 @@ static void _g1_EmitOp( G1Type InstType, const xRegisterInt& to, int imm )
void g1type::operator()( const xIndirectVoid& to, const xRegisterInt& from ) const { _g1_EmitOp( insttype, to, from ); } \ void g1type::operator()( const xIndirectVoid& to, const xRegisterInt& from ) const { _g1_EmitOp( insttype, to, from ); } \
void g1type::operator()( const xRegisterInt& to, const xIndirectVoid& from ) const { _g1_EmitOp( insttype, to, from ); } \ void g1type::operator()( const xRegisterInt& to, const xIndirectVoid& from ) const { _g1_EmitOp( insttype, to, from ); } \
void g1type::operator()( const xRegisterInt& to, int imm ) const { _g1_EmitOp( insttype, to, imm ); } \ void g1type::operator()( const xRegisterInt& to, int imm ) const { _g1_EmitOp( insttype, to, imm ); } \
void g1type::operator()( const xIndirect32orLess& sibdest, int imm ) const { _g1_IndirectImm( insttype, sibdest, imm ); } void g1type::operator()( const xIndirect64orLess& sibdest, int imm ) const { _g1_IndirectImm( insttype, sibdest, imm ); }
ImplementGroup1( xImpl_Group1, InstType ) ImplementGroup1( xImpl_Group1, InstType )
ImplementGroup1( xImpl_G1Logic, InstType ) ImplementGroup1( xImpl_G1Logic, InstType )
@ -158,14 +158,14 @@ void xImpl_Group2::operator()(const xRegisterInt& to, u8 imm ) const
} }
} }
void xImpl_Group2::operator()( const xIndirect32orLess& sibdest, const xRegisterCL& /* from */ ) const void xImpl_Group2::operator()( const xIndirect64orLess& sibdest, const xRegisterCL& /* from */ ) const
{ {
sibdest.prefix16(); sibdest.prefix16();
xWrite8( sibdest.Is8BitOp() ? 0xd2 : 0xd3 ); xWrite8( sibdest.Is8BitOp() ? 0xd2 : 0xd3 );
EmitSibMagic( InstType, sibdest ); EmitSibMagic( InstType, sibdest );
} }
void xImpl_Group2::operator()( const xIndirect32orLess& sibdest, u8 imm ) const void xImpl_Group2::operator()( const xIndirect64orLess& sibdest, u8 imm ) const
{ {
if( imm == 0 ) return; if( imm == 0 ) return;
@ -204,7 +204,7 @@ static void _g3_EmitOp( G3Type InstType, const xRegisterInt& from )
EmitSibMagic( InstType, from ); EmitSibMagic( InstType, from );
} }
static void _g3_EmitOp( G3Type InstType, const xIndirect32orLess& from ) static void _g3_EmitOp( G3Type InstType, const xIndirect64orLess& from )
{ {
from.prefix16(); from.prefix16();
xWrite8( from.Is8BitOp() ? 0xf6 : 0xf7 ); xWrite8( from.Is8BitOp() ? 0xf6 : 0xf7 );
@ -212,10 +212,10 @@ static void _g3_EmitOp( G3Type InstType, const xIndirect32orLess& from )
} }
void xImpl_Group3::operator()( const xRegisterInt& from ) const { _g3_EmitOp( InstType, from ); } void xImpl_Group3::operator()( const xRegisterInt& from ) const { _g3_EmitOp( InstType, from ); }
void xImpl_Group3::operator()( const xIndirect32orLess& from ) const { _g3_EmitOp( InstType, from ); } void xImpl_Group3::operator()( const xIndirect64orLess& from ) const { _g3_EmitOp( InstType, from ); }
void xImpl_iDiv::operator()( const xRegisterInt& from ) const { _g3_EmitOp( G3Type_iDIV, from ); } void xImpl_iDiv::operator()( const xRegisterInt& from ) const { _g3_EmitOp( G3Type_iDIV, from ); }
void xImpl_iDiv::operator()( const xIndirect32orLess& from ) const { _g3_EmitOp( G3Type_iDIV, from ); } void xImpl_iDiv::operator()( const xIndirect64orLess& from ) const { _g3_EmitOp( G3Type_iDIV, from ); }
template< typename SrcType > template< typename SrcType >
static void _imul_ImmStyle( const xRegisterInt& param1, const SrcType& param2, int imm ) static void _imul_ImmStyle( const xRegisterInt& param1, const SrcType& param2, int imm )
@ -235,7 +235,7 @@ static void _imul_ImmStyle( const xRegisterInt& param1, const SrcType& param2, i
} }
void xImpl_iMul::operator()( const xRegisterInt& from ) const { _g3_EmitOp( G3Type_iMUL, from ); } void xImpl_iMul::operator()( const xRegisterInt& from ) const { _g3_EmitOp( G3Type_iMUL, from ); }
void xImpl_iMul::operator()( const xIndirect32orLess& from ) const { _g3_EmitOp( G3Type_iMUL, from ); } void xImpl_iMul::operator()( const xIndirect64orLess& from ) const { _g3_EmitOp( G3Type_iMUL, from ); }
void xImpl_iMul::operator()( const xRegister32& to, const xRegister32& from ) const { xOpWrite0F( 0xaf, to, from ); } void xImpl_iMul::operator()( const xRegister32& to, const xRegister32& from ) const { xOpWrite0F( 0xaf, to, from ); }
void xImpl_iMul::operator()( const xRegister32& to, const xIndirectVoid& src ) const { xOpWrite0F( 0xaf, to, src ); } void xImpl_iMul::operator()( const xRegister32& to, const xIndirectVoid& src ) const { xOpWrite0F( 0xaf, to, src ); }

2
common/src/x86emitter/jmp.cpp
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@ -34,7 +34,7 @@
namespace x86Emitter { namespace x86Emitter {
void xImpl_JmpCall::operator()( const xRegisterInt& absreg ) const { xOpWrite( 0, 0xff, isJmp ? 4 : 2, absreg ); } void xImpl_JmpCall::operator()( const xRegisterInt& absreg ) const { xOpWrite( 0, 0xff, isJmp ? 4 : 2, absreg ); }
void xImpl_JmpCall::operator()( const xIndirect32orLess& src ) const { xOpWrite( 0, 0xff, isJmp ? 4 : 2, src ); } void xImpl_JmpCall::operator()( const xIndirect64orLess& src ) const { xOpWrite( 0, 0xff, isJmp ? 4 : 2, src ); }
const xImpl_JmpCall xJMP = { true }; const xImpl_JmpCall xJMP = { true };
const xImpl_JmpCall xCALL = { false }; const xImpl_JmpCall xCALL = { false };

2
common/src/x86emitter/movs.cpp
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@ -89,7 +89,7 @@ void xImpl_Mov::operator()( const xRegisterInt& to, const xIndirectVoid& src ) c
} }
} }
void xImpl_Mov::operator()( const xIndirect32orLess& dest, int imm ) const void xImpl_Mov::operator()( const xIndirect64orLess& dest, int imm ) const
{ {
dest.prefix16(); dest.prefix16();
xWrite8( dest.Is8BitOp() ? 0xc6 : 0xc7 ); xWrite8( dest.Is8BitOp() ? 0xc6 : 0xc7 );

4
common/src/x86emitter/x86emitter.cpp
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@ -934,7 +934,7 @@ void xImpl_Test::operator()( const xRegisterInt& to, const xRegisterInt& from )
EmitSibMagic( from, to ); EmitSibMagic( from, to );
} }
void xImpl_Test::operator()( const xIndirect32orLess& dest, int imm ) const void xImpl_Test::operator()( const xIndirect64orLess& dest, int imm ) const
{ {
dest.prefix16(); dest.prefix16();
xWrite8( dest.Is8BitOp() ? 0xf6 : 0xf7 ); xWrite8( dest.Is8BitOp() ? 0xf6 : 0xf7 );
@ -979,7 +979,7 @@ void xImpl_IncDec::operator()( const xRegisterInt& to ) const
} }
} }
void xImpl_IncDec::operator()( const xIndirect32orLess& to ) const void xImpl_IncDec::operator()( const xIndirect64orLess& to ) const
{ {
to.prefix16(); to.prefix16();
xWrite8( to.Is8BitOp() ? 0xfe : 0xff ); xWrite8( to.Is8BitOp() ? 0xfe : 0xff );