mirror of https://github.com/PCSX2/pcsx2.git
GregMiscellaneous: zzogl-pg:
* Fix previous commit :) git-svn-id: http://pcsx2.googlecode.com/svn/branches/GregMiscellaneous@3921 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -649,14 +649,9 @@ static const __aligned16 int s_clut16mask[8] = { 0xffff0000, 0xffff0000, 0xffff0
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0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff
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};
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template<bool CSA_0_15>
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__forceinline void WriteCLUT_T16_I4_CSM1_core_sse2(u32* vm, u32* clut)
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template<bool CSA_0_15, bool HIGH_16BITS_VM>
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void __fastcall WriteCLUT_T16_I4_CSM1_core_sse2(u32* vm, u32* clut)
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{
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// CSA 0-15
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// Replace lower 16 bits of clut with lower 16 bits of vm
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// CSA 16-31
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// Replace higher 16 bits of clut with higher 16 bits of vm
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__m128i vm_0;
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__m128i vm_1;
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__m128i vm_2;
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@ -668,19 +663,47 @@ __forceinline void WriteCLUT_T16_I4_CSM1_core_sse2(u32* vm, u32* clut)
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__m128i clut_mask = _mm_load_si128((__m128i*)s_clut_16bits_mask);
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// load new data & remove useless part
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if(CSA_0_15) {
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// Note:
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// !HIGH_16BITS_VM
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// CSA in 0-15 -> Replace lower 16 bits of clut0 with lower 16 bits of vm
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// CSA in 16-31 -> Replace higher 16 bits of clut0 with lower 16 bits of vm
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// HIGH_16BITS_VM
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// CSA in 0-15 -> Replace lower 16 bits of clut0 with higher 16 bits of vm
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// CSA in 16-31 -> Replace higher 16 bits of clut0 with higher 16 bits of vm
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if(HIGH_16BITS_VM && CSA_0_15) {
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// move high to low
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vm_0 = _mm_load_si128((__m128i*)vm); // 9 8 1 0
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vm_1 = _mm_load_si128((__m128i*)vm+1); // 11 10 3 2
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vm_2 = _mm_load_si128((__m128i*)vm+2); // 13 12 5 4
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vm_3 = _mm_load_si128((__m128i*)vm+3); // 15 14 7 6
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vm_0 = _mm_srli_epi32(vm_0, 16);
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vm_1 = _mm_srli_epi32(vm_1, 16);
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vm_2 = _mm_srli_epi32(vm_2, 16);
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vm_3 = _mm_srli_epi32(vm_3, 16);
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} else if(HIGH_16BITS_VM && !CSA_0_15) {
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// Remove lower 16 bits
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vm_0 = _mm_andnot_si128(clut_mask, _mm_load_si128((__m128i*)vm)); // 9 8 1 0
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vm_1 = _mm_andnot_si128(clut_mask, _mm_load_si128((__m128i*)vm+1)); // 11 10 3 2
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vm_2 = _mm_andnot_si128(clut_mask, _mm_load_si128((__m128i*)vm+2)); // 13 12 5 4
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vm_3 = _mm_andnot_si128(clut_mask, _mm_load_si128((__m128i*)vm+3)); // 15 14 7 6
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} else if(!HIGH_16BITS_VM && CSA_0_15) {
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// Remove higher 16 bits
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vm_0 = _mm_and_si128(clut_mask, _mm_load_si128((__m128i*)vm)); // 9 8 1 0
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vm_1 = _mm_and_si128(clut_mask, _mm_load_si128((__m128i*)vm+1)); // 11 10 3 2
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vm_2 = _mm_and_si128(clut_mask, _mm_load_si128((__m128i*)vm+2)); // 13 12 5 4
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vm_3 = _mm_and_si128(clut_mask, _mm_load_si128((__m128i*)vm+3)); // 15 14 7 6
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} else {
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// Remove lower 16 bits
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vm_0 = _mm_andnot_si128(clut_mask, _mm_load_si128((__m128i*)vm));
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vm_1 = _mm_andnot_si128(clut_mask, _mm_load_si128((__m128i*)vm+1));
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vm_2 = _mm_andnot_si128(clut_mask, _mm_load_si128((__m128i*)vm+2));
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vm_3 = _mm_andnot_si128(clut_mask, _mm_load_si128((__m128i*)vm+3));
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} else if(!HIGH_16BITS_VM && !CSA_0_15) {
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// move low to high
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vm_0 = _mm_load_si128((__m128i*)vm); // 9 8 1 0
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vm_1 = _mm_load_si128((__m128i*)vm+1); // 11 10 3 2
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vm_2 = _mm_load_si128((__m128i*)vm+2); // 13 12 5 4
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vm_3 = _mm_load_si128((__m128i*)vm+3); // 15 14 7 6
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vm_0 = _mm_slli_epi32(vm_0, 16);
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vm_1 = _mm_slli_epi32(vm_1, 16);
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vm_2 = _mm_slli_epi32(vm_2, 16);
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vm_3 = _mm_slli_epi32(vm_3, 16);
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}
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// Unsizzle the data
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@ -719,9 +742,11 @@ __forceinline void WriteCLUT_T16_I4_CSM1_core_sse2(u32* vm, u32* clut)
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extern "C" void __fastcall WriteCLUT_T16_I4_CSM1_sse2(u32* vm, u32* clut)
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{
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if ((u32)clut & 0x0F) {
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WriteCLUT_T16_I4_CSM1_core_sse2<false>(vm, clut);
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// CSA 16-31 && low 16bits vm
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WriteCLUT_T16_I4_CSM1_core_sse2<false, false>(vm, clut);
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} else {
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WriteCLUT_T16_I4_CSM1_core_sse2<true>(vm, clut);
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// CSA 0-15 && low 16bits vm
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WriteCLUT_T16_I4_CSM1_core_sse2<true, false>(vm, clut);
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}
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}
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@ -1078,23 +1103,36 @@ __forceinline void WriteCLUT_T16_I8_CSM1_sse2(u32* vm, u32 csa)
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{
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// update the right clut column (csa < 16)
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u32* clut = (u32*)(g_pbyGSClut + 64*(csa & 15));
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// u32 csa_right = (csa < 16) ? 16 - csa : 0;
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u32 csa_right = 16 - csa;
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u32 csa_right = (csa < 16) ? 16 - csa : 0;
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for(int i = csa_right; i > 0 ; --i) {
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WriteCLUT_T16_I4_CSM1_core_sse2<true>(vm, clut);
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vm += 16; // go down one column
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for(int i = (csa_right/2); i > 0 ; --i) {
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WriteCLUT_T16_I4_CSM1_core_sse2<true,false>(vm, clut);
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clut += 16;
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WriteCLUT_T16_I4_CSM1_core_sse2<true,true>(vm, clut);
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clut += 16;
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vm += 16; // go down one column
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}
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// update the left clut column
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clut = (u32*)(g_pbyGSClut);
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u32 csa_left = (csa >= 16) ? 16 : csa;
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for(int i = csa_left; i > 0 ; --i) {
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WriteCLUT_T16_I4_CSM1_core_sse2<false>(vm, clut);
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vm += 16; // go down one column
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// In case csa_right is odd (so csa_left is also odd), we cross the clut column
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if(csa_right & 0x1) {
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WriteCLUT_T16_I4_CSM1_core_sse2<true,false>(vm, clut);
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// go back to the base before processing left clut column
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clut = (u32*)(g_pbyGSClut);
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WriteCLUT_T16_I4_CSM1_core_sse2<false,true>(vm, clut);
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} else if(csa_right != 0) {
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// go back to the base before processing left clut column
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clut = (u32*)(g_pbyGSClut);
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}
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for(int i = (csa_left/2); i > 0 ; --i) {
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WriteCLUT_T16_I4_CSM1_core_sse2<false,false>(vm, clut);
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clut += 16;
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WriteCLUT_T16_I4_CSM1_core_sse2<false,true>(vm, clut);
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clut += 16;
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vm += 16; // go down one column
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}
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}
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