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Misc:Debugger: Support write-only GS priv reads

This commit is contained in:
ty 2021-03-29 11:59:10 -04:00 committed by lightningterror
parent 9ea1610d37
commit e36199c499
6 changed files with 38 additions and 1 deletions
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2
pcsx2/DebugTools/Debug.h
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@ -37,6 +37,8 @@ namespace R5900
extern const char * const COP2_REG_FP[32];
extern const char * const COP2_REG_CTL[32];
extern const char * const COP2_VFnames[4];
extern const char * const GS_REG_PRIV[19];
extern const u32 GS_REG_PRIV_ADDR[19];
}
namespace R3000A

16
pcsx2/DebugTools/DebugInterface.cpp
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@ -21,6 +21,7 @@
#include "AppCoreThread.h"
#include "Debug.h"
#include "../VU.h"
#include "../GS.h" // Required for gsNonMirroredRead()
#include "Counters.h"
#include "../R3000A.h"
@ -322,6 +323,8 @@ const char* R5900DebugInterface::getRegisterCategoryName(int cat)
return "VU0f";
case EECAT_VU0I:
return "VU0i";
case EECAT_GSPRIV:
return "GS";
default:
return "Invalid";
}
@ -339,6 +342,8 @@ int R5900DebugInterface::getRegisterSize(int cat)
case EECAT_FCR:
case EECAT_VU0I:
return 32;
case EECAT_GSPRIV:
return 64;
default:
return 0;
}
@ -357,6 +362,8 @@ int R5900DebugInterface::getRegisterCount(int cat)
return 32;
case EECAT_VU0F:
return 33; // 32 + ACC
case EECAT_GSPRIV:
return 19;
default:
return 0;
}
@ -371,6 +378,7 @@ DebugInterface::RegisterType R5900DebugInterface::getRegisterType(int cat)
case EECAT_VU0F:
case EECAT_VU0I:
case EECAT_FCR:
case EECAT_GSPRIV:
default:
return NORMAL;
case EECAT_FPR:
@ -410,6 +418,8 @@ const char* R5900DebugInterface::getRegisterName(int cat, int num)
}
case EECAT_VU0I:
return R5900::COP2_REG_CTL[num];
case EECAT_GSPRIV:
return R5900::GS_REG_PRIV[num];
default:
return "Invalid";
}
@ -460,6 +470,9 @@ u128 R5900DebugInterface::getRegister(int cat, int num)
case EECAT_VU0I:
result = u128::From32(VU0.VI[num].UL);
break;
case EECAT_GSPRIV:
result = gsNonMirroredRead(0x12000000 | R5900::GS_REG_PRIV_ADDR[num]);
break;
default:
result = u128::From32(0);
break;
@ -552,6 +565,9 @@ void R5900DebugInterface::setRegister(int cat, int num, u128 newValue)
case EECAT_VU0I:
VU0.VI[num].UL = newValue._u32[0];
break;
case EECAT_GSPRIV:
memWrite64(0x12000000 | R5900::GS_REG_PRIV_ADDR[num], newValue.lo);
break;
default:
break;
}

2
pcsx2/DebugTools/DebugInterface.h
View File

@ -17,7 +17,7 @@
#include "MemoryTypes.h"
#include "ExpressionParser.h"
enum { EECAT_GPR, EECAT_CP0, EECAT_FPR, EECAT_FCR, EECAT_VU0F, EECAT_VU0I, EECAT_COUNT };
enum { EECAT_GPR, EECAT_CP0, EECAT_FPR, EECAT_FCR, EECAT_VU0F, EECAT_VU0I, EECAT_GSPRIV, EECAT_COUNT };
enum { IOPCAT_GPR, IOPCAT_COUNT };
enum BreakPointCpu
{

13
pcsx2/DebugTools/DisR5900asm.cpp
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@ -142,6 +142,19 @@ const char * const COP2_REG_CTL[32] ={
const char * const COP2_VFnames[4] = { "x", "y", "z", "w" };
//gs privileged registers
const char * const GS_REG_PRIV[19] = {
"PMODE","SMODE1","SMODE2","SRFSH","SYNCH1","SYNCH2","SYNCV",
"DISPFB1","DISPLAY1","DISPFB2","DISPLAY2","EXTBUF","EXTDATA",
"EXTWRITE","BGCOLOR","CSR","IMR","BUSDIR","SIGLBLID",
};
//gs privileged register addresses relative to 12000000h
const u32 GS_REG_PRIV_ADDR[19] = {
0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,
0xa0,0xb0,0xc0,0xd0,0xE0,0x1000,0x1010,0x1040,0x1080
};
void P_COP2_Unknown( std::string& output );
void P_COP2_SPECIAL2( std::string& output );
void P_COP2_SPECIAL( std::string& output );

5
pcsx2/GS.cpp
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@ -349,6 +349,11 @@ __fi u64 gsRead64(u32 mem)
}
}
__fi u128 gsNonMirroredRead(u32 mem)
{
return *(u128*)PS2GS_BASE(mem);
}
void gsIrq() {
hwIntcIrq(INTC_GS);
}

1
pcsx2/GS.h
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@ -435,6 +435,7 @@ extern u8 gsRead8(u32 mem);
extern u16 gsRead16(u32 mem);
extern u32 gsRead32(u32 mem);
extern u64 gsRead64(u32 mem);
extern u128 gsNonMirroredRead(u32 mem);
void gsIrq();