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Minor bug fixes. Reformat iVUzerorec.cpp & get rid of all occurrances of the FORIT macro. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1153 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2009-05-08 04:44:32 +00:00
parent afc5760e6c
commit e330c57556
5 changed files with 2022 additions and 1534 deletions
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5
pcsx2/x86/iR3000Atables.cpp
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@ -1567,9 +1567,10 @@ void rpsxBGEZAL()
_psxFlushAllUnused(); _psxFlushAllUnused();
if( PSX_IS_CONST1(_Rs_) ) { if( PSX_IS_CONST1(_Rs_) ) {
if( g_psxConstRegs[_Rs_] < 0 ) if( (int)g_psxConstRegs[_Rs_] < 0 )
branchTo = psxpc+4; branchTo = psxpc+4;
else MOV32ItoM((uptr)&psxRegs.GPR.r[31], psxpc+4); else
MOV32ItoM((uptr)&psxRegs.GPR.r[31], psxpc+4);
psxRecompileNextInstruction(1); psxRecompileNextInstruction(1);
psxSetBranchImm( branchTo ); psxSetBranchImm( branchTo );

3521
pcsx2/x86/iVUzerorec.cpp
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File diff suppressed because it is too large Load Diff

23
pcsx2/x86/ix86/implement/xmm/moremovs.h
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@ -64,6 +64,7 @@ public:
// This happens when using Mem,Reg or Reg,Mem forms where the address is simple displacement // This happens when using Mem,Reg or Reg,Mem forms where the address is simple displacement
// which can be checked for alignment at runtime. // which can be checked for alignment at runtime.
// //
template< u8 Prefix, bool isAligned > template< u8 Prefix, bool isAligned >
class SimdImpl_MoveSSE class SimdImpl_MoveSSE
{ {
@ -78,9 +79,17 @@ public:
if( to != from ) xOpWrite0F( Prefix, OpcodeA, to, from ); if( to != from ) xOpWrite0F( Prefix, OpcodeA, to, from );
} }
__forceinline void operator()( const xRegisterSSE& to, const void* from ) const __forceinline void operator()( const xRegisterSSE& to, void* from ) const
{ {
xOpWrite0F( Prefix, (isAligned || ((uptr)from & 0x0f) == 0) ? OpcodeA : OpcodeU, to, from ); u16 opcode;
// @$@$@!$#@! GCC & Debug builds.
if (isAligned || ((uptr)from & 0x0f) == 0)
opcode = OpcodeA;
else
opcode = OpcodeU;
xOpWrite0F( Prefix, opcode, to, from );
} }
__forceinline void operator()( void* to, const xRegisterSSE& from ) const __forceinline void operator()( void* to, const xRegisterSSE& from ) const
@ -92,7 +101,15 @@ public:
{ {
// ModSib form is aligned if it's displacement-only and the displacement is aligned: // ModSib form is aligned if it's displacement-only and the displacement is aligned:
bool isReallyAligned = isAligned || ( ((from.Displacement & 0x0f) == 0) && from.Index.IsEmpty() && from.Base.IsEmpty() ); bool isReallyAligned = isAligned || ( ((from.Displacement & 0x0f) == 0) && from.Index.IsEmpty() && from.Base.IsEmpty() );
xOpWrite0F( Prefix, isReallyAligned ? OpcodeA : OpcodeU, to, from ); u16 opcode;
// See previous comment.
if (isReallyAligned)
opcode = OpcodeA;
else
opcode = OpcodeU;
xOpWrite0F( Prefix, opcode, to, from );
} }
__forceinline void operator()( const ModSibBase& to, const xRegisterSSE& from ) const __forceinline void operator()( const ModSibBase& to, const xRegisterSSE& from ) const

5
pcsx2/x86/ix86/ix86_inlines.inl
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@ -216,7 +216,12 @@ namespace x86Emitter
if( !is_s8( displacement ) ) if( !is_s8( displacement ) )
{ {
assert( false ); assert( false );
// Don't ask. --arcum42
#ifdef __LINUX__
#ifndef DEBUG
Console::Error( "Emitter Error: Invalid short jump displacement = 0x%x", params (int)displacement ); Console::Error( "Emitter Error: Invalid short jump displacement = 0x%x", params (int)displacement );
#endif
#endif
} }
BasePtr[-1] = (s8)displacement; BasePtr[-1] = (s8)displacement;
} }

2
pcsx2/x86/ix86/ix86_types.h
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@ -635,7 +635,7 @@ __forceinline void xWrite( T val )
JccComparisonType m_cc; // comparison type of the instruction JccComparisonType m_cc; // comparison type of the instruction
public: public:
const int GetMaxInstructionSize() const int GetMaxInstructionSize() const
{ {
jASSUME( m_cc != Jcc_Unknown ); jASSUME( m_cc != Jcc_Unknown );
return ( m_cc == Jcc_Unconditional ) ? 5 : 6; return ( m_cc == Jcc_Unconditional ) ? 5 : 6;