mirror of https://github.com/PCSX2/pcsx2.git
Some cleanups of the hwRead/Write functions (maybe a small speedup)
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@643 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine
Gregory Hainaut
parent
44f5117d24
commit
e3149cfd5f
235
pcsx2/Hw.cpp
235
pcsx2/Hw.cpp
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@ -155,16 +155,16 @@ __forceinline u16 hwRead16(u32 mem)
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return ret;
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}
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__forceinline u32 hwRead32(u32 mem) {
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u32 ret;
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__forceinline u32 hwRead32(u32 mem)
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{
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//IPU regs
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if ((mem>=0x10002000) && (mem<0x10003000)) {
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return ipuRead32(mem);
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}
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// gauntlen uses 0x1001xxxx
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switch (mem) {
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switch (mem)
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{
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case 0x10000000: return (u16)rcntRcount(0);
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case 0x10000010: return (u16)counters[0].modeval;
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case 0x10000020: return (u16)counters[0].target;
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@ -183,89 +183,87 @@ __forceinline u32 hwRead32(u32 mem) {
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case 0x10001810: return (u16)counters[3].modeval;
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case 0x10001820: return (u16)counters[3].target;
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#ifdef PCSX2_DEVBUILD
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case 0x1000A000:
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ret = psHu32(mem);//dma2 chcr
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HW_LOG("Hardware read DMA2_CHCR 32bit at %lx, ret %lx\n", mem, ret);
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break;
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case 0x1000A010:
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ret = psHu32(mem);//dma2 madr
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HW_LOG("Hardware read DMA2_MADR 32bit at %lx, ret %lx\n", mem, ret);
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break;
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case 0x1000A020:
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ret = psHu32(mem);//dma2 qwc
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HW_LOG("Hardware readDMA2_QWC 32bit at %lx, ret %lx\n", mem, ret);
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break;
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case 0x1000A030:
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ret = psHu32(mem);//dma2 taddr
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HW_LOG("Hardware read DMA2_TADDR 32bit at %lx, ret %lx\n", mem, ret);
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break;
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case 0x1000A040:
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ret = psHu32(mem);//dma2 asr0
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HW_LOG("Hardware read DMA2_ASR0 32bit at %lx, ret %lx\n", mem, ret);
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break;
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case 0x1000A050:
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ret = psHu32(mem);//dma2 asr1
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HW_LOG("Hardware read DMA2_ASR1 32bit at %lx, ret %lx\n", mem, ret);
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break;
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case 0x1000A080:
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ret = psHu32(mem);//dma2 saddr
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HW_LOG("Hardware read DMA2_SADDR 32 at %lx, ret %lx\n", mem, ret);
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break;
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//#ifdef PCSX2_DEVBUILD
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case 0x1000A000: //dma2 chcr
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HW_LOG("Hardware read DMA2_CHCR 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A010: //dma2 madr
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HW_LOG("Hardware read DMA2_MADR 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A020: //dma2 qwc
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HW_LOG("Hardware readDMA2_QWC 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A030: //dma2 taddr
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HW_LOG("Hardware read DMA2_TADDR 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A040: //dma2 asr0
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HW_LOG("Hardware read DMA2_ASR0 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A050: //dma2 asr1
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HW_LOG("Hardware read DMA2_ASR1 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A080: //dma2 saddr
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HW_LOG("Hardware read DMA2_SADDR 32 at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000B400: // dma4 chcr
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ret = ((DMACh *)&PS2MEM_HW[0xb400])->chcr;
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SPR_LOG("Hardware read IPU1_CHCR 32 at %lx, ret %x\n", mem, ret);
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break;
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SPR_LOG("Hardware read IPU1_CHCR 32 at %lx, ret %x\n", mem, ((DMACh *)&PS2MEM_HW[0xb400])->chcr);
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return ((DMACh *)&PS2MEM_HW[0xb400])->chcr;
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case 0x1000e010: // DMAC_STAT
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HW_LOG("DMAC_STAT Read 32bit %x\n", psHu32(0xe010));
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return psHu32(0xe010);
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case 0x1000f000: // INTC_STAT
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// HW_LOG("INTC_STAT Read 32bit %x\n", psHu32(0xf000));
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//HW_LOG("INTC_STAT Read 32bit %x\n", psHu32(0xf000)); // this one tends to spam the logs..
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return psHu32(0xf000);
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case 0x1000f010: // INTC_MASK
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HW_LOG("INTC_MASK Read 32bit %x\n", psHu32(0xf010));
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return psHu32(0xf010);
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#endif
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//#endif
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case 0x1000f130:
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case 0x1000f260:// SIF?
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case 0x1000f410:
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case 0x1000f430://MCH_RICM
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ret = 0;
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break;
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return 0;
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case 0x1000f440://MCH_DRD
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if ((psHu32(0xf430) >> 6) & 0xF)
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ret = 0;
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else
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switch ((psHu32(0xf430)>>16) & 0xFFF){//MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5
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if( !((psHu32(0xf430) >> 6) & 0xF) )
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{
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switch ((psHu32(0xf430)>>16) & 0xFFF)
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{ //MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5
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case 0x21://INIT
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ret = 0x1F * (rdram_sdevid < rdram_devices);
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rdram_sdevid += (rdram_sdevid < rdram_devices);
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break;
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case 0x23://CNFGA
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ret = 0x0D0D; //PVER=3 | MVER=16 | DBL=1 | REFBIT=5
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break;
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case 0x24://CNFGB
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//0x0110 for PSX SVER=0 | CORG=8(5x9x7) | SPT=1 | DEVTYP=0 | BYTE=0
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ret = 0x0090; //SVER=0 | CORG=4(5x9x6) | SPT=1 | DEVTYP=0 | BYTE=0
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break;
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case 0x40://DEVID
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ret = psHu32(0xf430) & 0x1F; // =SDEV
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break;
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default:
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ret = 0;
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break;
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if(rdram_sdevid < rdram_devices)
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{
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rdram_sdevid++;
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return 0x1F;
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}
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break;
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case 0x23://CNFGA
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return 0x0D0D; //PVER=3 | MVER=16 | DBL=1 | REFBIT=5
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case 0x24://CNFGB
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//0x0110 for PSX SVER=0 | CORG=8(5x9x7) | SPT=1 | DEVTYP=0 | BYTE=0
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return 0x0090; //SVER=0 | CORG=4(5x9x6) | SPT=1 | DEVTYP=0 | BYTE=0
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case 0x40://DEVID
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return psHu32(0xf430) & 0x1F; // =SDEV
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}
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}
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return 0;
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case 0x1000f520: // DMAC_ENABLER
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HW_LOG("DMAC_ENABLER Read 32bit %lx\n", psHu32(0xf590));
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return psHu32(0xf590);
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case 0x1000f240: // SIF?
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return psHu32(mem) | 0xF0000102;
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default:
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if ((mem & 0xffffff0f) == 0x1000f200) {
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//if ((mem & 0xffffff0f) == 0x1000f200) {
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// SIF Control Registers
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/*1D000020 (word) - EE -> IOP status flag ( set to 0x10000 always ready )
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1D000030 (word) - IOP -> EE status flag
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@ -275,7 +273,7 @@ __forceinline u32 hwRead32(u32 mem) {
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read must be 0x1D000060, or the top 20 bits must be zero
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*/
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// note, any changes you make in here, also make on recMemRead32
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if(mem ==0x1000f260) ret = 0;
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/*if(mem ==0x1000f260) ret = 0;
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else if(mem == 0x1000F240) {
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ret = psHu32(mem) | 0xF0000102;
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//psHu32(mem) &= ~0x4000;
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@ -287,21 +285,20 @@ __forceinline u32 hwRead32(u32 mem) {
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break;
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}
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else if (mem < 0x10010000) {
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ret = psHu32(mem);
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}
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else {
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SysPrintf("32bit HW read of address 0x%x\n", mem);
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ret = 0;
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}
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HW_LOG("Unknown Hardware Read 32 at %lx, ret %lx\n", mem, ret);
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break;
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}
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else */
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return ret;
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HW_LOG("Unknown Hardware Read 32 at %lx, ret %lx\n", mem, psHu32(mem));
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if (mem < 0x10010000)
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return psHu32(mem);
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else
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Console::Notice("*PCSX2* 32bit HW read of invalid address 0x%x\n", params mem);
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return 0;
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}
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}
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u64 hwRead64(u32 mem) {
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__forceinline u64 hwRead64(u32 mem) {
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u64 ret;
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if ((mem>=0x10002000) && (mem<0x10003000)) {
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@ -321,7 +318,7 @@ u64 hwRead64(u32 mem) {
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return ret;
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}
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void hwRead128(u32 mem, u64 *out) {
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__forceinline void hwRead128(u32 mem, u64 *out) {
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if (mem >= 0x10004000 && mem < 0x10008000) {
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ReadFIFO(mem, out); return;
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}
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@ -472,20 +469,16 @@ void hwWrite8(u32 mem, u8 value) {
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psHu8(0xf522) = value;
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break;
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default:
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if ((mem & 0xffffff0f) == 0x1000f200) {
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u32 at = mem & 0xf0;
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switch(at)
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{
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case 0x00:
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case 0x1000f200: // SIF(?)
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psHu8(mem) = value;
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break;
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case 0x40:
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if(!(value & 0x100)) psHu32(mem) &= ~0x100;
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case 0x1000f240:// SIF(?)
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if(!(value & 0x100))
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psHu32(mem) &= ~0x100;
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break;
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}
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return;
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}
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default:
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assert( (mem&0xff0f) != 0xf200 );
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switch(mem&~3) {
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@ -501,7 +494,7 @@ void hwWrite8(u32 mem, u8 value) {
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}
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}
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void hwWrite16(u32 mem, u16 value)
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__forceinline void hwWrite16(u32 mem, u16 value)
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{
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#ifdef PCSX2_DEVBUILD
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if( mem >= 0x10000000 && mem < 0x10008000 )
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@ -679,46 +672,40 @@ void hwWrite16(u32 mem, u16 value)
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case 0x1000f430:
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case 0x1000f432:
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break;
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default:
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if ((mem & 0xffffff0f) == 0x1000f200) {
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u32 at = mem & 0xf0;
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switch(at)
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{
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case 0x00:
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case 0x1000f200:
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psHu16(mem) = value;
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break;
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case 0x20:
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case 0x1000f220:
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psHu16(mem) |= value;
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break;
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case 0x30:
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case 0x1000f230:
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psHu16(mem) &= ~value;
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break;
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case 0x40:
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assert( (mem&2)==0);
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if(!(value & 0x100)) psHu16(mem) &= ~0x100;
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else psHu16(mem) |= 0x100;
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case 0x1000f240:
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if(!(value & 0x100))
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psHu16(mem) &= ~0x100;
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else
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psHu16(mem) |= 0x100;
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break;
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case 0x60:
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case 0x1000f260:
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psHu16(mem) = 0;
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break;
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}
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return;
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}
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assert( (mem&0xff0f) != 0xf200 );
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default:
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#ifndef PCSX2_VIRTUAL_MEM
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if (mem < 0x10010000)
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#endif
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{
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psHu16(mem) = value;
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}
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}
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HW_LOG("Unknown Hardware write 16 at %x with value %x\n",mem,value);
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}
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}
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void hwWrite32(u32 mem, u32 value) {
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__forceinline void hwWrite32(u32 mem, u32 value) {
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if ((mem>=0x10002000) && (mem<0x10003000)) { //IPU regs
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ipuWrite32(mem,value);
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@ -782,6 +769,7 @@ void hwWrite32(u32 mem, u32 value) {
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DMA_LOG("VIF1dma CHCR %lx\n", value);
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DmaExec(dmaVIF1, mem, value);
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break;
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#ifdef PCSX2_DEVBUILD
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case 0x10009010: // dma1 - vif1 - madr
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HW_LOG("VIF1dma Madr %lx\n", value);
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psHu32(mem) = value;//dma1 madr
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@ -806,11 +794,13 @@ void hwWrite32(u32 mem, u32 value) {
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HW_LOG("VIF1dma SADR %lx\n", value);
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psHu32(mem) = value;//dma1 sadr
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break;
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#endif
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//------------------------------------------------------------------
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case 0x1000a000: // dma2 - gif
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DMA_LOG("0x%8.8x hwWrite32: GSdma %lx\n", cpuRegs.cycle, value);
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DmaExec(dmaGIF, mem, value);
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break;
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#ifdef PCSX2_DEVBUILD
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case 0x1000a010:
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psHu32(mem) = value;//dma2 madr
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HW_LOG("Hardware write DMA2_MADR 32bit at %x with value %x\n",mem,value);
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@ -835,12 +825,14 @@ void hwWrite32(u32 mem, u32 value) {
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psHu32(mem) = value;//dma2 saddr
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HW_LOG("Hardware write DMA2_SADDR 32bit at %x with value %x\n",mem,value);
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break;
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#endif
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//------------------------------------------------------------------
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case 0x1000b000: // dma3 - fromIPU
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DMA_LOG("IPU0dma %lx\n", value);
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DmaExec(dmaIPU0, mem, value);
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break;
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//------------------------------------------------------------------
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#ifdef PCSX2_DEVBUILD
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case 0x1000b010:
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psHu32(mem) = value;//dma2 madr
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HW_LOG("Hardware write IPU0DMA_MADR 32bit at %x with value %x\n",mem,value);
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@ -857,12 +849,14 @@ void hwWrite32(u32 mem, u32 value) {
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psHu32(mem) = value;//dma2 saddr
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HW_LOG("Hardware write IPU0DMA_SADDR 32bit at %x with value %x\n",mem,value);
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break;
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#endif
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//------------------------------------------------------------------
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case 0x1000b400: // dma4 - toIPU
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DMA_LOG("IPU1dma %lx\n", value);
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DmaExec(dmaIPU1, mem, value);
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break;
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//------------------------------------------------------------------
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#ifdef PCSX2_DEVBUILD
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case 0x1000b410:
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psHu32(mem) = value;//dma2 madr
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HW_LOG("Hardware write IPU1DMA_MADR 32bit at %x with value %x\n",mem,value);
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@ -879,6 +873,7 @@ void hwWrite32(u32 mem, u32 value) {
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psHu32(mem) = value;//dma2 saddr
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HW_LOG("Hardware write IPU1DMA_SADDR 32bit at %x with value %x\n",mem,value);
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break;
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#endif
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//------------------------------------------------------------------
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case 0x1000c000: // dma5 - sif0
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DMA_LOG("SIF0dma %lx\n", value);
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@ -890,6 +885,7 @@ void hwWrite32(u32 mem, u32 value) {
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DMA_LOG("SIF1dma %lx\n", value);
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DmaExec(dmaSIF1, mem, value);
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break;
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#ifdef PCSX2_DEVBUILD
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case 0x1000c420: // dma6 - sif1 - qwc
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HW_LOG("SIF1dma QWC = %lx\n", value);
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psHu32(mem) = value;
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@ -898,6 +894,7 @@ void hwWrite32(u32 mem, u32 value) {
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HW_LOG("SIF1dma TADR = %lx\n", value);
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psHu32(mem) = value;
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break;
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#endif
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//------------------------------------------------------------------
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case 0x1000c800: // dma7 - sif2
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DMA_LOG("SIF2dma %lx\n", value);
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@ -916,7 +913,7 @@ void hwWrite32(u32 mem, u32 value) {
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//------------------------------------------------------------------
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case 0x1000e000: // DMAC_CTRL
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HW_LOG("DMAC_CTRL Write 32bit %x\n", value);
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psHu32(mem) = value;
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psHu32(0xe000) = value;
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break;
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case 0x1000e010: // DMAC_STAT
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@ -965,8 +962,10 @@ void hwWrite32(u32 mem, u32 value) {
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psHu32(mem) &= ~value;
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break;
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case 0x1000f240:
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if(!(value & 0x100)) psHu32(mem) &= ~0x100;
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else psHu32(mem) |= 0x100;
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if(!(value & 0x100))
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psHu32(mem) &= ~0x100;
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else
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||||
psHu32(mem) |= 0x100;
|
||||
break;
|
||||
case 0x1000f260:
|
||||
psHu32(mem) = 0;
|
||||
|
|
@ -989,7 +988,7 @@ void hwWrite32(u32 mem, u32 value) {
|
|||
}
|
||||
}
|
||||
|
||||
void hwWrite64(u32 mem, u64 value) {
|
||||
__forceinline void hwWrite64(u32 mem, u64 value) {
|
||||
u32 val32;
|
||||
int i;
|
||||
|
||||
|
|
@ -1051,8 +1050,10 @@ void hwWrite64(u32 mem, u64 value) {
|
|||
val32 = val32 >> 16;
|
||||
for (i=0; i<16; i++) { // reverse on 1
|
||||
if (val32 & (1<<i)) {
|
||||
if (psHu16(0xe012) & (1<<i)) psHu16(0xe012)&= ~(1<<i);
|
||||
else psHu16(0xe012)|= 1<<i;
|
||||
if (psHu16(0xe012) & (1<<i))
|
||||
psHu16(0xe012)&= ~(1<<i);
|
||||
else
|
||||
psHu16(0xe012)|= 1<<i;
|
||||
}
|
||||
}
|
||||
cpuTestDMACInts();
|
||||
|
|
@ -1074,8 +1075,10 @@ void hwWrite64(u32 mem, u64 value) {
|
|||
for (i=0; i<16; i++) { // reverse on 1
|
||||
const int s = (1<<i);
|
||||
if (value & s) {
|
||||
if (psHu32(INTC_MASK) & s) psHu32(INTC_MASK)&= ~s;
|
||||
else psHu32(INTC_MASK)|= s;
|
||||
if (psHu32(INTC_MASK) & s)
|
||||
psHu32(INTC_MASK)&= ~s;
|
||||
else
|
||||
psHu32(INTC_MASK)|= s;
|
||||
}
|
||||
}
|
||||
cpuTestINTCInts();
|
||||
|
|
@ -1094,7 +1097,7 @@ void hwWrite64(u32 mem, u64 value) {
|
|||
}
|
||||
}
|
||||
|
||||
void hwWrite128(u32 mem, const u64 *value) {
|
||||
__forceinline void hwWrite128(u32 mem, const u64 *value) {
|
||||
if (mem >= 0x10004000 && mem < 0x10008000) {
|
||||
WriteFIFO(mem, value); return;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue