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VU: Improve VU0/Mbit sync with VU Interpreter. Improve Kickstart.

This commit is contained in:
refractionpcsx2 2021-09-05 21:36:41 +01:00
parent 2e2d6ba35d
commit e19b0bce57
5 changed files with 13 additions and 14 deletions
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3
pcsx2/VU0.cpp
View File

@ -65,7 +65,7 @@ __fi void _vu0run(bool breakOnMbit, bool addCycles) {
return; return;
} }
u32 startcycle = VU0.cycle; u32 startcycle = cpuRegs.cycle;
u32 runCycles = 0x7fffffff; u32 runCycles = 0x7fffffff;
do { // Run VU until it finishes or M-Bit do { // Run VU until it finishes or M-Bit
@ -77,7 +77,6 @@ __fi void _vu0run(bool breakOnMbit, bool addCycles) {
if (addCycles) if (addCycles)
{ {
cpuRegs.cycle += (VU0.cycle - startcycle); cpuRegs.cycle += (VU0.cycle - startcycle);
VU0.cycle = cpuRegs.cycle;
CpuVU1->ExecuteBlock(0); // Catch up VU1 as it's likely fallen behind CpuVU1->ExecuteBlock(0); // Catch up VU1 as it's likely fallen behind
} }
} }

7
pcsx2/VU0microInterp.cpp
View File

@ -154,9 +154,7 @@ static void _vu0Exec(VURegs* VU)
} }
} }
_vuAddUpperStalls(VU, &uregs); _vuAddUpperStalls(VU, &uregs);
_vuAddLowerStalls(VU, &lregs);
if (!(ptr[1] & 0x80000000))
_vuAddLowerStalls(VU, &lregs);
if (VU->branch > 0) { if (VU->branch > 0) {
if (VU->branch-- == 1) { if (VU->branch-- == 1) {
@ -222,7 +220,8 @@ void InterpVU0::Execute(u32 cycles)
VU0.VI[REG_TPC].UL <<= 3; VU0.VI[REG_TPC].UL <<= 3;
VU0.flags &= ~VUFLAG_MFLAGSET; VU0.flags &= ~VUFLAG_MFLAGSET;
for (int i = (int)cycles; i > 0; i--) { u32 startcycles = VU0.cycle;
while((VU0.cycle - startcycles) < cycles) {
if (!(VU0.VI[REG_VPU_STAT].UL & 0x1) || (VU0.flags & VUFLAG_MFLAGSET)) { if (!(VU0.VI[REG_VPU_STAT].UL & 0x1) || (VU0.flags & VUFLAG_MFLAGSET)) {
if (VU0.branch || VU0.ebit) { if (VU0.branch || VU0.ebit) {
vu0Exec(&VU0); // run branch delay slot? vu0Exec(&VU0); // run branch delay slot?

3
pcsx2/VU1microInterp.cpp
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@ -297,7 +297,8 @@ void InterpVU1::Execute(u32 cycles)
fesetround(g_sseVUMXCSR.RoundingControl << 8); fesetround(g_sseVUMXCSR.RoundingControl << 8);
VU1.VI[REG_TPC].UL <<= 3; VU1.VI[REG_TPC].UL <<= 3;
for (int i = (int)cycles; i > 0; i--) u32 startcycles = VU1.cycle;
while ((VU1.cycle - startcycles) < cycles)
{ {
if (!(VU0.VI[REG_VPU_STAT].UL & 0x100)) if (!(VU0.VI[REG_VPU_STAT].UL & 0x100))
{ {

8
pcsx2/VUmicro.cpp
View File

@ -87,12 +87,12 @@ void BaseVUmicroCPU::ExecuteBlock(bool startUp)
// I don't like doing this, but Crash Twinsanity seems to be upset without it // I don't like doing this, but Crash Twinsanity seems to be upset without it
if (stat & test) if (stat & test)
{ {
cpuSetNextEventDelta(s);
if (m_Idx) if (m_Idx)
VU1.cycle = cpuRegs.cycle; cpuRegs.cycle = VU1.cycle;
else else
VU0.cycle = cpuRegs.cycle; cpuRegs.cycle = VU0.cycle;
cpuSetNextEventDelta(s);
} }
} }
else // Continue Executing else // Continue Executing

6
pcsx2/VUops.cpp
View File

@ -106,8 +106,8 @@ static __ri bool _vuFMACflush(VURegs * VU) {
{ {
if ((VU->cycle - VU->fmac[currentpipe].sCycle) < lastmac) if ((VU->cycle - VU->fmac[currentpipe].sCycle) < lastmac)
{ {
VUM_LOG("flushing FMAC pipe[%d] (macflag=%x status=%x) Cur Cycle %d Expected cycle %d", currentpipe, VU->fmac[currentpipe].macflag, (VU->VI[REG_STATUS_FLAG].UL & 0xF30) | (VU->fmac[currentpipe].statusflag & 0x3CF), VU->cycle, VU->fmac[currentpipe].sCycle + VU->fmac[currentpipe].Cycle); VUM_LOG("flushing FMAC pipe[%d] (macflag=%x status=%x) Cur Cycle %d Expected cycle %d", currentpipe, VU->fmac[currentpipe].macflag, (VU->VI[REG_STATUS_FLAG].UL & 0xF30) | (VU->fmac[currentpipe].statusflag & 0x3CF), VU->cycle, VU->fmac[currentpipe].sCycle + VU->fmac[currentpipe].Cycle);
// FMAC only affectx Z/S/I/O // FMAC only affectx Z/S/I/O
VU->VI[REG_STATUS_FLAG].UL = (VU->VI[REG_STATUS_FLAG].UL & 0xFF0) | ((VU->fmac[currentpipe].statusflag & 0xF) | ((VU->fmac[currentpipe].statusflag & 0xF) << 6)); VU->VI[REG_STATUS_FLAG].UL = (VU->VI[REG_STATUS_FLAG].UL & 0xFF0) | ((VU->fmac[currentpipe].statusflag & 0xF) | ((VU->fmac[currentpipe].statusflag & 0xF) << 6));
VU->VI[REG_MAC_FLAG].UL = VU->fmac[currentpipe].macflag; VU->VI[REG_MAC_FLAG].UL = VU->fmac[currentpipe].macflag;
lastmac = (VU->cycle - VU->fmac[currentpipe].sCycle); lastmac = (VU->cycle - VU->fmac[currentpipe].sCycle);
@ -263,7 +263,7 @@ void _vuFlushAll(VURegs* VU)
__fi void _vuTestPipes(VURegs * VU) { __fi void _vuTestPipes(VURegs * VU) {
bool flushed; bool flushed;
u32 startcycle = VU->cycle;
do { do {
flushed = false; flushed = false;
flushed |= _vuFMACflush(VU); flushed |= _vuFMACflush(VU);