mirror of https://github.com/PCSX2/pcsx2.git
DEV9: Add extra defines
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TheLastRar
refractionpcsx2
parent
6c5b63707d
commit
e0da758d1b
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@ -146,20 +146,33 @@ void SysMessage(char* fmt, ...);
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*/
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// clang-format off
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#define SPD_INTR_ATA_FIFO_DATA (1 << 1)
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#define SPD_INTR_ATA_FIFO_FULL (1 << 15) //Or Error/underflow/overfolw(?)
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#define SPD_INTR_ATA_FIFO_EMPTY (1 << 14)
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#define SPD_INTR_ATA_FIFO_OVERFLOW (SPD_INTR_ATA_FIFO_FULL | SPD_INTR_ATA_FIFO_EMPTY) //by HDD only?
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#define SPD_REGBASE 0x10000000
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#define SPD_R_REV (SPD_REGBASE + 0x00)
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#define SPD_R_REV_1 (SPD_REGBASE + 0x02)
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// bit 0: smap
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// bit 1: hdd
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// bit 5: flash
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#define SPD_R_REV_3 (SPD_REGBASE + 0x04)
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#define SPD_R_0e (SPD_REGBASE + 0x0e)
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#define ATA_INTR_INTRQ (1 << 0)
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#define SPD_R_REV_1 (SPD_REGBASE + 0x00)
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#define SPD_R_REV_2 (SPD_REGBASE + 0x02)
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#define SPD_CAPS_SMAP (1 << 0)
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#define SPD_CAPS_ATA (1 << 1)
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#define SPD_CAPS_UART (1 << 3)
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#define SPD_CAPS_DVR (1 << 4)
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#define SPD_CAPS_FLASH (1 << 5)
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#define SPD_R_REV_3 (SPD_REGBASE + 0x04)
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#define SPD_R_0e (SPD_REGBASE + 0x0e)
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#define SPD_R_DMA_CTRL (SPD_REGBASE + 0x24)
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#define SPD_DMA_TO_SMAP (1 << 0)
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#define SPD_DMA_FASTEST (1 << 1)
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#define SPD_DMA_WIDE (1 << 2)
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#define SPD_DMA_PAUSE (1 << 4) //Pause SPEED->IOP DMA, by keeping DREQ inactive
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#define SPD_R_INTR_STAT (SPD_REGBASE + 0x28)
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#define SPD_R_INTR_MASK (SPD_REGBASE + 0x2a)
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#define SPD_R_PIO_DIR (SPD_REGBASE + 0x2c)
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#define SPD_R_PIO_DATA (SPD_REGBASE + 0x2e)
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#define SPD_PP_DOUT (1<<4) /* Data output, read port */
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@ -173,13 +186,29 @@ void SysMessage(char* fmt, ...);
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#define SPD_PP_OP_EWDS 0
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#define SPD_R_XFR_CTRL (SPD_REGBASE + 0x32)
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#define SPD_R_IF_CTRL (SPD_REGBASE + 0x64)
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#define SPD_IF_ATA_RESET 0x80
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#define SPD_IF_DMA_ENABLE 0x04
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#define SPD_R_PIO_MODE (SPD_REGBASE + 0x70)
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#define SPD_R_MWDMA_MODE (SPD_REGBASE + 0x72)
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#define SPD_R_UDMA_MODE (SPD_REGBASE + 0x74)
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#define SPD_XFR_WRITE (1 << 0)
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#define SPD_XFR_DMAEN (1 << 1)
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#define SPD_R_DBUF_STAT (SPD_REGBASE + 0x38)
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//Read
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#define SPD_DBUF_AVAIL_MAX 0x10
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#define SPD_DBUF_AVAIL_MASK 0x1F
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#define SPD_DBUF_STAT_1 (1 << 5) //HDD->SPEED: Buffer has free space, IOP->SPEED: Buffer is completely empty
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#define SPD_DBUF_STAT_2 (1 << 6) //HDD->SPEED: Buffer is completely empty, no data written IOP->SPEED: Buffer has data
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#define SPD_DBUF_STAT_FULL (1 << 7)
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//HDD->SPEED: both SPD_DBUF_STAT_2 and SPD_DBUF_STAT_FULL set to 1 indicates overflow
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//Write
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#define SPD_DBUF_RESET_FIFO (1 << 1) //Set SPD_DBUF_STAT_1 & SPD_DBUF_STAT_2, SPD_DBUF_AVAIL set to 0
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#define SPD_R_IF_CTRL (SPD_REGBASE + 0x64)
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#define SPD_IF_UDMA (1 << 0)
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#define SPD_IF_READ (1 << 1)
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#define SPD_IF_ATA_DMAEN (1 << 2) //Allow HDD<->SPEED DMA, auto cleared on trasfer end
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#define SPD_IF_HDD_RESET (1 << 6) //HDD Hard Reset, 0=act.low/1=inact.high.
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#define SPD_IF_ATA_RESET (1 << 7) //Reset ATA Interface
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#define SPD_R_PIO_MODE (SPD_REGBASE + 0x70)
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#define SPD_R_MDMA_MODE (SPD_REGBASE + 0x72)
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#define SPD_R_UDMA_MODE (SPD_REGBASE + 0x74)
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/*
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* SMAP (PS2 Network Adapter) register definitions.
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@ -551,8 +580,6 @@ typedef struct _smap_bd {
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#define SMAP_DsPHYTER_10BTSCR 0x1A
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#define SMAP_DsPHYTER_CDCTRL 0x1B
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// clang-format on
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/*
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* ATA hardware types and definitions.
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*
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@ -561,23 +588,47 @@ typedef struct _smap_bd {
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* * code included from the ps2drv iop driver, modified by linuzappz *
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*/
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#define ATA_DEV9_HDD_BASE (SPD_REGBASE + 0x40)
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#define ATA_DEV9_HDD_BASE (SPD_REGBASE + 0x40)
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/* AIF on T10Ks - Not supported yet. */
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#define ATA_AIF_HDD_BASE (SPD_REGBASE + 0x4000000 + 0x60)
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#define ATA_AIF_HDD_BASE (SPD_REGBASE + 0x4000000 + 0x60)
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#define ATA_R_DATA (ATA_DEV9_HDD_BASE + 0x00)
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#define ATA_R_ERROR (ATA_DEV9_HDD_BASE + 0x02) //On Read
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#define ATA_R_FEATURE (ATA_DEV9_HDD_BASE + 0x02) //On Write
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#define ATA_R_NSECTOR (ATA_DEV9_HDD_BASE + 0x04)
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#define ATA_R_SECTOR (ATA_DEV9_HDD_BASE + 0x06)
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#define ATA_R_LCYL (ATA_DEV9_HDD_BASE + 0x08)
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#define ATA_R_HCYL (ATA_DEV9_HDD_BASE + 0x0a)
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#define ATA_R_SELECT (ATA_DEV9_HDD_BASE + 0x0c)
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#define ATA_R_STATUS (ATA_DEV9_HDD_BASE + 0x0e) //On Read
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#define ATA_R_CMD (ATA_DEV9_HDD_BASE + 0x0e) //On Write
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#define ATA_R_ALT_STATUS (ATA_DEV9_HDD_BASE + 0x1c) //On Read
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#define ATA_R_CONTROL (ATA_DEV9_HDD_BASE + 0x1c) //On Write
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#define ATA_DEV9_INT (0x01)
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#define ATA_DEV9_INT_DMA (0x02) //not sure rly
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#define ATA_DEV9_HDD_END (ATA_R_CONTROL + 4)
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/* r_error bits. */
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#define ATA_ERR_MARK 0x01
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#define ATA_ERR_TRACK0 0x02
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#define ATA_ERR_ABORT 0x04
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#define ATA_ERR_MCR 0x08
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#define ATA_ERR_ID 0x10
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#define ATA_ERR_MC 0x20
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#define ATA_ERR_ECC 0x40
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#define ATA_ERR_ICRC 0x80
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/* r_status bits. */
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#define ATA_STAT_ERR 0x01
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#define ATA_STAT_INDEX 0x02
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#define ATA_STAT_ECC 0x04
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#define ATA_STAT_DRQ 0x08
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#define ATA_STAT_SEEK 0x10
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#define ATA_STAT_WRERR 0x20
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#define ATA_STAT_READY 0x40
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#define ATA_STAT_BUSY 0x80
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#define ATA_R_DATA (ATA_DEV9_HDD_BASE + 0x00)
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#define ATA_R_ERROR (ATA_DEV9_HDD_BASE + 0x02)
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#define ATA_R_NSECTOR (ATA_DEV9_HDD_BASE + 0x04)
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#define ATA_R_SECTOR (ATA_DEV9_HDD_BASE + 0x06)
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#define ATA_R_LCYL (ATA_DEV9_HDD_BASE + 0x08)
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#define ATA_R_HCYL (ATA_DEV9_HDD_BASE + 0x0a)
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#define ATA_R_SELECT (ATA_DEV9_HDD_BASE + 0x0c)
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#define ATA_R_STATUS (ATA_DEV9_HDD_BASE + 0x0e)
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#define ATA_R_CONTROL (ATA_DEV9_HDD_BASE + 0x1c)
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#define ATA_DEV9_INT (0x01)
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#define ATA_DEV9_INT_DMA (0x02) //not sure rly
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#define ATA_DEV9_HDD_END (ATA_R_CONTROL + 4)
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/*
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* NAND Flash via Dev9 driver definitions
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*
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@ -604,6 +655,8 @@ typedef struct _smap_bd {
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#define SM_CMD_GETSTATUS 0x70
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#define SM_CMD_READID 0x90
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// clang-format on
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typedef struct
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{
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u32 id;
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