mirror of https://github.com/PCSX2/pcsx2.git
A couple misc changes. Converted a few more lines to the new register format, fixed spelling in a few comments, and so on...
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1997 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42
parent
4b6e67eff8
commit
e0cef88d54
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@ -120,7 +120,7 @@ FILE *_cdvdOpenNVM()
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nvmfile.SetExt( L"nvm" );
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const wxCharBuffer file( nvmfile.GetFullPath().ToUTF8() );
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// if file doesnt exist, create empty one
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// if file doesn't exist, create empty one
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fd = fopen(file.data(), "r+b");
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if (fd == NULL)
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{
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@ -266,13 +266,13 @@ s32 cdvdReadConfig(u8* config)
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switch (cdvd.COffset)
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{
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case 0:
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return getNvmData(config, (cdvd.CBlockIndex++)*16, 16, offsetof(NVMLayout, config0));
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return getNvmData(config, (cdvd.CBlockIndex++)*16, 16, offsetof(NVMLayout, config0));
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break;
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case 2:
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return getNvmData(config, (cdvd.CBlockIndex++)*16, 16, offsetof(NVMLayout, config2));
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return getNvmData(config, (cdvd.CBlockIndex++)*16, 16, offsetof(NVMLayout, config2));
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break;
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default:
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return getNvmData(config, (cdvd.CBlockIndex++)*16, 16, offsetof(NVMLayout, config1));
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return getNvmData(config, (cdvd.CBlockIndex++)*16, 16, offsetof(NVMLayout, config1));
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}
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}
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s32 cdvdWriteConfig(const u8* config)
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@ -291,7 +291,7 @@ s32 cdvdWriteConfig(const u8* config)
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switch (cdvd.COffset)
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{
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case 0:
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return setNvmData(config, (cdvd.CBlockIndex++)*16, 16,offsetof(NVMLayout, config0));
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return setNvmData(config, (cdvd.CBlockIndex++)*16, 16, offsetof(NVMLayout, config0));
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break;
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case 2:
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return setNvmData(config, (cdvd.CBlockIndex++)*16, 16, offsetof(NVMLayout, config2));
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@ -301,6 +301,16 @@ s32 cdvdWriteConfig(const u8* config)
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}
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}
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void reloadElfInfo(const char* str)
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{
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// Now's a good time to reload the ELF info...
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if (ElfCRC == 0)
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{
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ElfCRC = loadElfCRC( str );
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ElfApplyPatches();
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mtgsThread.SendGameCRC( ElfCRC );
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}
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}
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void cdvdReadKey(u8 arg0, u16 arg1, u32 arg2, u8* key) {
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wxString fname;
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@ -345,40 +355,36 @@ void cdvdReadKey(u8 arg0, u16 arg1, u32 arg2, u8* key) {
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key[ 3] = (key_0_3&0xFF000000)>>24;
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key[ 4] = key_4;
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if(arg2 == 75)
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{
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key[14] = key_14;
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key[15] = 0x05;
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}
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else if(arg2 == 3075)
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{
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key[15] = 0x01;
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}
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else if(arg2 == 4246)
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{
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// 0x0001F2F707 = sector 0x0001F2F7 dec 0x07
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key[ 0] = 0x07;
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key[ 1] = 0xF7;
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key[ 2] = 0xF2;
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key[ 3] = 0x01;
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key[ 4] = 0x00;
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key[15] = 0x01;
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}
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else
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{
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key[15] = 0x01;
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}
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switch (arg2)
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{
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case 75:
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key[14] = key_14;
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key[15] = 0x05;
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break;
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// case 3075:
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// key[15] = 0x01;
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// break;
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case 4246:
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// 0x0001F2F707 = sector 0x0001F2F7 dec 0x07
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key[ 0] = 0x07;
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key[ 1] = 0xF7;
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key[ 2] = 0xF2;
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key[ 3] = 0x01;
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key[ 4] = 0x00;
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key[15] = 0x01;
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break;
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default:
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key[15] = 0x01;
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break;
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}
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Console.WriteLn( "CDVD.KEY = %02X,%02X,%02X,%02X,%02X,%02X,%02X",
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cdvd.Key[0],cdvd.Key[1],cdvd.Key[2],cdvd.Key[3],cdvd.Key[4],cdvd.Key[14],cdvd.Key[15] );
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// Now's a good time to reload the ELF info...
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if( IsPs2 && (ElfCRC == 0) )
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{
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ElfCRC = loadElfCRC( str );
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ElfApplyPatches();
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mtgsThread.SendGameCRC( ElfCRC );
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}
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if (IsPs2) reloadElfInfo(str);
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}
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s32 cdvdGetToc(void* toc)
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@ -505,13 +511,7 @@ void cdvdDetectDisk()
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wxString str;
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bool IsPs2 = (GetPS2ElfName(str) == 2);
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// Now's a good time to reload the ELF info...
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if( IsPs2 && (ElfCRC == 0) )
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{
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ElfCRC = loadElfCRC( str.ToAscii().data() );
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ElfApplyPatches();
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mtgsThread.SendGameCRC( ElfCRC );
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}
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if (IsPs2) reloadElfInfo(str.ToAscii().data());
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}
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void cdvdNewDiskCB()
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@ -65,7 +65,11 @@ __forceinline void gsInterrupt()
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if (Path3progress != IMAGE_MODE) vif1Regs->stat.VGW = 0;
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}
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if (Path3progress == STOPPED_MODE) gifRegs->stat.clear(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
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if (Path3progress == STOPPED_MODE)
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{
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gifRegs->stat.clear(GIF_STAT_APATH3 | GIF_STAT_OPH);
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}
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if ((gif->qwc > 0) || (!gspath3done))
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{
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if (!dmacRegs->ctrl.DMAE)
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@ -94,8 +98,9 @@ __forceinline void gsInterrupt()
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}
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static u32 WRITERING_DMA(u32 *pMem, u32 qwc)
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{
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psHu32(GIF_STAT) |= GIF_STAT_APATH3 | GIF_STAT_OPH;
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{
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gifRegs->stat.APATH = GIF_APATH3;
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gifRegs->stat.OPH = 1;
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int size = mtgsThread.PrepDataPacket(GIF_PATH_3, pMem, qwc);
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u8* pgsmem = mtgsThread.GetDataPacketPtr();
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@ -490,7 +495,7 @@ void mfifoGIFtransfer(int qwc)
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{
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SPR_LOG("dmaIrq Set");
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gifstate = GIF_STATE_DONE;
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gifmfifoirq = TRUE;
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gifmfifoirq = true;
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}
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}
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@ -511,7 +516,12 @@ void mfifoGIFtransfer(int qwc)
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void gifMFIFOInterrupt()
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{
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mfifocycles = 0;
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if (Path3progress == STOPPED_MODE) psHu32(GIF_STAT)&= ~(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
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if (Path3progress == STOPPED_MODE)
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{
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gifRegs->stat.APATH = GIF_APATH_IDLE;
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gifRegs->stat.OPH = 0;
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}
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if ((spr0->chcr.STR) && (spr0->qwc == 0))
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{
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@ -188,7 +188,7 @@ __forceinline void SIF0Dma()
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if (eesifbusy[0]) // If EE SIF enabled and there's something to transfer
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{
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int size = sif0dma->qwc;
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if (dmacRegs->ctrl.STS == STS_SIF0) // STS == fromSIF0
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if (dmacRegs->ctrl.STS == STS_SIF0)
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{
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SIF_LOG("SIF0 stall control");
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}
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@ -217,7 +217,8 @@ __forceinline void SIF0Dma()
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if (sif0dma->qwc == 0)
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{
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// Stop if TIE & the IRQ are set, or at the end. (I'll try to convert this to use the tags code later.)
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if (((sif0dma->chcr._u32 & 0x80000080) == 0x80000080) || (sif0.end))
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//if (((sif0dma->chcr._u32 & 0x80000080) == 0x80000080) || (sif0.end))
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if ((sif0dma->chcr.TIE & Tag::IRQ(sif0dma->chcr._u32)) || sif0.end)
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{
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if (sif0.end)
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SIF_LOG(" EE SIF end");
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@ -242,11 +243,10 @@ __forceinline void SIF0Dma()
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// (tag[0] >> 28) & 3? Surely this is supposed to be (tag[0] >> 28) & 7? --arcum42
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if ((dmacRegs->ctrl.STS != NO_STS) && ((tag[0] >> 28) & 3) == 0)
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psHu32(DMAC_STADR) = sif0dma->madr + (sif0dma->qwc * 16);
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dmacRegs->stadr.ADDR = sif0dma->madr + (sif0dma->qwc * 16);
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sif0.chain = 1;
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if (tag[0] & 0x40000000) sif0.end = 1;
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done = false;
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}
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}
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}
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@ -263,7 +263,6 @@ __forceinline void SIF1Dma()
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{
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if (eesifbusy[1]) // If EE SIF1 is enabled
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{
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if (dmacRegs->ctrl.STD == STD_SIF1)
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SIF_LOG("SIF1 stall control"); // STD == fromSIF1
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@ -286,8 +285,6 @@ __forceinline void SIF1Dma()
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ptag = _dmaGetAddr(sif1dma, sif1dma->tadr, DMAC_SIF1);
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if (ptag == NULL) return;
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//_dmaGetAddr(sif1dma, *ptag, sif1dma->tadr, DMAC_SIF1);
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sif1dma->chcr._u32 = (sif1dma->chcr._u32 & 0xFFFF) | ((*ptag) & 0xFFFF0000); // Copy the tag
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sif1dma->qwc = (u16)ptag[0];
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@ -352,8 +349,6 @@ __forceinline void SIF1Dma()
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data = _dmaGetAddr(sif1dma, sif1dma->madr, DMAC_SIF1);
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if (data == NULL) return;
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//_dmaGetAddr(sif1dma, *data, sif1dma->madr, DMAC_SIF1);
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if (qwTransfer > (FIFO_SIF1_W - sif1.fifoSize) / 4) // Copy part of sif1dma into FIFO
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qwTransfer = (FIFO_SIF1_W - sif1.fifoSize) / 4;
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@ -451,6 +446,7 @@ __forceinline void dmaSIF0()
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psHu32(SBUS_F240) |= 0x2000;
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eesifbusy[0] = true;
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if (iopsifbusy[0])
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{
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FreezeXMMRegs(1);
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@ -474,6 +470,7 @@ __forceinline void dmaSIF1()
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psHu32(SBUS_F240) |= 0x4000;
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eesifbusy[1] = true;
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if (iopsifbusy[1])
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{
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FreezeXMMRegs(1);
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@ -635,6 +635,7 @@ void vifMFIFOInterrupt()
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vif1Regs->stat.INT = 1;
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hwIntcIrq(INTC_VIF1);
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--vif1.irq;
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if (vif1Regs->stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
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{
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vif1Regs->stat.FQC = 0; // FQC=0
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@ -645,12 +646,10 @@ void vifMFIFOInterrupt()
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if (vif1.done == false || vif1ch->qwc)
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{
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switch(vif1.inprogress & 1)
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{
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case 0: //Set up transfer
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if (vif1ch->tadr == spr0->madr)
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if (vif1ch->tadr == spr0->madr)
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{
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// Console.WriteLn("Empty 1");
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vifqwc = 0;
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@ -660,13 +659,14 @@ void vifMFIFOInterrupt()
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return;
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}
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mfifoVIF1transfer(0);
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if ((vif1ch->madr >= dmacRegs->rbor.ADDR) && (vif1ch->madr <= (dmacRegs->rbor.ADDR + dmacRegs->rbsr.RMSK)))
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CPU_INT(10, 0);
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else
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mfifoVIF1transfer(0);
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if ((vif1ch->madr >= dmacRegs->rbor.ADDR) && (vif1ch->madr <= (dmacRegs->rbor.ADDR + dmacRegs->rbsr.RMSK)))
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CPU_INT(10, 0);
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else
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CPU_INT(10, vif1ch->qwc * BIAS);
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return;
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case 1: //Transfer data
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mfifo_VIF1chain();
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CPU_INT(10, 0);
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@ -689,6 +689,5 @@ void vifMFIFOInterrupt()
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hwDmacIrq(DMAC_VIF1);
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VIF_LOG("vif mfifo dma end");
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vif1Regs->stat.FQC = 0; // FQC=0
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vif1Regs->stat.FQC = 0;
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}
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@ -123,7 +123,7 @@ struct GifPathStruct
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// and raise a gsIrq. If CSR is already *set*, then ignore all subsequent drawing operations
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// and writes to general purpose registers to the GS. (note: I'm pretty sure this includes
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// direct GS and GSreg accesses, as well as those coming through the GIFpath -- but that
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// behavior isn't confirmed yet). Privlidged writes are still active.
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// behavior isn't confirmed yet). Privileged writes are still active.
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//
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// Ignorance continues until the SIGNAL bit in CSR is manually cleared by the EE. And here's
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// the tricky part: the interrupt from the second SIGNAL is still pending, and should be
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@ -222,7 +222,7 @@ __forceinline bool GIFPath::StepReg()
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__forceinline u8 GIFPath::GetReg() { return regs[curreg]; }
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// unpack the registers - registers are stored as a sequence of 4 bit values in the
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// Unpack the registers - registers are stored as a sequence of 4 bit values in the
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// upper 64 bits of the GIFTAG. That sucks for us when handling partialized GIF packets
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// coming in from paths 2 and 3, so we unpack them into an 8 bit array here.
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//
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@ -393,7 +393,7 @@ void GIFPath_Reset()
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}
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// This is a hackfix tool provided for "canceling" the contents of the GIFpath when
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// invalid GIFdma states are encountered (tpyically needed for PATH3 only).
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// invalid GIFdma states are encountered (typically needed for PATH3 only).
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__forceinline void GIFPath_Clear( GIF_PATH pathidx )
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{
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memzero(s_gifPath.path[pathidx]);
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@ -662,7 +662,7 @@ static __forceinline s32 recExecuteBlock( s32 eeCycles )
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// We should be able to rely on GAS syntax (the register clobber list) as a
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// replacement for manual push/pop of unpreserved registers.
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//
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// EBP note: As I feared, EBP is "required" for C++ excepion handling in Linux, and trying
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// EBP note: As I feared, EBP is "required" for C++ exception handling in Linux, and trying
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// to issue a clobber specifier for it causes an error. We really need to find a way to
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// disable EBP regalloc in iCore. --air
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Loading…
Reference in New Issue