mirror of https://github.com/PCSX2/pcsx2.git
recoded RSQRT opcode.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@40 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
17b04bbd0c
commit
e096347d51
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@ -4225,8 +4225,8 @@ void recVUMI_SQRT( VURegs *VU, int info )
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SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (u32)const_clip); //So we do a cardinal sqrt
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x86SetJ8(pjmp);
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
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if (CHECK_EXTRA_OVERFLOW) // Clamp Infinities to Fmax
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SSE_MINSS_M32_to_XMM(EEREC_TEMP, (uptr)g_maxvals);
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SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
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vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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@ -4235,117 +4235,109 @@ void recVUMI_SQRT( VURegs *VU, int info )
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}
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PCSX2_ALIGNED16(u64 RSQRT_TEMP_XMM[2];)
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void recVUMI_RSQRT(VURegs *VU, int info)
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{
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int vftemp = ALLOCTEMPX86(MODE_8BITREG);
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u8* njmp;
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int t1reg;
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u32* ajmp32;
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u32* bjmp32;
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SysPrintf("RSQRT Opcode \n");
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if( _Ftf_ ) {
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SSE_MOVAPS_XMM_to_XMM(EEREC_TEMP, EEREC_T);
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_unpackVF_xyzw(EEREC_TEMP, EEREC_TEMP, _Ftf_);
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}
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else {
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if( _Ftf_ )
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_unpackVFSS_xyzw(EEREC_TEMP, EEREC_T, _Ftf_);
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else
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SSE_MOVSS_XMM_to_XMM(EEREC_TEMP, EEREC_T);
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}
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/* Check for negative divide */
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XOR32RtoR(vftemp, vftemp);
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SSE_MOVMSKPS_XMM_to_R32(vftemp, EEREC_TEMP);
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AND32ItoR(vftemp, 1); //Check sign
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njmp = JZ8(0); //Skip if none are
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//SysPrintf("Invalid RSQRT\n");
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x410); //Invalid Flag - Negative number sqrt
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SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (u32)const_clip); //So we do a cardinal sqrt
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x86SetJ8(njmp);
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ajmp32 = JZ32(0); //Skip if none are
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x410); //Invalid Flag - Negative number sqrt
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SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (u32)const_clip); //So we do a cardinal sqrt
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x86SetJ32(ajmp32);
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//SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (u32)const_clip);
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if (CHECK_EXTRA_OVERFLOW) // Clamp Infinities to Fmax
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SSE_MINSS_M32_to_XMM(EEREC_TEMP, (uptr)g_maxvals);
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if( _Fs_ == 0 ) {
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if( _Fsf_ == 3 ) {
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if(_Ft_ != 0 ||_Ftf_ == 3 )
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{
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//SysPrintf("_Fs_ = 0.3 _Ft_ != 0 || _Ft_ = 0.3 \n");
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SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP); //Dont use RSQRT, terrible accuracy
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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//SSE_MOVAPS_XMM_to_XMM(EEREC_TEMP, EEREC_S);
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_unpackVF_xyzw(EEREC_TEMP, EEREC_S, _Fsf_);
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SSE_DIVSS_M32_to_XMM(EEREC_TEMP, VU_VI_ADDR(REG_Q, 0));
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SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
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t1reg = _vuGetTempXMMreg(info);
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if( t1reg >= 0 )
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{
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SysPrintf("RSQRT Opcode Part 1 \n");
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// Ft can still be zero here! so we need to check if its zero and set the correct flag.
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SSE_XORPS_XMM_to_XMM(t1reg, t1reg); // Clear t1reg
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XOR32RtoR(vftemp, vftemp);
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SSE_CMPEQSS_XMM_to_XMM(t1reg, EEREC_TEMP); // Set all F's if each vector is zero
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SSE_MOVMSKPS_XMM_to_R32(vftemp, t1reg); // Move the sign bits of the previous calculation
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AND32ItoR( vftemp, 0x01 ); // Grab "Is Zero" bits from the previous calculation
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ajmp32 = JZ32(0); // Skip if none are
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x820); // Zero divide flag
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}
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else
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{
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//SysPrintf("FS0.3 / 0!\n");
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SSE_XORPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x820); //Zero divide (only when not 0/0)
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MOV32ItoM(VU_VI_ADDR(REG_Q, 0), 0x7f7fffff);
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_freeX86reg(vftemp);
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return;
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}
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}else {
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if(_Ft_ != 0 || _Ftf_ == 3) {
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//SysPrintf("FS = 0 FT != 0\n");
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//SSE_XORPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x820); //Zero divide (only when not 0/0)
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MOV32ItoM(VU_VI_ADDR(REG_Q, 0), 0x7f7fffff); // +MAX, no negative in here :p
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_freeX86reg(vftemp);
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return;
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}
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else
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{
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//SysPrintf("FS = 0 FT = 0!\n");
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x410); //Invalid Flag (only when 0/0)
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MOV32ItoM(VU_VI_ADDR(REG_Q, 0), 0);
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_freeX86reg(vftemp);
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return;
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}
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}
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}
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else {
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int t1reg;
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if( _Ft_ == 0 ) {
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if( _Ftf_ < 3 ) {
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//SysPrintf("FS != 0 FT = 0!\n");
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x410); //Invalid Flag (only when 0/0)
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SSE_MOVMSKPS_XMM_to_R32(vftemp, EEREC_S);
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SHL32ItoR(vftemp, 31); //Check sign
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OR32ItoR(vftemp, 0x7f7fffff);
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MOV32RtoM(VU_VI_ADDR(REG_Q, 0), vftemp);
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_freeX86reg(vftemp);
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return;
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}else {
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//SysPrintf("FS != 0 FT = 1!\n");
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x820); //Zero divide (only when not 0/0)
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MOV32ItoM(VU_VI_ADDR(REG_Q, 0), 0xff7fffff);
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_freeX86reg(vftemp);
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return;
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}
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}
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//SysPrintf("Normal RSQRT\n");
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SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
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t1reg = _vuGetTempXMMreg(info);
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if( t1reg >= 0 )
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{
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_unpackVFSS_xyzw(t1reg, EEREC_S, _Fsf_);
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SSE_DIVSS_XMM_to_XMM(t1reg, EEREC_TEMP);
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SSE_MOVAPS_XMM_to_XMM(EEREC_TEMP, t1reg);
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_freeXMMreg(t1reg);
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}
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else
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{
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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_unpackVFSS_xyzw(EEREC_TEMP, EEREC_S, _Fsf_);
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SSE_DIVSS_M32_to_XMM(EEREC_TEMP, VU_VI_ADDR(REG_Q, 0));
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}
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SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (uptr)&VU_Signed_Zero_Mask[0]);
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SSE_ORPS_M128_to_XMM(EEREC_TEMP, (uptr)&g_maxvals[0]); // If division by zero, then EEREC_TEMP = positive fmax
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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bjmp32 = JMP32(0);
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x86SetJ32(ajmp32);
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_unpackVFSS_xyzw(t1reg, EEREC_S, _Fsf_);
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if (CHECK_EXTRA_OVERFLOW) // Clamp Infinities
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vuFloat2(t1reg, t1reg, 0x8);
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SSE_DIVSS_XMM_to_XMM(t1reg, EEREC_TEMP);
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vuFloat2(t1reg, t1reg, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), t1reg);
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x86SetJ32(bjmp32);
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_freeXMMreg(t1reg);
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}
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else
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{
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SysPrintf("RSQRT Opcode Part 2 \n");
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for (t1reg = 0; ( (t1reg == EEREC_TEMP) || (t1reg == EEREC_S) ); t1reg++)
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; // Makes t1reg not be EEREC_TEMP or EEREC_S.
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SSE_MOVAPS_XMM_to_M128( (uptr)&RSQRT_TEMP_XMM[0], t1reg ); // backup data in t1reg to a temp address
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// Ft can still be zero here! so we need to check if its zero and set the correct flag.
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SSE_XORPS_XMM_to_XMM(t1reg, t1reg); // Clear t1reg
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XOR32RtoR(vftemp, vftemp);
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SSE_CMPEQSS_XMM_to_XMM(t1reg, EEREC_TEMP); // Set all F's if each vector is zero
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SSE_MOVMSKPS_XMM_to_R32(vftemp, t1reg); // Move the sign bits of the previous calculation
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AND32ItoR( vftemp, 0x01 ); // Grab "Is Zero" bits from the previous calculation
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ajmp32 = JZ32(0); // Skip if none are
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x820); // Zero divide flag
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_unpackVFSS_xyzw(EEREC_TEMP, EEREC_S, _Fsf_);
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SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (uptr)&VU_Signed_Zero_Mask[0]);
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SSE_ORPS_M128_to_XMM(EEREC_TEMP, (uptr)&g_maxvals[0]); // If division by zero, then EEREC_TEMP = positive fmax
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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bjmp32 = JMP32(0);
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x86SetJ32(ajmp32);
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_unpackVFSS_xyzw(t1reg, EEREC_S, _Fsf_);
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if (CHECK_EXTRA_OVERFLOW) // Clamp Infinities
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vuFloat2(t1reg, t1reg, 0x8);
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SSE_DIVSS_XMM_to_XMM(t1reg, EEREC_TEMP);
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vuFloat2(t1reg, t1reg, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), t1reg);
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x86SetJ32(bjmp32);
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SSE_MOVAPS_M128_to_XMM( t1reg, (uptr)&RSQRT_TEMP_XMM[0] ); // restore t1reg data
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}
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vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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_freeX86reg(vftemp);
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}
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