mirror of https://github.com/PCSX2/pcsx2.git
VIF MSCAL instructions wait on VU T-Bit stop (#3539)
* VIF MSCAL instructions wait on VU T-Bit stop Fixes: The Sims Spiderman 3 Sharks Tale Maybe some bits of Over the Hedge * Removed Spiderman 3 patches * Fix VIF DMA resuming when stalled on tag * Remove warning which doesn't really need to be there anymore
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@ -17082,20 +17082,10 @@ Serial = SLES-54723
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Name = Spider-Man 3
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Region = PAL-E
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Compat = 4
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[patches = 0C881B25]
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comment=Patch by Kozarovv
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// Fixes hang before loading level 2.
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patch=1,EE,0044bae4,word,000002ff
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[/patches]
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---------------------------------------------
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Serial = SLES-54724
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Name = Spider-Man 3
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Region = PAL-M4
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[patches = C529B0AD]
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comment=Patch by Kozarovv
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// Fixes hang before loading level 2.
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patch=1,EE,0044bae4,word,000002ff
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[/patches]
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---------------------------------------------
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Serial = SLES-54727
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Name = Naruto - Uzumaki Chronicles
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@ -19263,11 +19253,6 @@ Region = NTSC-K
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Serial = SLKA-25385
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Name = Spider-Man 3
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Region = NTSC-K
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[patches = B35F8AAE]
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comment=Patch by Kozarovv and Arapapa
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// Fixes hang before loading level 2.
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patch=1,EE,0044bc64,word,000002ff //400002ff
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[/patches]
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---------------------------------------------
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Serial = SLKA-25388
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Name = One Piece - Grand Adventure
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@ -34272,11 +34257,6 @@ Region = NTSC-J
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Serial = SLPS-25823
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Name = Spider-Man 3
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Region = NTSC-J
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[patches = 9295A3BE]
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comment=Patch by Kozarovv and Arapapa
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// Fixes hang before loading level 2.
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patch=1,EE,0044bde4,word,000002ff //400002ff
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[/patches]
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---------------------------------------------
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Serial = SLPS-25825
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Name = Zero no Tsukaima [Best Collection]
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@ -42254,11 +42234,6 @@ Serial = SLUS-21552
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Name = Spider-Man 3
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Region = NTSC-U
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Compat = 4
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[patches = 29873A0C]
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comment= Patch by Kozarovv
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// Fixes hang before loading level 2.
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patch=1,EE,0044bae4,word,000002ff
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[/patches]
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---------------------------------------------
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Serial = SLUS-21553
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Name = Lumines Plus
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@ -25,7 +25,7 @@ u32 g_vif0Cycles = 0;
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// because its vif stalling not the EE core...
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__fi void vif0FLUSH()
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{
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if(vif0Regs.stat.VEW)
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if (VU0.VI[REG_VPU_STAT].UL & 0x5) // T bit stop or Busy
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{
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vif0.waitforvu = true;
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vif0.vifstalled.enabled = VifStallEnable(vif0ch);
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@ -111,6 +111,7 @@ __fi void vif0SetupTransfer()
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if (!ret && vif0.irqoffset.enabled)
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{
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vif0.inprogress = 0; // Better clear this so it has to do it again (Jak 1)
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vif0ch.qwc = 0; // Gumball 3000 pauses the DMA when the tag stalls so we need to reset the QWC, it'll be gotten again later
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return; // IRQ set by VIFTransfer
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}
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@ -134,6 +135,12 @@ __fi void vif0SetupTransfer()
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__fi void vif0VUFinish()
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{
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if (VU0.VI[REG_VPU_STAT].UL & 0x4)
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{
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CPU_INT(VIF_VU0_FINISH, 128);
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return;
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}
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if ((VU0.VI[REG_VPU_STAT].UL & 1))
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{
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int _cycles = VU0.cycle;
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@ -294,7 +301,6 @@ void dmaVIF0()
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}
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else
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{
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if (vif0.irqoffset.enabled && !vif0.done) DevCon.Warning("Warning! VIF0 starting a new Chain transfer with vif offset set (Possible force stop?)");
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vif0.dmamode = VIF_CHAIN_MODE;
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vif0.done = false;
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vif0.inprogress &= ~0x1;
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@ -25,7 +25,7 @@ u32 g_vif1Cycles = 0;
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__fi void vif1FLUSH()
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{
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if(vif1Regs.stat.VEW)
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if (VU0.VI[REG_VPU_STAT].UL & 0x500) // T bit stop or Busy
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{
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vif1.waitforvu = true;
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vif1.vifstalled.enabled = VifStallEnable(vif1ch);
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@ -207,6 +207,7 @@ __fi void vif1SetupTransfer()
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if (!ret && vif1.irqoffset.enabled)
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{
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vif1.inprogress &= ~1; // Better clear this so it has to do it again (Jak 1)
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vif1ch.qwc = 0; // Gumball 3000 pauses the DMA when the tag stalls so we need to reset the QWC, it'll be gotten again later
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return; // IRQ set by VIFTransfer
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}
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}
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@ -230,6 +231,12 @@ __fi void vif1SetupTransfer()
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__fi void vif1VUFinish()
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{
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if (VU0.VI[REG_VPU_STAT].UL & 0x400)
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{
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CPU_INT(VIF_VU1_FINISH, 128);
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return;
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}
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if (VU0.VI[REG_VPU_STAT].UL & 0x100)
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{
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int _cycles = VU1.cycle;
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@ -471,10 +478,10 @@ void dmaVIF1()
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}
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else
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{
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if(vif1.irqoffset.enabled && !vif1.done) DevCon.Warning("Warning! VIF1 starting a new Chain transfer with vif offset set (Possible force stop?)");
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vif1.inprogress &= ~0x1;
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vif1.dmamode = VIF_CHAIN_MODE;
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vif1.done = false;
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vif1.inprogress &= ~0x1;
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}
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if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = std::min((u16)0x10, vif1ch.qwc);
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