mirror of https://github.com/PCSX2/pcsx2.git
FPU fixes:
tweaked the fpu compare clamping so now gt4 works again. made the digimon rumble arena 2 fix into a gamefix. tekken 5 doesn't need a gamefix anymore. VU fixes: fixed 2 opcodes thanks to nneeve. optimized FCOR a bit. changed the way ICO gamefix works so its less hacky (just always sets VI to 1 instead of setting VI to the opposite of the 'correct' result) General fix: there was some odd bug with the autogenerated TEXTINCLUDE stuff. if you edited a resource, it would generate #include "afxresmw.h instead of #include "afxresmw.h" (a quotation mark was missing so you'd get compile errors) so i fixed that ;p git-svn-id: http://pcsx2.googlecode.com/svn/trunk@563 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
4a8ba5cd40
commit
de2e939fcc
28
pcsx2/Misc.h
28
pcsx2/Misc.h
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@ -82,23 +82,23 @@ extern SessionOverrideFlags g_Session;
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#define CHECK_MULTIGS (Config.Options&PCSX2_GSMULTITHREAD)
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#define CHECK_EEREC (!g_Session.ForceDisableEErec && Config.Options&PCSX2_EEREC)
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//------------ SPEED/MISC HACKS!!! ---------------
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#define CHECK_EE_CYCLERATE (Config.Hacks & 0x03)
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#define CHECK_IOP_CYCLERATE (Config.Hacks & (1<<3))
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#define CHECK_WAITCYCLE_HACK (Config.Hacks & (1<<4))
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#define CHECK_INTC_STAT_HACK (Config.Hacks & (1<<5))
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#define CHECK_ESCAPE_HACK (Config.Hacks & 0x400)
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#define CHECK_EE_CYCLERATE (Config.Hacks & 0x03)
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#define CHECK_IOP_CYCLERATE (Config.Hacks & 0x08)
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#define CHECK_WAITCYCLE_HACK (Config.Hacks & 0x10)
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#define CHECK_INTC_STAT_HACK (Config.Hacks & 0x20)
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#define CHECK_ESCAPE_HACK (Config.Hacks & 0x400)
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//------------ SPECIAL GAME FIXES!!! ---------------
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#define CHECK_VUADDSUBHACK (Config.GameFixes & 0x1) // Special Fix for Tri-ace games, they use an encryption algorithm that requires VU addi opcode to be bit-accurate.
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#define CHECK_FPUCLAMPHACK (Config.GameFixes & 0x4) // Special Fix for Tekken 5, different clamping for FPU (sets NaN to zero; doesn't clamp infinities)
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#define CHECK_FCORHACK (Config.GameFixes & 0x8) // Special Fix for ICO, cures SPS due to some misscalculation of the clip flag.
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#define CHECK_VUADDSUBHACK (Config.GameFixes & 0x1) // Special Fix for Tri-ace games, they use an encryption algorithm that requires VU addi opcode to be bit-accurate.
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#define CHECK_FPUCOMPAREHACK (Config.GameFixes & 0x4) // Special Fix for Digimon Rumble Arena 2, fixes spinning/hanging on intro-menu.
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#define CHECK_FCORHACK (Config.GameFixes & 0x8) // Special Fix for ICO, cures SPS due to some misscalculation of the clip flag.
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//------------ Advanced Options!!! ---------------
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#define CHECK_VU_OVERFLOW (Config.vuOptions & 0x1)
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#define CHECK_VU_EXTRA_OVERFLOW (Config.vuOptions & 0x2) // If enabled, Operands are clamped before being used in the VU recs
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#define CHECK_VU_SIGN_OVERFLOW (Config.vuOptions & 0x4)
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#define CHECK_VU_UNDERFLOW (Config.vuOptions & 0x8)
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#define CHECK_VU_OVERFLOW (Config.vuOptions & 0x1)
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#define CHECK_VU_EXTRA_OVERFLOW (Config.vuOptions & 0x2) // If enabled, Operands are clamped before being used in the VU recs
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#define CHECK_VU_SIGN_OVERFLOW (Config.vuOptions & 0x4)
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#define CHECK_VU_UNDERFLOW (Config.vuOptions & 0x8)
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#define CHECK_VU_EXTRA_FLAGS 0 // Always disabled now // Sets correct flags in the VU recs
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#define CHECK_FPU_OVERFLOW (Config.eeOptions & 0x1)
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#define CHECK_FPU_EXTRA_OVERFLOW (Config.eeOptions & 0x2) // If enabled, Operands are checked for infinities before being used in the FPU recs
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#define CHECK_FPU_OVERFLOW (Config.eeOptions & 0x1)
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#define CHECK_FPU_EXTRA_OVERFLOW (Config.eeOptions & 0x2) // If enabled, Operands are checked for infinities before being used in the FPU recs
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#define CHECK_FPU_EXTRA_FLAGS 1 // Always enabled now // Sets D/I flags on FPU instructions
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#define DEFAULT_eeOptions 0x01
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#define DEFAULT_vuOptions 0x01
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@ -8,7 +8,6 @@
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// Generated from the TEXTINCLUDE 2 resource.
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//
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#include "afxresmw.h"
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/////////////////////////////////////////////////////////////////////////////
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#undef APSTUDIO_READONLY_SYMBOLS
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@ -84,11 +83,12 @@ BEGIN
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PUSHBUTTON "Cancel",IDCANCEL,139,99,50,14
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CTEXT "Some games need special settings.\nConfigure them here.",IDC_STATIC,7,7,264,17
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GROUPBOX "PCSX2 Gamefixes",IDC_STATIC,7,31,264,89
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CONTROL "FPU Clamp Hack - Special fix for Tekken 5.",IDC_GAMEFIX3,
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CONTROL "FPU Compare Hack - Special fix for Digimon Rumble Arena 2.",IDC_GAMEFIX3,
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"Button",BS_AUTOCHECKBOX | WS_TABSTOP,12,51,249,10
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CONTROL "VU Add / Sub Hack - Special fix for Tri-Ace games!",IDC_GAMEFIX2,
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"Button",BS_AUTOCHECKBOX | WS_TABSTOP,12,65,252,10
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CONTROL "VU FCOR Hack - Fixes ICO SPS",IDC_GAMEFIX7,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,12,79,252,10
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CONTROL "VU FCOR Hack - Special Fix for ICO SPS.",IDC_GAMEFIX7,
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"Button",BS_AUTOCHECKBOX | WS_TABSTOP,12,79,252,10
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END
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@ -1388,7 +1388,7 @@ END
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2 TEXTINCLUDE
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BEGIN
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"#include ""afxresmw.h\0"
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"#include ""afxresmw.h""\0"
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END
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3 TEXTINCLUDE
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@ -371,70 +371,61 @@ REC_FPUFUNC(RSQRT_S);
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//------------------------------------------------------------------
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// Clamp Functions (Converts NaN's and Infinities to Normal Numbers)
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//------------------------------------------------------------------
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void fpuFloat(int regd) { // +/-NaN -> +fMax, +Inf -> +fMax, -Inf -> -fMax
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if (CHECK_FPU_OVERFLOW && !CHECK_FPUCLAMPHACK) { // Tekken 5 doesn't like clamping infinities.
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PCSX2_ALIGNED16(u64 FPU_FLOAT_TEMP[2]);
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__forceinline void fpuFloat4(int regd) { // +NaN -> +fMax, -NaN -> -fMax, +Inf -> +fMax, -Inf -> -fMax
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int t1reg = _allocTempXMMreg(XMMT_FPS, -1);
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if (t1reg >= 0) {
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SSE_MOVSS_XMM_to_XMM(t1reg, regd);
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SSE_ANDPS_M128_to_XMM(t1reg, (uptr)&s_neg[0]);
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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SSE_ORPS_XMM_to_XMM(regd, t1reg);
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_freeXMMreg(t1reg);
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}
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else {
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Console::Error("fpuFloat2() allocation error");
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t1reg = (regd == 0) ? 1 : 0; // get a temp reg thats not regd
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SSE_MOVAPS_XMM_to_M128( (uptr)&FPU_FLOAT_TEMP[0], t1reg ); // backup data in t1reg to a temp address
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SSE_MOVSS_XMM_to_XMM(t1reg, regd);
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SSE_ANDPS_M128_to_XMM(t1reg, (uptr)&s_neg[0]);
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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SSE_ORPS_XMM_to_XMM(regd, t1reg);
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SSE_MOVAPS_M128_to_XMM( t1reg, (uptr)&FPU_FLOAT_TEMP[0] ); // restore t1reg data
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}
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}
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__forceinline void fpuFloat(int regd) { // +/-NaN -> +fMax, +Inf -> +fMax, -Inf -> -fMax
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if (CHECK_FPU_OVERFLOW) {
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]); // MIN() must be before MAX()! So that NaN's become +Maximum
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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}
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}
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PCSX2_ALIGNED16(u64 FPU_FLOAT_TEMP[2]);
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void fpuFloat2(int regd) { // +NaN -> +fMax, -NaN -> -fMax, +Inf -> +fMax, -Inf -> -fMax
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if (CHECK_FPU_OVERFLOW && !CHECK_FPUCLAMPHACK) { // Tekken 5 doesn't like clamping infinities.
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int t1reg = _allocTempXMMreg(XMMT_FPS, -1);
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if (t1reg >= 0) {
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SSE_MOVSS_XMM_to_XMM(t1reg, regd);
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SSE_ANDPS_M128_to_XMM(t1reg, (uptr)&s_neg[0]);
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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SSE_ORPS_XMM_to_XMM(regd, t1reg);
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_freeXMMreg(t1reg);
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}
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else {
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Console::Error("fpuFloat2() allocation error");
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t1reg = (regd == 0) ? 1 : 0; // get a temp reg thats not regd
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SSE_MOVAPS_XMM_to_M128( (uptr)&FPU_FLOAT_TEMP[0], t1reg ); // backup data in t1reg to a temp address
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SSE_MOVSS_XMM_to_XMM(t1reg, regd);
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SSE_ANDPS_M128_to_XMM(t1reg, (uptr)&s_neg[0]);
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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SSE_ORPS_XMM_to_XMM(regd, t1reg);
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SSE_MOVAPS_M128_to_XMM( t1reg, (uptr)&FPU_FLOAT_TEMP[0] ); // restore t1reg data
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}
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__forceinline void fpuFloat2(int regd) { // +NaN -> +fMax, -NaN -> -fMax, +Inf -> +fMax, -Inf -> -fMax
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if (CHECK_FPU_OVERFLOW) {
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fpuFloat4(regd);
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}
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}
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__forceinline void fpuFloat3(int regd) {
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// This clamp function used in the recC_xx opcodes
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// This clamp function is used in the recC_xx opcodes
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// Rule of Rose needs clamping or else it crashes (minss or maxss both fix the crash)
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// Tekken 5 has disappearing characters unless preserving NaN sign (fpuFloat4() preserves NaN sign).
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// Digimon Rumble Arena 2 needs MAXSS clamping (if you only use minss, it spins on the intro-menus;
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// it also doesn't like preserving NaN sign with fpuFloat2, so the only way to make Digimon work
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// it also doesn't like preserving NaN sign with fpuFloat4, so the only way to make Digimon work
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// is by calling MAXSS first)
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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//SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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if (CHECK_FPUCOMPAREHACK) {
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//SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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}
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else fpuFloat4(regd);
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}
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void ClampValues(int regd) {
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fpuFloat(regd);
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}
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void ClampValues2(int regd) {
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if (CHECK_FPUCLAMPHACK) { // Fixes Tekken 5 ( Makes NaN equal 0, infinities stay the same )
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int t5reg = _allocTempXMMreg(XMMT_FPS, -1);
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SSE_XORPS_XMM_to_XMM(t5reg, t5reg);
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SSE_CMPORDSS_XMM_to_XMM(t5reg, regd);
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SSE_ANDPS_XMM_to_XMM(regd, t5reg);
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/* --- Its odd but tekken dosn't like Infinities to be clamped. --- */
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//SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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//SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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_freeXMMreg(t5reg);
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}
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else fpuFloat(regd);
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}
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//------------------------------------------------------------------
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@ -639,7 +630,7 @@ int recCommutativeOp(int info, int regd, int op)
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void recADD_S_xmm(int info)
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{
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//AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO|FPUflagU)); // Clear O and U flags
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ClampValues2(recCommutativeOp(info, EEREC_D, 0));
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ClampValues(recCommutativeOp(info, EEREC_D, 0));
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//REC_FPUOP(ADD_S);
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}
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@ -1561,7 +1552,7 @@ void recSUBop(int info, int regd)
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break;
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}
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ClampValues2(regd);
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ClampValues(regd);
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_freeXMMreg(t0reg);
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}
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@ -1364,7 +1364,7 @@ void recVUMI_FMEQ( VURegs *VU, int info )
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if ( _Ft_ == 0 ) return;
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//SysPrintf("recVUMI_FMEQ \n");
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if( _Ft_ == _Fs_ ) {
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ftreg = ALLOCVI(_Ft_, MODE_WRITE|MODE_READ);//|MODE_8BITREG);
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ftreg = ALLOCVI(_Ft_, MODE_WRITE|MODE_READ|MODE_8BITREG);
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CMP16MtoR(ftreg, VU_VI_ADDR(REG_MAC_FLAG, 1));
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SETE8R(EAX);
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@ -1397,7 +1397,7 @@ void recVUMI_FMOR( VURegs *VU, int info )
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MOVZX32M16toR( ftreg, VU_VI_ADDR(REG_MAC_FLAG, 1) );
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}
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else if( _Ft_ == _Fs_ ) {
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ftreg = ALLOCVI(_Ft_, MODE_WRITE);//|MODE_READ|MODE_8BITREG);
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ftreg = ALLOCVI(_Ft_, MODE_WRITE|MODE_READ);//|MODE_8BITREG);
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OR16MtoR( ftreg, VU_VI_ADDR(REG_MAC_FLAG, 1) );
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}
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else {
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@ -1453,18 +1453,20 @@ void recVUMI_FCEQ( VURegs *VU, int info )
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//------------------------------------------------------------------
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void recVUMI_FCOR( VURegs *VU, int info )
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{
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int ftreg = ALLOCVI(1, MODE_WRITE|MODE_8BITREG);
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//SysPrintf("recVUMI_FCOR \n");
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MOV32MtoR( EAX, VU_VI_ADDR(REG_CLIP_FLAG, 1) );
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XOR32RtoR( ftreg, ftreg );
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OR32ItoR( EAX, VU->code );
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AND32ItoR( EAX, 0xffffff );
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CMP32ItoR( EAX, 0xffffff );
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if(CHECK_FCORHACK) //ICO Misscalculated CLIP flag (bits missing id guess)
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SETNZ8R(ftreg);
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else
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SETZ8R(ftreg);
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int ftreg;
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//SysPrintf("recVUMI_FCOR\n");
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if(CHECK_FCORHACK) {//ICO Miss-calculated CLIP flag so always set to true (probably a zerorec pipeline problem)
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ftreg = ALLOCVI(1, MODE_WRITE|MODE_8BITREG);
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MOV32ItoR( ftreg, 1 );
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}
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else {
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ftreg = ALLOCVI(1, MODE_WRITE);
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MOV32MtoR( ftreg, VU_VI_ADDR(REG_CLIP_FLAG, 1) );
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OR32ItoR ( ftreg, VU->code );
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AND32ItoR( ftreg, 0xffffff );
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ADD32ItoR( ftreg, 1 ); // If 24 1's will make 25th bit 1, else 0
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SHR32ItoR( ftreg, 24 ); // Get the 25th bit (also clears the rest of the garbage in the reg)
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}
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}
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//------------------------------------------------------------------
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