ShuriZma
/
pcsx2
mirror of https://github.com/PCSX2/pcsx2.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Switch a bunch of 64 bit #ifdef's to use the cross-platform 64-bit define I added into Pcsx2Defs.h.

This commit is contained in:
Shanoah Alkire 2019-06-18 22:08:43 -07:00
parent 43981f5981
commit de1717c1a1
9 changed files with 28 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
common/include/x86emitter/implement/jmpcall.h
View File

@ -58,7 +58,7 @@ struct xImpl_FastCall
// Type unsafety is nice
#ifdef __x86_64__
#ifdef __M_X86_64
#define XFASTCALL \
xCALL(f);
@ -90,7 +90,7 @@ struct xImpl_FastCall
void operator()(void *f, const xRegisterLong &a1 = xEmptyReg, const xRegisterLong &a2 = xEmptyReg) const
{
#ifdef __x86_64__
#ifdef __M_X86_64
if (a1.IsEmpty()) {
XFASTCALL;
} else if (a2.IsEmpty()) {
@ -114,7 +114,7 @@ struct xImpl_FastCall
{
void *f = (void *)func;
#ifdef __x86_64__
#ifdef __M_X86_64
XFASTCALL2;
#else
XFASTCALL2;
@ -126,7 +126,7 @@ struct xImpl_FastCall
{
void *f = (void *)func;
#ifdef __x86_64__
#ifdef __M_X86_64
XFASTCALL1;
#else
XFASTCALL1;
@ -138,7 +138,7 @@ struct xImpl_FastCall
{
void *f = (void *)func;
#ifdef __x86_64__
#ifdef __M_X86_64
XFASTCALL2;
#else
XFASTCALL2;
@ -150,7 +150,7 @@ struct xImpl_FastCall
{
void *f = (void *)func;
#ifdef __x86_64__
#ifdef __M_X86_64
XFASTCALL1;
#else
XFASTCALL1;
@ -159,7 +159,7 @@ struct xImpl_FastCall
void operator()(const xIndirect32 &f, const xRegisterLong &a1 = xEmptyReg, const xRegisterLong &a2 = xEmptyReg) const
{
#ifdef __x86_64__
#ifdef __M_X86_64
if (a1.IsEmpty()) {
XFASTCALL;
} else if (a2.IsEmpty()) {

2
common/include/x86emitter/instructions.h
View File

@ -86,7 +86,7 @@ extern const xImpl_Group8 xBTC;
extern const xImpl_BitScan xBSF, xBSR;
extern const xImpl_JmpCall xJMP;
#ifdef __x86_64__
#ifdef __M_X86_64
// 32 bits Call won't be compatible in 64 bits (different ABI)
// Just a reminder to port the code
[[deprecated]] extern const xImpl_JmpCall xCALL;

4
common/include/x86emitter/internal.h
View File

@ -120,7 +120,7 @@ __emitinline void xOpWriteC5(u8 prefix, u8 opcode, const T1 &param1, const T2 &p
const xRegisterInt &reg = param1.IsReg() ? param1 : param2;
#ifdef __x86_64__
#ifdef __M_X86_64
u8 nR = reg.IsExtended() ? 0x00 : 0x80;
#else
u8 nR = 0x80;
@ -149,7 +149,7 @@ __emitinline void xOpWriteC4(u8 prefix, u8 mb_prefix, u8 opcode, const T1 &param
const xRegisterInt &reg = param1.IsReg() ? param1 : param2;
#ifdef __x86_64__
#ifdef __M_X86_64
u8 nR = reg.IsExtended() ? 0x00 : 0x80;
u8 nB = param3.IsExtended() ? 0x00 : 0x20;
u8 nX = 0x40; // likely unused so hardwired to disabled

6
common/include/x86emitter/x86types.h
View File

@ -15,7 +15,7 @@
#pragma once
#ifdef __x86_64__
#ifdef __M_X86_64
static const uint iREGCNT_XMM = 16;
static const uint iREGCNT_GPR = 16;
#else
@ -277,7 +277,7 @@ public:
bool IsSIMD() const { return GetOperandSize() == 16; }
// IsWide: return true if the register is 64 bits (requires a wide op on the rex prefix)
#ifdef __x86_64__
#ifdef __M_X86_64
bool IsWide() const
{
return GetOperandSize() == 8;
@ -464,7 +464,7 @@ public:
// more sense and allows the programmer a little more type protection if needed.
//
#ifdef __x86_64__
#ifdef __M_X86_64
#define xRegisterLong xRegister64
#else
#define xRegisterLong xRegister32

6
common/src/x86emitter/cpudetect.cpp
View File

@ -194,7 +194,7 @@ void x86capabilities::Identify()
u32 cmds;
//AMD 64 STUFF
#ifdef __x86_64__
#ifdef __M_X86_64
u32 x86_64_8BITBRANDID;
u32 x86_64_12BITBRANDID;
#endif
@ -226,7 +226,7 @@ void x86capabilities::Identify()
Model = (regs[0] >> 4) & 0xf;
FamilyID = (regs[0] >> 8) & 0xf;
TypeID = (regs[0] >> 12) & 0x3;
#ifdef __x86_64__
#ifdef __M_X86_64
x86_64_8BITBRANDID = regs[1] & 0xff;
#endif
Flags = regs[3];
@ -245,7 +245,7 @@ void x86capabilities::Identify()
if (cmds >= 0x80000001) {
cpuid(regs, 0x80000001);
#ifdef __x86_64__
#ifdef __M_X86_64
x86_64_12BITBRANDID = regs[1] & 0xfff;
#endif
EFlags2 = regs[2];

2
common/src/x86emitter/jmp.cpp
View File

@ -125,7 +125,7 @@ __emitinline void xJccKnownTarget(JccComparisonType comparison, const void *targ
s32 *bah = xJcc32(comparison);
sptr distance = (sptr)target - (sptr)xGetPtr();
#ifdef __x86_64__
#ifdef __M_X86_64
// This assert won't physically happen on x86 targets
pxAssertDev(distance >= -0x80000000LL && distance < 0x80000000LL, "Jump target is too far away, needs an indirect register");
#endif

4
common/src/x86emitter/movs.cpp
View File

@ -58,7 +58,7 @@ void xImpl_Mov::operator()(const xIndirectVoid &dest, const xRegisterInt &from)
if (from.IsAccumulator() && dest.Index.IsEmpty() && dest.Base.IsEmpty()) {
// FIXME: in 64 bits, it could be 8B whereas Displacement is limited to 4B normally
#ifdef __x86_64__
#ifdef __M_X86_64
pxAssert(0);
#endif
xOpAccWrite(from.GetPrefix16(), from.Is8BitOp() ? 0xa2 : 0xa3, from.Id, dest);
@ -75,7 +75,7 @@ void xImpl_Mov::operator()(const xRegisterInt &to, const xIndirectVoid &src) con
if (to.IsAccumulator() && src.Index.IsEmpty() && src.Base.IsEmpty()) {
// FIXME: in 64 bits, it could be 8B whereas Displacement is limited to 4B normally
#ifdef __x86_64__
#ifdef __M_X86_64
pxAssert(0);
#endif
xOpAccWrite(to.GetPrefix16(), to.Is8BitOp() ? 0xa0 : 0xa1, to, src);

2
common/src/x86emitter/simd.cpp
View File

@ -95,7 +95,7 @@ namespace x86Emitter
//
__emitinline void SimdPrefix(u8 prefix, u16 opcode)
{
#ifdef __x86_64__
#ifdef __M_X86_64
pxAssertMsg(prefix == 0, "REX prefix must be just before the opcode");
#endif
const bool is16BitOpcode = ((opcode & 0xff) == 0x38) || ((opcode & 0xff) == 0x3a);

16
common/src/x86emitter/x86emitter.cpp
View File

@ -205,7 +205,7 @@ const char *xRegisterBase::GetName()
return x86_regnames_gpr16[Id];
case 4:
return x86_regnames_gpr32[Id];
#ifdef __x86_64__
#ifdef __M_X86_64
case 8:
return x86_regnames_gpr64[Id];
#endif
@ -258,7 +258,7 @@ void EmitSibMagic(uint regfield, const void *address)
// We must make sure that the displacement is within the 32bit range
// Else we will fail out in a spectacular fashion
sptr displacement = (sptr)address;
#ifdef __x86_64__
#ifdef __M_X86_64
pxAssertDev(displacement >= -0x80000000LL && displacement < 0x80000000LL, "SIB target is too far away, needs an indirect register");
#endif
@ -372,7 +372,7 @@ void EmitSibMagic(const xRegisterBase &reg1, const xIndirectVoid &sib)
//////////////////////////////////////////////////////////////////////////////////////////
__emitinline static void EmitRex(bool w, bool r, bool x, bool b)
{
#ifdef __x86_64__
#ifdef __M_X86_64
u8 rex = 0x40 | (w << 3) | (r << 2) | (x << 1) | b;
if (rex != 0x40)
xWrite8(rex);
@ -581,7 +581,7 @@ xAddressVoid::xAddressVoid(const void *displacement)
Base = xEmptyReg;
Index = xEmptyReg;
Factor = 0;
#ifdef __x86_64__
#ifdef __M_X86_64
pxAssert(0);
//Displacement = (s32)displacement;
#else
@ -918,7 +918,7 @@ void xImpl_IncDec::operator()(const xRegisterInt &to) const
u8 regfield = isDec ? 1 : 0;
xOpWrite(to.GetPrefix16(), 0xfe, regfield, to);
} else {
#ifdef __x86_64__
#ifdef __M_X86_64
pxAssertMsg(0, "Single Byte INC/DEC aren't valid in 64 bits."
"You need to use the ModR/M form (FF/0 FF/1 opcodes)");
#endif
@ -1055,7 +1055,7 @@ __emitinline void xRestoreReg(const xRegisterSSE &dest)
// Helper object to handle ABI frame
#ifdef __GNUC__
#ifdef __x86_64__
#ifdef __M_X86_64
// GCC ensures/requires stack to be 16 bytes aligned (but when?)
#define ALIGN_STACK(v) xADD(rsp, v)
#else
@ -1077,7 +1077,7 @@ xScopedStackFrame::xScopedStackFrame(bool base_frame, bool save_base_pointer, in
m_save_base_pointer = save_base_pointer;
m_offset = offset;
#ifdef __x86_64__
#ifdef __M_X86_64
m_offset += 8; // Call stores the return address (4 bytes)
@ -1127,7 +1127,7 @@ xScopedStackFrame::~xScopedStackFrame()
{
ALIGN_STACK(16 - m_offset % 16);
#ifdef __x86_64__
#ifdef __M_X86_64
// Restore the register context
xPOP(r15);