mirror of https://github.com/PCSX2/pcsx2.git
pcsx2: sign compare mismatch 3/3
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@ -157,7 +157,7 @@ __ri bool hwMFIFOWrite(u32 addr, const u128* data, uint qwc)
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pxAssert((dmacRegs.rbor.ADDR & 15) == 0);
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pxAssert((dmacRegs.rbor.ADDR & 15) == 0);
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pxAssert((addr & 15) == 0);
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pxAssert((addr & 15) == 0);
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if(qwc > ((dmacRegs.rbsr.RMSK + 16) >> 4)) DevCon.Warning("MFIFO Write bigger than MFIFO! QWC=%x FifoSize=%x", qwc, ((dmacRegs.rbsr.RMSK + 16) >> 4));
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if(qwc > ((dmacRegs.rbsr.RMSK + 16u) >> 4u)) DevCon.Warning("MFIFO Write bigger than MFIFO! QWC=%x FifoSize=%x", qwc, ((dmacRegs.rbsr.RMSK + 16) >> 4));
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// DMAC Address resolution: FIFO can be placed anywhere in the *physical* memory map
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// DMAC Address resolution: FIFO can be placed anywhere in the *physical* memory map
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// for the PS2. Its probably a serious error for a PS2 app to have the buffer cross
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// for the PS2. Its probably a serious error for a PS2 app to have the buffer cross
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// valid/invalid page areas of ram, so realistically we only need to test the base address
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// valid/invalid page areas of ram, so realistically we only need to test the base address
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@ -395,7 +395,7 @@ static void intExecute()
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while (cpuRegs.pc != EELOAD_START);
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while (cpuRegs.pc != EELOAD_START);
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eeloadReplaceOSDSYS();
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eeloadReplaceOSDSYS();
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}
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}
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if (ElfEntry != -1) {
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if (ElfEntry != 0xFFFFFFFF) {
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do
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do
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execI();
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execI();
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while (cpuRegs.pc != ElfEntry);
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while (cpuRegs.pc != ElfEntry);
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@ -71,7 +71,7 @@ REC_FUNC(SQC2);
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__aligned16 u64 retValues[2];
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__aligned16 u64 retValues[2];
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void _eeOnLoadWrite(int reg)
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void _eeOnLoadWrite(u32 reg)
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{
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{
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int regt;
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int regt;
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@ -106,7 +106,7 @@ void eeRecompileCode0(R5900FNPTR constcode, R5900FNPTR_INFO constscode, R5900FNP
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_addNeededGPRtoXMMreg(_Rt_);
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_addNeededGPRtoXMMreg(_Rt_);
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if( GPR_IS_CONST1(_Rs_) || GPR_IS_CONST1(_Rt_) ) {
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if( GPR_IS_CONST1(_Rs_) || GPR_IS_CONST1(_Rt_) ) {
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int creg = GPR_IS_CONST1(_Rs_) ? _Rs_ : _Rt_;
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u32 creg = GPR_IS_CONST1(_Rs_) ? _Rs_ : _Rt_;
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int vreg = creg == _Rs_ ? _Rt_ : _Rs_;
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int vreg = creg == _Rs_ ? _Rt_ : _Rs_;
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// if(g_pCurInstInfo->regs[vreg]&EEINST_XMM) {
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// if(g_pCurInstInfo->regs[vreg]&EEINST_XMM) {
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@ -602,7 +602,7 @@ bool ZZshLoadExtraEffects()
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SHADERHEADER* header;
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SHADERHEADER* header;
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bool bLoadSuccess = true;
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bool bLoadSuccess = true;
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const int vsshaders[4] = { SH_REGULARVS, SH_TEXTUREVS, SH_REGULARFOGVS, SH_TEXTUREFOGVS };
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const u32 vsshaders[4] = { SH_REGULARVS, SH_TEXTUREVS, SH_REGULARFOGVS, SH_TEXTUREFOGVS };
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for(int i = 0; i < 4; ++i) {
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for(int i = 0; i < 4; ++i) {
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LOAD_VS(vsshaders[i], pvs[2*i]);
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LOAD_VS(vsshaders[i], pvs[2*i]);
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@ -690,7 +690,7 @@ FRAGMENTSHADER* ZZshLoadShadeEffect(int type, int texfilter, int fog, int testae
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else
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else
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texwrap = TEXWRAP_REPEAT_CLAMP;
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texwrap = TEXWRAP_REPEAT_CLAMP;
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int index = GET_SHADER_INDEX(type, texfilter, texwrap, fog, s_bWriteDepth, testaem, exactcolor, context, 0);
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u32 index = GET_SHADER_INDEX(type, texfilter, texwrap, fog, s_bWriteDepth, testaem, exactcolor, context, 0);
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assert( index < ArraySize(ppsTexture) );
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assert( index < ArraySize(ppsTexture) );
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FRAGMENTSHADER* pf = ppsTexture+index;
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FRAGMENTSHADER* pf = ppsTexture+index;
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