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pcsx2
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Clang Format: cache.cpp and vtlb.cpp

This commit is contained in:
Ty Lamontagne 2024-06-25 11:36:12 -04:00 committed by refractionpcsx2
parent d47cdfba2d
commit dbfd506c8a
2 changed files with 119 additions and 121 deletions
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20
pcsx2/Cache.cpp
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@ -156,7 +156,7 @@ namespace
};
static Cache cache = {};
}
} // namespace
void resetCache()
{
@ -165,8 +165,7 @@ void resetCache()
static bool findInCache(const CacheSet& set, uptr ppf, int* way)
{
auto check = [&](int checkWay) -> bool
{
auto check = [&](int checkWay) -> bool {
if (!set.tags[checkWay].matches(ppf))
return false;
@ -349,7 +348,8 @@ void doCacheHitOp(u32 addr, const char* name, Op op)
op(cache.lineAt(index, way));
}
namespace R5900 {
namespace R5900
{
namespace Interpreter
{
namespace OpcodeImpl
@ -364,23 +364,20 @@ void CACHE()
switch (_Rt_)
{
case 0x1a: //DHIN (Data Cache Hit Invalidate)
doCacheHitOp(addr, "DHIN", [](CacheLine line)
{
doCacheHitOp(addr, "DHIN", [](CacheLine line) {
line.clear();
});
break;
case 0x18: //DHWBIN (Data Cache Hit WriteBack with Invalidate)
doCacheHitOp(addr, "DHWBIN", [](CacheLine line)
{
doCacheHitOp(addr, "DHWBIN", [](CacheLine line) {
line.writeBackIfNeeded();
line.clear();
});
break;
case 0x1c: //DHWOIN (Data Cache Hit WriteBack Without Invalidate)
doCacheHitOp(addr, "DHWOIN", [](CacheLine line)
{
doCacheHitOp(addr, "DHWOIN", [](CacheLine line) {
line.writeBackIfNeeded();
});
break;
@ -484,4 +481,5 @@ void CACHE()
}
} // end namespace OpcodeImpl
}}
} // namespace Interpreter
} // namespace R5900