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Apparently the MSB of integer register specifications in VU micro instructions is ignored, making the upper 16 registers mirror the lower 16. Changed all relevant instructions to reflect this. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1132 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
sudonim1 2009-05-04 18:21:44 +00:00
parent 8ab8adabf1
commit db41e52940
8 changed files with 531 additions and 513 deletions
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4
pcsx2/DebugTools/DisR5900.cpp
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@ -470,8 +470,8 @@ MakeDisF(disCVTSw, dName("CVTSw"); dCP132(_Fd_); dCP132(_Fs_);)
* Format: OP rt, offset(base) * * Format: OP rt, offset(base) *
*********************************************************/ *********************************************************/
MakeDisF(disLWC1, dName("LWC1"); dCP132(_Rt_); dOffset();) MakeDisF(disLWC1, dName("LWC1"); dCP132(_Ft_); dOffset();)
MakeDisF(disSWC1, dName("SWC1"); dCP132(_Rt_); dOffset();) MakeDisF(disSWC1, dName("SWC1"); dCP132(_Ft_); dOffset();)
/********************************************************* /*********************************************************
* Conditional Move * * Conditional Move *

3
pcsx2/DebugTools/DisVU0Micro.cpp
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@ -40,6 +40,9 @@ typedef char* (*TdisR5900F)DisFInterface;
#define _Ft_ ((code >> 16) & 0x1F) // The rt part of the instruction register #define _Ft_ ((code >> 16) & 0x1F) // The rt part of the instruction register
#define _Fs_ ((code >> 11) & 0x1F) // The rd part of the instruction register #define _Fs_ ((code >> 11) & 0x1F) // The rd part of the instruction register
#define _Fd_ ((code >> 6) & 0x1F) // The sa part of the instruction register #define _Fd_ ((code >> 6) & 0x1F) // The sa part of the instruction register
#define _It_ (_Ft_ & 15)
#define _Is_ (_Fs_ & 15)
#define _Id_ (_Fd_ & 15)
#define dName(i) sprintf(ostr, "%s %-7s,", ostr, i) #define dName(i) sprintf(ostr, "%s %-7s,", ostr, i)
#define dNameU(i) { char op[256]; sprintf(op, "%s.%s%s%s%s", i, _X ? "x" : "", _Y ? "y" : "", _Z ? "z" : "", _W ? "w" : ""); sprintf(ostr, "%s %-7s,", ostr, op); } #define dNameU(i) { char op[256]; sprintf(op, "%s.%s%s%s%s", i, _X ? "x" : "", _Y ? "y" : "", _Z ? "z" : "", _W ? "w" : ""); sprintf(ostr, "%s %-7s,", ostr, op); }

3
pcsx2/DebugTools/DisVU1Micro.cpp
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@ -42,6 +42,9 @@ typedef char* (*TdisR5900F)DisFInterface;
#define _Ft_ ((code >> 16) & 0x1F) // The rt part of the instruction register #define _Ft_ ((code >> 16) & 0x1F) // The rt part of the instruction register
#define _Fs_ ((code >> 11) & 0x1F) // The rd part of the instruction register #define _Fs_ ((code >> 11) & 0x1F) // The rd part of the instruction register
#define _Fd_ ((code >> 6) & 0x1F) // The sa part of the instruction register #define _Fd_ ((code >> 6) & 0x1F) // The sa part of the instruction register
#define _It_ (_Ft_ & 15)
#define _Is_ (_Fs_ & 15)
#define _Id_ (_Fd_ & 15)
#define dName(i) sprintf(ostr, "%s %-12s", ostr, i); \ #define dName(i) sprintf(ostr, "%s %-12s", ostr, i); \

78
pcsx2/DebugTools/DisVUops.h
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@ -26,55 +26,55 @@
MakeDisF(dis##VU##MI_DIV, dName("DIV"); dCP232f(_Fs_, _Fsf_); dCP232f(_Ft_, _Ftf_);) \ MakeDisF(dis##VU##MI_DIV, dName("DIV"); dCP232f(_Fs_, _Fsf_); dCP232f(_Ft_, _Ftf_);) \
MakeDisF(dis##VU##MI_SQRT, dName("SQRT"); dCP232f(_Ft_, _Ftf_);) \ MakeDisF(dis##VU##MI_SQRT, dName("SQRT"); dCP232f(_Ft_, _Ftf_);) \
MakeDisF(dis##VU##MI_RSQRT, dName("RSQRT"); dCP232f(_Fs_, _Fsf_); dCP232f(_Ft_, _Ftf_);) \ MakeDisF(dis##VU##MI_RSQRT, dName("RSQRT"); dCP232f(_Fs_, _Fsf_); dCP232f(_Ft_, _Ftf_);) \
MakeDisF(dis##VU##MI_IADDI, dName("IADDI"); dCP232i(_Ft_); dCP232i(_Fs_); dImm5();) \ MakeDisF(dis##VU##MI_IADDI, dName("IADDI"); dCP232i(_It_); dCP232i(_Is_); dImm5();) \
MakeDisF(dis##VU##MI_IADDIU, dName("IADDIU"); dCP232i(_Ft_); dCP232i(_Fs_); dImm15();) \ MakeDisF(dis##VU##MI_IADDIU, dName("IADDIU"); dCP232i(_It_); dCP232i(_Is_); dImm15();) \
MakeDisF(dis##VU##MI_IADD, dName("IADD"); dCP232i(_Fd_); dCP232i(_Fs_); dCP232i(_Ft_);) \ MakeDisF(dis##VU##MI_IADD, dName("IADD"); dCP232i(_Id_); dCP232i(_Is_); dCP232i(_It_);) \
MakeDisF(dis##VU##MI_IAND, dName("IAND"); dCP232i(_Fd_); dCP232i(_Fs_); dCP232i(_Ft_);) \ MakeDisF(dis##VU##MI_IAND, dName("IAND"); dCP232i(_Id_); dCP232i(_Is_); dCP232i(_It_);) \
MakeDisF(dis##VU##MI_IOR, dName("IOR"); dCP232i(_Fd_); dCP232i(_Fs_); dCP232i(_Ft_);) \ MakeDisF(dis##VU##MI_IOR, dName("IOR"); dCP232i(_Id_); dCP232i(_Is_); dCP232i(_It_);) \
MakeDisF(dis##VU##MI_ISUB, dName("ISUB"); dCP232i(_Fd_); dCP232i(_Fs_); dCP232i(_Ft_);) \ MakeDisF(dis##VU##MI_ISUB, dName("ISUB"); dCP232i(_Id_); dCP232i(_Is_); dCP232i(_It_);) \
MakeDisF(dis##VU##MI_ISUBIU, dName("ISUBIU"); dCP232i(_Ft_); dCP232i(_Fs_); dImm15();) \ MakeDisF(dis##VU##MI_ISUBIU, dName("ISUBIU"); dCP232i(_It_); dCP232i(_Is_); dImm15();) \
MakeDisF(dis##VU##MI_MOVE, if (_Fs_ == 0 && _Ft_ == 0) { dNameU("NOP"); } else { dNameU("MOVE"); dCP2128f(_Ft_); dCP2128f(_Fs_); }) \ MakeDisF(dis##VU##MI_MOVE, if (_Fs_ == 0 && _Ft_ == 0) { dNameU("NOP"); } else { dNameU("MOVE"); dCP2128f(_Ft_); dCP2128f(_Fs_); }) \
MakeDisF(dis##VU##MI_MFIR, dNameU("MFIR"); dCP2128f(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_MFIR, dNameU("MFIR"); dCP2128f(_Ft_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_MTIR, dNameU("MTIR"); dCP232i(_Ft_); dCP232f(_Fs_, _Fsf_);) \ MakeDisF(dis##VU##MI_MTIR, dNameU("MTIR"); dCP232i(_It_); dCP232f(_Fs_, _Fsf_);) \
MakeDisF(dis##VU##MI_MR32, dNameU("MR32"); dCP2128f(_Ft_); dCP2128f(_Fs_);) \ MakeDisF(dis##VU##MI_MR32, dNameU("MR32"); dCP2128f(_Ft_); dCP2128f(_Fs_);) \
MakeDisF(dis##VU##MI_LQ, dNameU("LQ"); dCP2128f(_Ft_); dCP232i(_Fs_); dImm11();) \ MakeDisF(dis##VU##MI_LQ, dNameU("LQ"); dCP2128f(_Ft_); dCP232i(_Is_); dImm11();) \
MakeDisF(dis##VU##MI_LQD, dNameU("LQD"); dCP2128f(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_LQD, dNameU("LQD"); dCP2128f(_Ft_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_LQI, dNameU("LQI"); dCP2128f(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_LQI, dNameU("LQI"); dCP2128f(_Ft_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_SQ, dNameU("SQ"); dCP2128f(_Fs_); dCP232i(_Ft_); dImm11(); ) \ MakeDisF(dis##VU##MI_SQ, dNameU("SQ"); dCP2128f(_Fs_); dCP232i(_It_); dImm11(); ) \
MakeDisF(dis##VU##MI_SQD, dNameU("SQD"); dCP2128f(_Fs_); dCP232i(_Ft_);) \ MakeDisF(dis##VU##MI_SQD, dNameU("SQD"); dCP2128f(_Fs_); dCP232i(_It_);) \
MakeDisF(dis##VU##MI_SQI, dNameU("SQI"); dCP2128f(_Fs_); dCP232i(_Ft_);) \ MakeDisF(dis##VU##MI_SQI, dNameU("SQI"); dCP2128f(_Fs_); dCP232i(_It_);) \
MakeDisF(dis##VU##MI_ILW, dNameU("ILW"); dCP232i(_Ft_); dImm11(); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_ILW, dNameU("ILW"); dCP232i(_It_); dImm11(); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_ISW, dNameU("ISW"); dCP232i(_Ft_); dImm11(); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_ISW, dNameU("ISW"); dCP232i(_It_); dImm11(); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_ILWR, dNameU("ILWR"); dCP232i(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_ILWR, dNameU("ILWR"); dCP232i(_It_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_ISWR, dNameU("ISWR"); dCP232i(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_ISWR, dNameU("ISWR"); dCP232i(_It_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_LOI, dName("LOI"); ) \ MakeDisF(dis##VU##MI_LOI, dName("LOI"); ) \
MakeDisF(dis##VU##MI_RINIT, dNameU("RINIT"); dCP232i(REG_R); dCP232f(_Fs_, _Fsf_);) \ MakeDisF(dis##VU##MI_RINIT, dNameU("RINIT"); dCP232i(REG_R); dCP232f(_Fs_, _Fsf_);) \
MakeDisF(dis##VU##MI_RGET, dNameU("RGET"); dCP232i(REG_R); dCP2128f(_Ft_);) \ MakeDisF(dis##VU##MI_RGET, dNameU("RGET"); dCP232i(REG_R); dCP2128f(_Ft_);) \
MakeDisF(dis##VU##MI_RNEXT, dNameU("RNEXT"); dCP232i(REG_R); dCP2128f(_Ft_);) \ MakeDisF(dis##VU##MI_RNEXT, dNameU("RNEXT"); dCP232i(REG_R); dCP2128f(_Ft_);) \
MakeDisF(dis##VU##MI_RXOR, dNameU("RXOR"); dCP232i(REG_R); dCP232f(_Fs_, _Fsf_);) \ MakeDisF(dis##VU##MI_RXOR, dNameU("RXOR"); dCP232i(REG_R); dCP232f(_Fs_, _Fsf_);) \
MakeDisF(dis##VU##MI_WAITQ, dName("WAITQ"); ) \ MakeDisF(dis##VU##MI_WAITQ, dName("WAITQ"); ) \
MakeDisF(dis##VU##MI_FSAND, dName("FSAND"); dCP232i(_Ft_); dCP232i(REG_STATUS_FLAG); sprintf(ostr, "%s %.3x,", ostr, code&0xfff); ) \ MakeDisF(dis##VU##MI_FSAND, dName("FSAND"); dCP232i(_It_); dCP232i(REG_STATUS_FLAG); sprintf(ostr, "%s %.3x,", ostr, code&0xfff); ) \
MakeDisF(dis##VU##MI_FSEQ, dName("FSEQ"); dCP232i(_Ft_); dCP232i(REG_STATUS_FLAG); sprintf(ostr, "%s %.3x,", ostr, code&0xfff);) \ MakeDisF(dis##VU##MI_FSEQ, dName("FSEQ"); dCP232i(_It_); dCP232i(REG_STATUS_FLAG); sprintf(ostr, "%s %.3x,", ostr, code&0xfff);) \
MakeDisF(dis##VU##MI_FSOR, dName("FSOR"); dCP232i(_Ft_); dCP232i(REG_STATUS_FLAG); sprintf(ostr, "%s %.3x,", ostr, code&0xfff);) \ MakeDisF(dis##VU##MI_FSOR, dName("FSOR"); dCP232i(_It_); dCP232i(REG_STATUS_FLAG); sprintf(ostr, "%s %.3x,", ostr, code&0xfff);) \
MakeDisF(dis##VU##MI_FSSET, dName("FSSET"); dCP232i(REG_STATUS_FLAG);) \ MakeDisF(dis##VU##MI_FSSET, dName("FSSET"); dCP232i(REG_STATUS_FLAG);) \
MakeDisF(dis##VU##MI_FMAND, dName("FMAND"); dCP232i(_Ft_); dCP232i(REG_MAC_FLAG); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_FMAND, dName("FMAND"); dCP232i(_It_); dCP232i(REG_MAC_FLAG); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_FMEQ, dName("FMEQ"); dCP232i(_Ft_); dCP232i(REG_MAC_FLAG); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_FMEQ, dName("FMEQ"); dCP232i(_It_); dCP232i(REG_MAC_FLAG); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_FMOR, dName("FMOR"); dCP232i(_Ft_); dCP232i(REG_MAC_FLAG); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_FMOR, dName("FMOR"); dCP232i(_It_); dCP232i(REG_MAC_FLAG); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_FCAND, dName("FCAND"); dCP232i(1); sprintf(ostr, "%s %8.8x,", ostr, code&0xffffff); ) \ MakeDisF(dis##VU##MI_FCAND, dName("FCAND"); dCP232i(1); sprintf(ostr, "%s %8.8x,", ostr, code&0xffffff); ) \
MakeDisF(dis##VU##MI_FCEQ, dName("FCEQ"); dCP232i(1); dCP232i(REG_CLIP_FLAG);) \ MakeDisF(dis##VU##MI_FCEQ, dName("FCEQ"); dCP232i(1); dCP232i(REG_CLIP_FLAG);) \
MakeDisF(dis##VU##MI_FCOR, dName("FCOR"); dCP232i(1); dCP232i(REG_CLIP_FLAG);) \ MakeDisF(dis##VU##MI_FCOR, dName("FCOR"); dCP232i(1); dCP232i(REG_CLIP_FLAG);) \
MakeDisF(dis##VU##MI_FCSET, dName("FCSET"); dCP232i(REG_CLIP_FLAG); sprintf(ostr, "%s %.6x,", ostr, code&0xffffff); ) \ MakeDisF(dis##VU##MI_FCSET, dName("FCSET"); dCP232i(REG_CLIP_FLAG); sprintf(ostr, "%s %.6x,", ostr, code&0xffffff); ) \
MakeDisF(dis##VU##MI_FCGET, dName("FCGET"); dCP232i(_Ft_); dCP232i(REG_CLIP_FLAG);) \ MakeDisF(dis##VU##MI_FCGET, dName("FCGET"); dCP232i(_It_); dCP232i(REG_CLIP_FLAG);) \
MakeDisF(dis##VU##MI_IBEQ, dName("IBEQ"); dImm11(); dCP232i(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_IBEQ, dName("IBEQ"); dImm11(); dCP232i(_It_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_IBGEZ, dName("IBEZ"); dImm11(); dCP232i(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_IBGEZ, dName("IBEZ"); dImm11(); dCP232i(_It_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_IBGTZ, dName("IBGTZ"); dImm11(); dCP232i(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_IBGTZ, dName("IBGTZ"); dImm11(); dCP232i(_It_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_IBLEZ, dName("IBLEZ"); dImm11(); dCP232i(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_IBLEZ, dName("IBLEZ"); dImm11(); dCP232i(_It_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_IBLTZ, dName("IBLTZ"); dImm11(); dCP232i(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_IBLTZ, dName("IBLTZ"); dImm11(); dCP232i(_It_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_IBNE, dName("IBNE"); dImm11(); dCP232i(_Ft_); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_IBNE, dName("IBNE"); dImm11(); dCP232i(_It_); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_B, dName("B"); dImm11();) \ MakeDisF(dis##VU##MI_B, dName("B"); dImm11();) \
MakeDisF(dis##VU##MI_BAL, dName("BAL"); dImm11(); dCP232i(_Ft_);) \ MakeDisF(dis##VU##MI_BAL, dName("BAL"); dImm11(); dCP232i(_It_);) \
MakeDisF(dis##VU##MI_JR, dName("JR"); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_JR, dName("JR"); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_JALR, dName("JALR"); dCP232i(_Ft_); dCP232i(_Fs_); ) \ MakeDisF(dis##VU##MI_JALR, dName("JALR"); dCP232i(_It_); dCP232i(_Is_); ) \
MakeDisF(dis##VU##MI_MFP, dNameU("MFP"); dCP2128f(_Ft_); dCP232i(REG_P);) \ MakeDisF(dis##VU##MI_MFP, dNameU("MFP"); dCP2128f(_Ft_); dCP232i(REG_P);) \
MakeDisF(dis##VU##MI_WAITP, dName("WAITP"); ) \ MakeDisF(dis##VU##MI_WAITP, dName("WAITP"); ) \
MakeDisF(dis##VU##MI_ESADD, dName("ESADD"); dCP2128f(_Fs_);) \ MakeDisF(dis##VU##MI_ESADD, dName("ESADD"); dCP2128f(_Fs_);) \
@ -83,16 +83,16 @@ MakeDisF(dis##VU##MI_ELENG, dName("ELENG"); dCP2128f(_Fs_); ) \
MakeDisF(dis##VU##MI_ERLENG, dName("ERLENG"); dCP2128f(_Fs_); ) \ MakeDisF(dis##VU##MI_ERLENG, dName("ERLENG"); dCP2128f(_Fs_); ) \
MakeDisF(dis##VU##MI_EATANxy, dName("EATANxy"); dCP2128f(_Fs_);) \ MakeDisF(dis##VU##MI_EATANxy, dName("EATANxy"); dCP2128f(_Fs_);) \
MakeDisF(dis##VU##MI_EATANxz, dName("EATANxz"); dCP2128f(_Fs_);) \ MakeDisF(dis##VU##MI_EATANxz, dName("EATANxz"); dCP2128f(_Fs_);) \
MakeDisF(dis##VU##MI_ESUM, dName("ESUM"); dCP232i(_Fs_); ) \ MakeDisF(dis##VU##MI_ESUM, dName("ESUM"); dCP2128f(_Fs_); ) \
MakeDisF(dis##VU##MI_ERCPR, dName("ERCPR"); dCP232f(_Fs_, _Fsf_); ) \ MakeDisF(dis##VU##MI_ERCPR, dName("ERCPR"); dCP232f(_Fs_, _Fsf_); ) \
MakeDisF(dis##VU##MI_ESQRT, dName("ESQRT"); dCP232f(_Fs_, _Fsf_); ) \ MakeDisF(dis##VU##MI_ESQRT, dName("ESQRT"); dCP232f(_Fs_, _Fsf_); ) \
MakeDisF(dis##VU##MI_ERSQRT, dName("ERSQRT"); dCP232f(_Fs_, _Fsf_); ) \ MakeDisF(dis##VU##MI_ERSQRT, dName("ERSQRT"); dCP232f(_Fs_, _Fsf_); ) \
MakeDisF(dis##VU##MI_ESIN, dName("ESIN"); dCP232f(_Fs_, _Fsf_); ) \ MakeDisF(dis##VU##MI_ESIN, dName("ESIN"); dCP232f(_Fs_, _Fsf_); ) \
MakeDisF(dis##VU##MI_EATAN, dName("EATAN"); dCP232f(_Fs_, _Fsf_); ) \ MakeDisF(dis##VU##MI_EATAN, dName("EATAN"); dCP232f(_Fs_, _Fsf_); ) \
MakeDisF(dis##VU##MI_EEXP, dName("EEXP"); dCP232f(_Fs_, _Fsf_); ) \ MakeDisF(dis##VU##MI_EEXP, dName("EEXP"); dCP232f(_Fs_, _Fsf_); ) \
MakeDisF(dis##VU##MI_XITOP, dName("XITOP"); dCP232i(_Ft_);) \ MakeDisF(dis##VU##MI_XITOP, dName("XITOP"); dCP232i(_It_);) \
MakeDisF(dis##VU##MI_XGKICK, dName("XGKICK"); dCP232i(_Fs_);) \ MakeDisF(dis##VU##MI_XGKICK, dName("XGKICK"); dCP232i(_Is_);) \
MakeDisF(dis##VU##MI_XTOP, dName("XTOP"); dCP232i(_Ft_);) \ MakeDisF(dis##VU##MI_XTOP, dName("XTOP"); dCP232i(_It_);) \
\ \
\ \
/*****************/ \ /*****************/ \

265
pcsx2/VUops.cpp
View File

@ -30,6 +30,9 @@
#define _Ft_ ((VU->code >> 16) & 0x1F) // The rt part of the instruction register #define _Ft_ ((VU->code >> 16) & 0x1F) // The rt part of the instruction register
#define _Fs_ ((VU->code >> 11) & 0x1F) // The rd part of the instruction register #define _Fs_ ((VU->code >> 11) & 0x1F) // The rd part of the instruction register
#define _Fd_ ((VU->code >> 6) & 0x1F) // The sa part of the instruction register #define _Fd_ ((VU->code >> 6) & 0x1F) // The sa part of the instruction register
#define _It_ (_Ft_ & 0xF)
#define _Is_ (_Fs_ & 0xF)
#define _Id_ (_Fd_ & 0xF)
#define _X ((VU->code>>24) & 0x1) #define _X ((VU->code>>24) & 0x1)
#define _Y ((VU->code>>23) & 0x1) #define _Y ((VU->code>>23) & 0x1)
@ -1508,38 +1511,38 @@ void _vuRSQRT(VURegs * VU) {
void _vuIADDI(VURegs * VU) { void _vuIADDI(VURegs * VU) {
s16 imm = ((VU->code >> 6) & 0x1f); s16 imm = ((VU->code >> 6) & 0x1f);
imm = ((imm & 0x10 ? 0xfff0 : 0) | (imm & 0xf)); imm = ((imm & 0x10 ? 0xfff0 : 0) | (imm & 0xf));
if(_Ft_ == 0) return; if(_It_ == 0) return;
VU->VI[_Ft_].SS[0] = VU->VI[_Fs_].SS[0] + imm; VU->VI[_It_].SS[0] = VU->VI[_Is_].SS[0] + imm;
}//last checked 17/05/03 shadow NOTE: not quite sure about that }//last checked 17/05/03 shadow NOTE: not quite sure about that
void _vuIADDIU(VURegs * VU) { void _vuIADDIU(VURegs * VU) {
if(_Ft_ == 0) return; if(_It_ == 0) return;
VU->VI[_Ft_].SS[0] = VU->VI[_Fs_].SS[0] + (((VU->code >> 10) & 0x7800) | (VU->code & 0x7ff)); VU->VI[_It_].SS[0] = VU->VI[_Is_].SS[0] + (((VU->code >> 10) & 0x7800) | (VU->code & 0x7ff));
}//last checked 17/05/03 shadow }//last checked 17/05/03 shadow
void _vuIADD(VURegs * VU) { void _vuIADD(VURegs * VU) {
if(_Fd_ == 0) return; if(_Id_ == 0) return;
VU->VI[_Fd_].SS[0] = VU->VI[_Fs_].SS[0] + VU->VI[_Ft_].SS[0]; VU->VI[_Id_].SS[0] = VU->VI[_Is_].SS[0] + VU->VI[_It_].SS[0];
}//last checked 17/05/03 shadow }//last checked 17/05/03 shadow
void _vuIAND(VURegs * VU) { void _vuIAND(VURegs * VU) {
if(_Fd_ == 0) return; if(_Id_ == 0) return;
VU->VI[_Fd_].US[0] = VU->VI[_Fs_].US[0] & VU->VI[_Ft_].US[0]; VU->VI[_Id_].US[0] = VU->VI[_Is_].US[0] & VU->VI[_It_].US[0];
}//last checked 17/05/03 shadow }//last checked 17/05/03 shadow
void _vuIOR(VURegs * VU) { void _vuIOR(VURegs * VU) {
if(_Fd_ == 0) return; if(_Id_ == 0) return;
VU->VI[_Fd_].US[0] = VU->VI[_Fs_].US[0] | VU->VI[_Ft_].US[0]; VU->VI[_Id_].US[0] = VU->VI[_Is_].US[0] | VU->VI[_It_].US[0];
} }
void _vuISUB(VURegs * VU) { void _vuISUB(VURegs * VU) {
if(_Fd_ == 0) return; if(_Id_ == 0) return;
VU->VI[_Fd_].SS[0] = VU->VI[_Fs_].SS[0] - VU->VI[_Ft_].SS[0]; VU->VI[_Id_].SS[0] = VU->VI[_Is_].SS[0] - VU->VI[_It_].SS[0];
} }
void _vuISUBIU(VURegs * VU) { void _vuISUBIU(VURegs * VU) {
if(_Ft_ == 0) return; if(_It_ == 0) return;
VU->VI[_Ft_].SS[0] = VU->VI[_Fs_].SS[0] - (((VU->code >> 10) & 0x7800) | (VU->code & 0x7ff)); VU->VI[_It_].SS[0] = VU->VI[_Is_].SS[0] - (((VU->code >> 10) & 0x7800) | (VU->code & 0x7ff));
} }
void _vuMOVE(VURegs * VU) { void _vuMOVE(VURegs * VU) {
@ -1554,16 +1557,16 @@ void _vuMOVE(VURegs * VU) {
void _vuMFIR(VURegs * VU) { void _vuMFIR(VURegs * VU) {
if (_Ft_ == 0) return; if (_Ft_ == 0) return;
if (_X) VU->VF[_Ft_].SL[0] = (s32)VU->VI[_Fs_].SS[0]; if (_X) VU->VF[_Ft_].SL[0] = (s32)VU->VI[_Is_].SS[0];
if (_Y) VU->VF[_Ft_].SL[1] = (s32)VU->VI[_Fs_].SS[0]; if (_Y) VU->VF[_Ft_].SL[1] = (s32)VU->VI[_Is_].SS[0];
if (_Z) VU->VF[_Ft_].SL[2] = (s32)VU->VI[_Fs_].SS[0]; if (_Z) VU->VF[_Ft_].SL[2] = (s32)VU->VI[_Is_].SS[0];
if (_W) VU->VF[_Ft_].SL[3] = (s32)VU->VI[_Fs_].SS[0]; if (_W) VU->VF[_Ft_].SL[3] = (s32)VU->VI[_Is_].SS[0];
} }
// Big bug!!! mov from fs to ft not ft to fs. asadr // Big bug!!! mov from fs to ft not ft to fs. asadr
void _vuMTIR(VURegs * VU) { void _vuMTIR(VURegs * VU) {
if(_Ft_ == 0) return; if(_It_ == 0) return;
VU->VI[_Ft_].US[0] = *(u16*)&VU->VF[_Fs_].F[_Fsf_]; VU->VI[_It_].US[0] = *(u16*)&VU->VF[_Fs_].F[_Fsf_];
} }
void _vuMR32(VURegs * VU) { void _vuMR32(VURegs * VU) {
@ -1585,7 +1588,7 @@ void _vuLQ(VURegs * VU) {
if (_Ft_ == 0) return; if (_Ft_ == 0) return;
imm = (VU->code & 0x400) ? (VU->code & 0x3ff) | 0xfc00 : (VU->code & 0x3ff); imm = (VU->code & 0x400) ? (VU->code & 0x3ff) | 0xfc00 : (VU->code & 0x3ff);
addr = ((imm + VU->VI[_Fs_].SS[0]) * 16)& (VU == &VU1 ? 0x3fff : 0xfff); addr = ((imm + VU->VI[_Is_].SS[0]) * 16)& (VU == &VU1 ? 0x3fff : 0xfff);
ptr = (u32*)GET_VU_MEM(VU, addr); ptr = (u32*)GET_VU_MEM(VU, addr);
if (_X) VU->VF[_Ft_].UL[0] = ptr[0]; if (_X) VU->VF[_Ft_].UL[0] = ptr[0];
@ -1598,10 +1601,10 @@ void _vuLQD( VURegs * VU ) {
u32 addr; u32 addr;
u32 *ptr; u32 *ptr;
if (_Fs_ != 0) VU->VI[_Fs_].US[0]--; if (_Is_ != 0) VU->VI[_Is_].US[0]--;
if (_Ft_ == 0) return; if (_Ft_ == 0) return;
addr = (VU->VI[_Fs_].US[0] * 16) & (VU == &VU1 ? 0x3fff : 0xfff); addr = (VU->VI[_Is_].US[0] * 16) & (VU == &VU1 ? 0x3fff : 0xfff);
ptr = (u32*)GET_VU_MEM(VU, addr); ptr = (u32*)GET_VU_MEM(VU, addr);
if (_X) VU->VF[_Ft_].UL[0] = ptr[0]; if (_X) VU->VF[_Ft_].UL[0] = ptr[0];
if (_Y) VU->VF[_Ft_].UL[1] = ptr[1]; if (_Y) VU->VF[_Ft_].UL[1] = ptr[1];
@ -1614,14 +1617,14 @@ void _vuLQI(VURegs * VU) {
u32 addr; u32 addr;
u32 *ptr; u32 *ptr;
addr = (VU->VI[_Fs_].US[0] * 16)& (VU == &VU1 ? 0x3fff : 0xfff); addr = (VU->VI[_Is_].US[0] * 16)& (VU == &VU1 ? 0x3fff : 0xfff);
ptr = (u32*)GET_VU_MEM(VU, addr); ptr = (u32*)GET_VU_MEM(VU, addr);
if (_X) VU->VF[_Ft_].UL[0] = ptr[0]; if (_X) VU->VF[_Ft_].UL[0] = ptr[0];
if (_Y) VU->VF[_Ft_].UL[1] = ptr[1]; if (_Y) VU->VF[_Ft_].UL[1] = ptr[1];
if (_Z) VU->VF[_Ft_].UL[2] = ptr[2]; if (_Z) VU->VF[_Ft_].UL[2] = ptr[2];
if (_W) VU->VF[_Ft_].UL[3] = ptr[3]; if (_W) VU->VF[_Ft_].UL[3] = ptr[3];
} }
if (_Fs_ != 0) VU->VI[_Fs_].US[0]++; if (_Fs_ != 0) VU->VI[_Is_].US[0]++;
} }
/* addr is now signed. Asadr */ /* addr is now signed. Asadr */
@ -1631,7 +1634,7 @@ void _vuSQ(VURegs * VU) {
u32 *ptr; u32 *ptr;
imm = (VU->code & 0x400) ? (VU->code & 0x3ff) | 0xfc00 : (VU->code & 0x3ff); imm = (VU->code & 0x400) ? (VU->code & 0x3ff) | 0xfc00 : (VU->code & 0x3ff);
addr = ((imm + VU->VI[_Ft_].SS[0]) * 16)& (VU == &VU1 ? 0x3fff : 0xfff); addr = ((imm + VU->VI[_It_].SS[0]) * 16)& (VU == &VU1 ? 0x3fff : 0xfff);
ptr = (u32*)GET_VU_MEM(VU, addr); ptr = (u32*)GET_VU_MEM(VU, addr);
if (_X) ptr[0] = VU->VF[_Fs_].UL[0]; if (_X) ptr[0] = VU->VF[_Fs_].UL[0];
if (_Y) ptr[1] = VU->VF[_Fs_].UL[1]; if (_Y) ptr[1] = VU->VF[_Fs_].UL[1];
@ -1643,8 +1646,8 @@ void _vuSQD(VURegs * VU) {
u32 addr; u32 addr;
u32 *ptr; u32 *ptr;
if(_Ft_ != 0) VU->VI[_Ft_].US[0]--; if(_Ft_ != 0) VU->VI[_It_].US[0]--;
addr = (VU->VI[_Ft_].US[0] * 16)& (VU == &VU1 ? 0x3fff : 0xfff); addr = (VU->VI[_It_].US[0] * 16)& (VU == &VU1 ? 0x3fff : 0xfff);
ptr = (u32*)GET_VU_MEM(VU, addr); ptr = (u32*)GET_VU_MEM(VU, addr);
if (_X) ptr[0] = VU->VF[_Fs_].UL[0]; if (_X) ptr[0] = VU->VF[_Fs_].UL[0];
if (_Y) ptr[1] = VU->VF[_Fs_].UL[1]; if (_Y) ptr[1] = VU->VF[_Fs_].UL[1];
@ -1656,13 +1659,13 @@ void _vuSQI(VURegs * VU) {
u32 addr; u32 addr;
u32 *ptr; u32 *ptr;
addr = (VU->VI[_Ft_].US[0] * 16)& (VU == &VU1 ? 0x3fff : 0xfff); addr = (VU->VI[_It_].US[0] * 16)& (VU == &VU1 ? 0x3fff : 0xfff);
ptr = (u32*)GET_VU_MEM(VU, addr); ptr = (u32*)GET_VU_MEM(VU, addr);
if (_X) ptr[0] = VU->VF[_Fs_].UL[0]; if (_X) ptr[0] = VU->VF[_Fs_].UL[0];
if (_Y) ptr[1] = VU->VF[_Fs_].UL[1]; if (_Y) ptr[1] = VU->VF[_Fs_].UL[1];
if (_Z) ptr[2] = VU->VF[_Fs_].UL[2]; if (_Z) ptr[2] = VU->VF[_Fs_].UL[2];
if (_W) ptr[3] = VU->VF[_Fs_].UL[3]; if (_W) ptr[3] = VU->VF[_Fs_].UL[3];
if(_Ft_ != 0) VU->VI[_Ft_].US[0]++; if(_Ft_ != 0) VU->VI[_It_].US[0]++;
} }
/* addr now signed. asadr */ /* addr now signed. asadr */
@ -1670,15 +1673,15 @@ void _vuILW(VURegs * VU) {
s16 imm; s16 imm;
u16 addr; u16 addr;
u16 *ptr; u16 *ptr;
if (_Ft_ == 0) return; if (_It_ == 0) return;
imm = (VU->code & 0x400) ? (VU->code & 0x3ff) | 0xfc00 : (VU->code & 0x3ff); imm = (VU->code & 0x400) ? (VU->code & 0x3ff) | 0xfc00 : (VU->code & 0x3ff);
addr = ((imm + VU->VI[_Fs_].SS[0]) * 16)& (VU == &VU1 ? 0x3fff : 0xfff); addr = ((imm + VU->VI[_Is_].SS[0]) * 16)& (VU == &VU1 ? 0x3fff : 0xfff);
ptr = (u16*)GET_VU_MEM(VU, addr); ptr = (u16*)GET_VU_MEM(VU, addr);
if (_X) VU->VI[_Ft_].US[0] = ptr[0]; if (_X) VU->VI[_It_].US[0] = ptr[0];
if (_Y) VU->VI[_Ft_].US[0] = ptr[2]; if (_Y) VU->VI[_It_].US[0] = ptr[2];
if (_Z) VU->VI[_Ft_].US[0] = ptr[4]; if (_Z) VU->VI[_It_].US[0] = ptr[4];
if (_W) VU->VI[_Ft_].US[0] = ptr[6]; if (_W) VU->VI[_It_].US[0] = ptr[6];
} }
void _vuISW(VURegs * VU) { void _vuISW(VURegs * VU) {
@ -1687,37 +1690,37 @@ void _vuISW(VURegs * VU) {
u16 *ptr; u16 *ptr;
imm = (VU->code & 0x400) ? (VU->code & 0x3ff) | 0xfc00 : (VU->code & 0x3ff); imm = (VU->code & 0x400) ? (VU->code & 0x3ff) | 0xfc00 : (VU->code & 0x3ff);
addr = ((imm + VU->VI[_Fs_].SS[0]) * 16)& (VU == &VU1 ? 0x3fff : 0xfff); addr = ((imm + VU->VI[_Is_].SS[0]) * 16)& (VU == &VU1 ? 0x3fff : 0xfff);
ptr = (u16*)GET_VU_MEM(VU, addr); ptr = (u16*)GET_VU_MEM(VU, addr);
if (_X) { ptr[0] = VU->VI[_Ft_].US[0]; ptr[1] = 0; } if (_X) { ptr[0] = VU->VI[_It_].US[0]; ptr[1] = 0; }
if (_Y) { ptr[2] = VU->VI[_Ft_].US[0]; ptr[3] = 0; } if (_Y) { ptr[2] = VU->VI[_It_].US[0]; ptr[3] = 0; }
if (_Z) { ptr[4] = VU->VI[_Ft_].US[0]; ptr[5] = 0; } if (_Z) { ptr[4] = VU->VI[_It_].US[0]; ptr[5] = 0; }
if (_W) { ptr[6] = VU->VI[_Ft_].US[0]; ptr[7] = 0; } if (_W) { ptr[6] = VU->VI[_It_].US[0]; ptr[7] = 0; }
} }
void _vuILWR(VURegs * VU) { void _vuILWR(VURegs * VU) {
u32 addr; u32 addr;
u16 *ptr; u16 *ptr;
if (_Ft_ == 0) return; if (_It_ == 0) return;
addr = (VU->VI[_Fs_].US[0] * 16)& (VU == &VU1 ? 0x3fff : 0xfff); addr = (VU->VI[_Is_].US[0] * 16)& (VU == &VU1 ? 0x3fff : 0xfff);
ptr = (u16*)GET_VU_MEM(VU, addr); ptr = (u16*)GET_VU_MEM(VU, addr);
if (_X) VU->VI[_Ft_].US[0] = ptr[0]; if (_X) VU->VI[_It_].US[0] = ptr[0];
if (_Y) VU->VI[_Ft_].US[0] = ptr[2]; if (_Y) VU->VI[_It_].US[0] = ptr[2];
if (_Z) VU->VI[_Ft_].US[0] = ptr[4]; if (_Z) VU->VI[_It_].US[0] = ptr[4];
if (_W) VU->VI[_Ft_].US[0] = ptr[6]; if (_W) VU->VI[_It_].US[0] = ptr[6];
} }
void _vuISWR(VURegs * VU) { void _vuISWR(VURegs * VU) {
u32 addr; u32 addr;
u16 *ptr; u16 *ptr;
addr = (VU->VI[_Fs_].US[0] * 16) & (VU == &VU1 ? 0x3fff : 0xfff); addr = (VU->VI[_Is_].US[0] * 16) & (VU == &VU1 ? 0x3fff : 0xfff);
ptr = (u16*)GET_VU_MEM(VU, addr); ptr = (u16*)GET_VU_MEM(VU, addr);
if (_X) { ptr[0] = VU->VI[_Ft_].US[0]; ptr[1] = 0; } if (_X) { ptr[0] = VU->VI[_It_].US[0]; ptr[1] = 0; }
if (_Y) { ptr[2] = VU->VI[_Ft_].US[0]; ptr[3] = 0; } if (_Y) { ptr[2] = VU->VI[_It_].US[0]; ptr[3] = 0; }
if (_Z) { ptr[4] = VU->VI[_Ft_].US[0]; ptr[5] = 0; } if (_Z) { ptr[4] = VU->VI[_It_].US[0]; ptr[5] = 0; }
if (_W) { ptr[6] = VU->VI[_Ft_].US[0]; ptr[7] = 0; } if (_W) { ptr[6] = VU->VI[_It_].US[0]; ptr[7] = 0; }
} }
/* code contributed by _Riff_ /* code contributed by _Riff_
@ -1780,23 +1783,23 @@ void _vuWAITQ(VURegs * VU) {
void _vuFSAND(VURegs * VU) { void _vuFSAND(VURegs * VU) {
u16 imm; u16 imm;
imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff); imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff);
if(_Ft_ == 0) return; if(_It_ == 0) return;
VU->VI[_Ft_].US[0] = (VU->VI[REG_STATUS_FLAG].US[0] & 0xFFF) & imm; VU->VI[_It_].US[0] = (VU->VI[REG_STATUS_FLAG].US[0] & 0xFFF) & imm;
} }
void _vuFSEQ(VURegs * VU) { void _vuFSEQ(VURegs * VU) {
u16 imm; u16 imm;
imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff); imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff);
if(_Ft_ == 0) return; if(_It_ == 0) return;
if((VU->VI[REG_STATUS_FLAG].US[0] & 0xFFF) == imm) VU->VI[_Ft_].US[0] = 1; if((VU->VI[REG_STATUS_FLAG].US[0] & 0xFFF) == imm) VU->VI[_It_].US[0] = 1;
else VU->VI[_Ft_].US[0] = 0; else VU->VI[_It_].US[0] = 0;
} }
void _vuFSOR(VURegs * VU) { void _vuFSOR(VURegs * VU) {
u16 imm; u16 imm;
imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff); imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff);
if(_Ft_ == 0) return; if(_It_ == 0) return;
VU->VI[_Ft_].US[0] = (VU->VI[REG_STATUS_FLAG].US[0] & 0xFFF) | imm; VU->VI[_It_].US[0] = (VU->VI[REG_STATUS_FLAG].US[0] & 0xFFF) | imm;
} }
void _vuFSSET(VURegs * VU) { void _vuFSSET(VURegs * VU) {
@ -1806,19 +1809,19 @@ void _vuFSSET(VURegs * VU) {
} }
void _vuFMAND(VURegs * VU) { void _vuFMAND(VURegs * VU) {
if(_Ft_ == 0) return; if(_It_ == 0) return;
VU->VI[_Ft_].US[0] = VU->VI[_Fs_].US[0] & (VU->VI[REG_MAC_FLAG].UL & 0xFFFF); VU->VI[_It_].US[0] = VU->VI[_Is_].US[0] & (VU->VI[REG_MAC_FLAG].UL & 0xFFFF);
} }
void _vuFMEQ(VURegs * VU) { void _vuFMEQ(VURegs * VU) {
if(_Ft_ == 0) return; if(_It_ == 0) return;
if((VU->VI[REG_MAC_FLAG].UL & 0xFFFF) == VU->VI[_Fs_].US[0]){ if((VU->VI[REG_MAC_FLAG].UL & 0xFFFF) == VU->VI[_Is_].US[0]){
VU->VI[_Ft_].US[0] =1;} else { VU->VI[_Ft_].US[0] =0; } VU->VI[_It_].US[0] =1;} else { VU->VI[_It_].US[0] =0; }
} }
void _vuFMOR(VURegs * VU) { void _vuFMOR(VURegs * VU) {
if(_Ft_ == 0) return; if(_It_ == 0) return;
VU->VI[_Ft_].US[0] = (VU->VI[REG_MAC_FLAG].UL & 0xFFFF) | VU->VI[_Fs_].US[0]; VU->VI[_It_].US[0] = (VU->VI[REG_MAC_FLAG].UL & 0xFFFF) | VU->VI[_Is_].US[0];
} }
void _vuFCAND(VURegs * VU) { void _vuFCAND(VURegs * VU) {
@ -1843,8 +1846,8 @@ void _vuFCSET(VURegs * VU) {
} }
void _vuFCGET(VURegs * VU) { void _vuFCGET(VURegs * VU) {
if(_Ft_ == 0) return; if(_It_ == 0) return;
VU->VI[_Ft_].US[0] = VU->VI[REG_CLIP_FLAG].UL & 0x0FFF; VU->VI[_It_].US[0] = VU->VI[REG_CLIP_FLAG].UL & 0x0FFF;
} }
s32 _branchAddr(VURegs * VU) { s32 _branchAddr(VURegs * VU) {
@ -1859,42 +1862,42 @@ void _setBranch(VURegs * VU, u32 bpc) {
} }
void _vuIBEQ(VURegs * VU) { void _vuIBEQ(VURegs * VU) {
if (VU->VI[_Ft_].US[0] == VU->VI[_Fs_].US[0]) { if (VU->VI[_It_].US[0] == VU->VI[_Is_].US[0]) {
s32 bpc = _branchAddr(VU); s32 bpc = _branchAddr(VU);
_setBranch(VU, bpc); _setBranch(VU, bpc);
} }
} }
void _vuIBGEZ(VURegs * VU) { void _vuIBGEZ(VURegs * VU) {
if (VU->VI[_Fs_].SS[0] >= 0) { if (VU->VI[_Is_].SS[0] >= 0) {
s32 bpc = _branchAddr(VU); s32 bpc = _branchAddr(VU);
_setBranch(VU, bpc); _setBranch(VU, bpc);
} }
} }
void _vuIBGTZ(VURegs * VU) { void _vuIBGTZ(VURegs * VU) {
if (VU->VI[_Fs_].SS[0] > 0) { if (VU->VI[_Is_].SS[0] > 0) {
s32 bpc = _branchAddr(VU); s32 bpc = _branchAddr(VU);
_setBranch(VU, bpc); _setBranch(VU, bpc);
} }
} }
void _vuIBLEZ(VURegs * VU) { void _vuIBLEZ(VURegs * VU) {
if (VU->VI[_Fs_].SS[0] <= 0) { if (VU->VI[_Is_].SS[0] <= 0) {
s32 bpc = _branchAddr(VU); s32 bpc = _branchAddr(VU);
_setBranch(VU, bpc); _setBranch(VU, bpc);
} }
} }
void _vuIBLTZ(VURegs * VU) { void _vuIBLTZ(VURegs * VU) {
if (VU->VI[_Fs_].SS[0] < 0) { if (VU->VI[_Is_].SS[0] < 0) {
s32 bpc = _branchAddr(VU); s32 bpc = _branchAddr(VU);
_setBranch(VU, bpc); _setBranch(VU, bpc);
} }
} }
void _vuIBNE(VURegs * VU) { void _vuIBNE(VURegs * VU) {
if (VU->VI[_Ft_].US[0] != VU->VI[_Fs_].US[0]) { if (VU->VI[_It_].US[0] != VU->VI[_Is_].US[0]) {
s32 bpc = _branchAddr(VU); s32 bpc = _branchAddr(VU);
_setBranch(VU, bpc); _setBranch(VU, bpc);
} }
@ -1908,19 +1911,19 @@ void _vuB(VURegs * VU) {
void _vuBAL(VURegs * VU) { void _vuBAL(VURegs * VU) {
s32 bpc = _branchAddr(VU); s32 bpc = _branchAddr(VU);
if (_Ft_) VU->VI[_Ft_].US[0] = (VU->VI[REG_TPC].UL + 8)/8; if (_It_) VU->VI[_It_].US[0] = (VU->VI[REG_TPC].UL + 8)/8;
_setBranch(VU, bpc); _setBranch(VU, bpc);
} }
void _vuJR(VURegs * VU) { void _vuJR(VURegs * VU) {
u32 bpc = VU->VI[_Fs_].US[0] * 8; u32 bpc = VU->VI[_Is_].US[0] * 8;
_setBranch(VU, bpc); _setBranch(VU, bpc);
} }
void _vuJALR(VURegs * VU) { void _vuJALR(VURegs * VU) {
u32 bpc = VU->VI[_Fs_].US[0] * 8; u32 bpc = VU->VI[_Is_].US[0] * 8;
if (_Ft_) VU->VI[_Ft_].US[0] = (VU->VI[REG_TPC].UL + 8)/8; if (_It_) VU->VI[_It_].US[0] = (VU->VI[REG_TPC].UL + 8)/8;
_setBranch(VU, bpc); _setBranch(VU, bpc);
} }
@ -2039,14 +2042,14 @@ void _vuEEXP(VURegs * VU) {
} }
void _vuXITOP(VURegs * VU) { void _vuXITOP(VURegs * VU) {
if (_Ft_ == 0) return; if (_It_ == 0) return;
VU->VI[_Ft_].US[0] = VU->vifRegs->itop; VU->VI[_It_].US[0] = VU->vifRegs->itop;
} }
void _vuXGKICK(VURegs * VU) void _vuXGKICK(VURegs * VU)
{ {
u32* ptr = (u32*)GET_VU_MEM(VU, (VU->VI[_Fs_].US[0]*16) & (VU == &VU1 ? 0x3fff : 0xfff)); u32* ptr = (u32*)GET_VU_MEM(VU, (VU->VI[_Is_].US[0]*16) & (VU == &VU1 ? 0x3fff : 0xfff));
// int temp = 0x4000 - ((VU->VI[_Fs_].US[0]*16) & 0x3fff); // int temp = 0x4000 - ((VU->VI[_Is_].US[0]*16) & 0x3fff);
// u32 tempmem[0x8000]; // u32 tempmem[0x8000];
// flush all pipelines first (in the right order) // flush all pipelines first (in the right order)
@ -2056,14 +2059,14 @@ void _vuXGKICK(VURegs * VU)
/* memset(tempmem, 0, sizeof(tempmem)); /* memset(tempmem, 0, sizeof(tempmem));
memcpy(tempmem, ptr, temp); memcpy(tempmem, ptr, temp);
ptr = (u32*)GET_VU_MEM(VU, 0); ptr = (u32*)GET_VU_MEM(VU, 0);
memcpy(&tempmem[temp], ptr, ((VU->VI[_Fs_].US[0]*16) & 0x3fff)); memcpy(&tempmem[temp], ptr, ((VU->VI[_Is_].US[0]*16) & 0x3fff));
GSGIFTRANSFER1((u32*)&tempmem[0], 0); GSGIFTRANSFER1((u32*)&tempmem[0], 0);
} else*/ GSGIFTRANSFER1((u32*)VU->Mem, (VU->VI[_Fs_].US[0]*16) & 0x3fff); } else*/ GSGIFTRANSFER1((u32*)VU->Mem, (VU->VI[_Is_].US[0]*16) & 0x3fff);
} }
void _vuXTOP(VURegs * VU) { void _vuXTOP(VURegs * VU) {
if(_Ft_ == 0) return; if(_It_ == 0) return;
VU->VI[_Ft_].US[0] = (u16)VU->vifRegs->top; VU->VI[_It_].US[0] = (u16)VU->vifRegs->top;
} }
#define GET_VF0_FLAG(reg) (((reg)==0)?(1<<REG_VF0_FLAG):0) #define GET_VF0_FLAG(reg) (((reg)==0)?(1<<REG_VF0_FLAG):0)
@ -2198,8 +2201,8 @@ void _vuRegs##OP(VURegs * VU, _VURegsNum *VUregsn) { \
VUregsn->VFwrite = 0; \ VUregsn->VFwrite = 0; \
VUregsn->VFread0 = 0; \ VUregsn->VFread0 = 0; \
VUregsn->VFread1 = 0; \ VUregsn->VFread1 = 0; \
VUregsn->VIwrite = 1 << _Fd_; \ VUregsn->VIwrite = 1 << _Id_; \
VUregsn->VIread = (1 << _Fs_) | (1 << _Ft_); \ VUregsn->VIread = (1 << _Is_) | (1 << _It_); \
VUregsn->cycles = 0; \ VUregsn->cycles = 0; \
} }
@ -2209,8 +2212,8 @@ void _vuRegs##OP(VURegs * VU, _VURegsNum *VUregsn) { \
VUregsn->VFwrite = 0; \ VUregsn->VFwrite = 0; \
VUregsn->VFread0 = 0; \ VUregsn->VFread0 = 0; \
VUregsn->VFread1 = 0; \ VUregsn->VFread1 = 0; \
VUregsn->VIwrite = 1 << _Ft_; \ VUregsn->VIwrite = 1 << _It_; \
VUregsn->VIread = 1 << _Fs_; \ VUregsn->VIread = 1 << _Is_; \
VUregsn->cycles = 0; \ VUregsn->cycles = 0; \
} }
@ -2512,7 +2515,7 @@ void _vuRegsMFIR(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsMTIR(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsMTIR(VURegs * VU, _VURegsNum *VUregsn) {
@ -2521,7 +2524,7 @@ void _vuRegsMTIR(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = _Fs_; VUregsn->VFread0 = _Fs_;
VUregsn->VFr0xyzw= 1 << (3-_Fsf_); VUregsn->VFr0xyzw= 1 << (3-_Fsf_);
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = GET_VF0_FLAG(_Fs_); VUregsn->VIread = GET_VF0_FLAG(_Fs_);
} }
@ -2544,7 +2547,7 @@ void _vuRegsLQ(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsLQD(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsLQD(VURegs * VU, _VURegsNum *VUregsn) {
@ -2553,8 +2556,8 @@ void _vuRegsLQD(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwxyzw = _XYZW; VUregsn->VFwxyzw = _XYZW;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Fs_; VUregsn->VIwrite = 1 << _Is_;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsLQI(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsLQI(VURegs * VU, _VURegsNum *VUregsn) {
@ -2563,8 +2566,8 @@ void _vuRegsLQI(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwxyzw = _XYZW; VUregsn->VFwxyzw = _XYZW;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Fs_; VUregsn->VIwrite = 1 << _Is_;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsSQ(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsSQ(VURegs * VU, _VURegsNum *VUregsn) {
@ -2574,7 +2577,7 @@ void _vuRegsSQ(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFr0xyzw= _XYZW; VUregsn->VFr0xyzw= _XYZW;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = (1 << _Ft_)|GET_VF0_FLAG(_Fs_); VUregsn->VIread = 1 << _It_;
} }
void _vuRegsSQD(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsSQD(VURegs * VU, _VURegsNum *VUregsn) {
@ -2583,8 +2586,8 @@ void _vuRegsSQD(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = _Fs_; VUregsn->VFread0 = _Fs_;
VUregsn->VFr0xyzw= _XYZW; VUregsn->VFr0xyzw= _XYZW;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = (1 << _Ft_)|GET_VF0_FLAG(_Fs_); VUregsn->VIread = 1 << _It_;
} }
void _vuRegsSQI(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsSQI(VURegs * VU, _VURegsNum *VUregsn) {
@ -2593,8 +2596,8 @@ void _vuRegsSQI(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = _Fs_; VUregsn->VFread0 = _Fs_;
VUregsn->VFr0xyzw= _XYZW; VUregsn->VFr0xyzw= _XYZW;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = (1 << _Ft_)|GET_VF0_FLAG(_Fs_); VUregsn->VIread = 1 << _It_;
} }
void _vuRegsILW(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsILW(VURegs * VU, _VURegsNum *VUregsn) {
@ -2602,8 +2605,8 @@ void _vuRegsILW(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
VUregsn->cycles = 3; VUregsn->cycles = 3;
} }
@ -2613,7 +2616,7 @@ void _vuRegsISW(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = (1 << _Fs_) | (1 << _Ft_); VUregsn->VIread = (1 << _Is_) | (1 << _It_);
} }
void _vuRegsILWR(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsILWR(VURegs * VU, _VURegsNum *VUregsn) {
@ -2621,8 +2624,8 @@ void _vuRegsILWR(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = (1 << _Ft_); VUregsn->VIwrite = (1 << _It_);
VUregsn->VIread = (1 << _Fs_); VUregsn->VIread = (1 << _Is_);
VUregsn->cycles = 3; VUregsn->cycles = 3;
} }
@ -2632,7 +2635,7 @@ void _vuRegsISWR(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = (1 << _Fs_) | (1 << _Ft_); VUregsn->VIread = (1 << _Is_) | (1 << _It_);
} }
void _vuRegsRINIT(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsRINIT(VURegs * VU, _VURegsNum *VUregsn) {
@ -2689,7 +2692,7 @@ void _vuRegsFSAND(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = 1 << REG_STATUS_FLAG; VUregsn->VIread = 1 << REG_STATUS_FLAG;
} }
@ -2698,7 +2701,7 @@ void _vuRegsFSEQ(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = 1 << REG_STATUS_FLAG; VUregsn->VIread = 1 << REG_STATUS_FLAG;
} }
@ -2707,7 +2710,7 @@ void _vuRegsFSOR(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = 1 << REG_STATUS_FLAG; VUregsn->VIread = 1 << REG_STATUS_FLAG;
} }
@ -2725,8 +2728,8 @@ void _vuRegsFMAND(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = (1 << REG_MAC_FLAG) | (1 << _Fs_); VUregsn->VIread = (1 << REG_MAC_FLAG) | (1 << _Is_);
} }
void _vuRegsFMEQ(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsFMEQ(VURegs * VU, _VURegsNum *VUregsn) {
@ -2734,8 +2737,8 @@ void _vuRegsFMEQ(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = (1 << REG_MAC_FLAG) | (1 << _Fs_); VUregsn->VIread = (1 << REG_MAC_FLAG) | (1 << _Is_);
} }
void _vuRegsFMOR(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsFMOR(VURegs * VU, _VURegsNum *VUregsn) {
@ -2743,8 +2746,8 @@ void _vuRegsFMOR(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = (1 << REG_MAC_FLAG) | (1 << _Fs_); VUregsn->VIread = (1 << REG_MAC_FLAG) | (1 << _Is_);
} }
void _vuRegsFCAND(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsFCAND(VURegs * VU, _VURegsNum *VUregsn) {
@ -2788,7 +2791,7 @@ void _vuRegsFCGET(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = 1 << REG_CLIP_FLAG; VUregsn->VIread = 1 << REG_CLIP_FLAG;
} }
@ -2798,7 +2801,7 @@ void _vuRegsIBEQ(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = (1 << _Fs_) | (1 << _Ft_); VUregsn->VIread = (1 << _Is_) | (1 << _It_);
} }
void _vuRegsIBGEZ(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsIBGEZ(VURegs * VU, _VURegsNum *VUregsn) {
@ -2807,7 +2810,7 @@ void _vuRegsIBGEZ(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsIBGTZ(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsIBGTZ(VURegs * VU, _VURegsNum *VUregsn) {
@ -2816,7 +2819,7 @@ void _vuRegsIBGTZ(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsIBLEZ(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsIBLEZ(VURegs * VU, _VURegsNum *VUregsn) {
@ -2825,7 +2828,7 @@ void _vuRegsIBLEZ(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsIBLTZ(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsIBLTZ(VURegs * VU, _VURegsNum *VUregsn) {
@ -2834,7 +2837,7 @@ void _vuRegsIBLTZ(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsIBNE(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsIBNE(VURegs * VU, _VURegsNum *VUregsn) {
@ -2843,7 +2846,7 @@ void _vuRegsIBNE(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = (1 << _Fs_) | (1 << _Ft_); VUregsn->VIread = (1 << _Is_) | (1 << _It_);
} }
void _vuRegsB(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsB(VURegs * VU, _VURegsNum *VUregsn) {
@ -2860,7 +2863,7 @@ void _vuRegsBAL(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = 0; VUregsn->VIread = 0;
} }
@ -2870,7 +2873,7 @@ void _vuRegsJR(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsJALR(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsJALR(VURegs * VU, _VURegsNum *VUregsn) {
@ -2878,8 +2881,8 @@ void _vuRegsJALR(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsMFP(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsMFP(VURegs * VU, _VURegsNum *VUregsn) {
@ -2920,7 +2923,7 @@ void _vuRegsXITOP(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = 0; VUregsn->VIread = 0;
VUregsn->cycles = 0; VUregsn->cycles = 0;
} }
@ -2931,7 +2934,7 @@ void _vuRegsXGKICK(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 0; VUregsn->VIwrite = 0;
VUregsn->VIread = 1 << _Fs_; VUregsn->VIread = 1 << _Is_;
} }
void _vuRegsXTOP(VURegs * VU, _VURegsNum *VUregsn) { void _vuRegsXTOP(VURegs * VU, _VURegsNum *VUregsn) {
@ -2939,7 +2942,7 @@ void _vuRegsXTOP(VURegs * VU, _VURegsNum *VUregsn) {
VUregsn->VFwrite = 0; VUregsn->VFwrite = 0;
VUregsn->VFread0 = 0; VUregsn->VFread0 = 0;
VUregsn->VFread1 = 0; VUregsn->VFread1 = 0;
VUregsn->VIwrite = 1 << _Ft_; VUregsn->VIwrite = 1 << _It_;
VUregsn->VIread = 0; VUregsn->VIread = 0;
VUregsn->cycles = 0; VUregsn->cycles = 0;
} }

3
pcsx2/x86/iVUmicro.cpp
View File

@ -46,6 +46,9 @@
#define _Ft_ (( VU->code >> 16) & 0x1F) // The rt part of the instruction register #define _Ft_ (( VU->code >> 16) & 0x1F) // The rt part of the instruction register
#define _Fs_ (( VU->code >> 11) & 0x1F) // The rd part of the instruction register #define _Fs_ (( VU->code >> 11) & 0x1F) // The rd part of the instruction register
#define _Fd_ (( VU->code >> 6) & 0x1F) // The sa part of the instruction register #define _Fd_ (( VU->code >> 6) & 0x1F) // The sa part of the instruction register
#define _It_ (_Ft_ & 15)
#define _Is_ (_Fs_ & 15)
#define _Id_ (_Fd_ & 15)
#define _X (( VU->code>>24) & 0x1) #define _X (( VU->code>>24) & 0x1)
#define _Y (( VU->code>>23) & 0x1) #define _Y (( VU->code>>23) & 0x1)

519
pcsx2/x86/iVUmicroLower.cpp
View File

@ -38,6 +38,9 @@
#define _Ft_ (( VU->code >> 16) & 0x1F) // The rt part of the instruction register #define _Ft_ (( VU->code >> 16) & 0x1F) // The rt part of the instruction register
#define _Fs_ (( VU->code >> 11) & 0x1F) // The rd part of the instruction register #define _Fs_ (( VU->code >> 11) & 0x1F) // The rd part of the instruction register
#define _Fd_ (( VU->code >> 6) & 0x1F) // The sa part of the instruction register #define _Fd_ (( VU->code >> 6) & 0x1F) // The sa part of the instruction register
#define _It_ (_Ft_ & 15)
#define _Is_ (_Fs_ & 15)
#define _Id_ (_Fd_ & 15)
#define _X (( VU->code>>24) & 0x1) #define _X (( VU->code>>24) & 0x1)
#define _Y (( VU->code>>23) & 0x1) #define _Y (( VU->code>>23) & 0x1)
@ -257,28 +260,28 @@ void recVUMI_RSQRT(VURegs *VU, int info)
//------------------------------------------------------------------ //------------------------------------------------------------------
void _addISIMMtoIT(VURegs *VU, s16 imm, int info) void _addISIMMtoIT(VURegs *VU, s16 imm, int info)
{ {
int fsreg = -1, ftreg; int isreg = -1, itreg;
if (_Ft_ == 0) return; if (_It_ == 0) return;
if( _Fs_ == 0 ) { if( _Is_ == 0 ) {
ftreg = ALLOCVI(_Ft_, MODE_WRITE); itreg = ALLOCVI(_It_, MODE_WRITE);
MOV32ItoR(ftreg, imm&0xffff); MOV32ItoR(itreg, imm&0xffff);
return; return;
} }
ADD_VI_NEEDED(_Ft_); ADD_VI_NEEDED(_It_);
fsreg = ALLOCVI(_Fs_, MODE_READ); isreg = ALLOCVI(_Is_, MODE_READ);
ftreg = ALLOCVI(_Ft_, MODE_WRITE); itreg = ALLOCVI(_It_, MODE_WRITE);
if ( _Ft_ == _Fs_ ) { if ( _It_ == _Is_ ) {
if (imm != 0 ) ADD16ItoR(ftreg, imm); if (imm != 0 ) ADD16ItoR(itreg, imm);
} }
else { else {
if( imm ) { if( imm ) {
LEA32RtoR(ftreg, fsreg, imm); LEA32RtoR(itreg, isreg, imm);
MOVZX32R16toR(ftreg, ftreg); MOVZX32R16toR(itreg, itreg);
} }
else MOV32RtoR(ftreg, fsreg); else MOV32RtoR(itreg, isreg);
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -291,7 +294,7 @@ void recVUMI_IADDI(VURegs *VU, int info)
{ {
s16 imm; s16 imm;
if ( _Ft_ == 0 ) return; if ( _It_ == 0 ) return;
//Console::WriteLn("recVUMI_IADDI"); //Console::WriteLn("recVUMI_IADDI");
imm = ( VU->code >> 6 ) & 0x1f; imm = ( VU->code >> 6 ) & 0x1f;
imm = ( imm & 0x10 ? 0xfff0 : 0) | ( imm & 0xf ); imm = ( imm & 0x10 ? 0xfff0 : 0) | ( imm & 0xf );
@ -307,7 +310,7 @@ void recVUMI_IADDIU(VURegs *VU, int info)
{ {
s16 imm; s16 imm;
if ( _Ft_ == 0 ) return; if ( _It_ == 0 ) return;
//Console::WriteLn("recVUMI_IADDIU"); //Console::WriteLn("recVUMI_IADDIU");
imm = ( ( VU->code >> 10 ) & 0x7800 ) | ( VU->code & 0x7ff ); imm = ( ( VU->code >> 10 ) & 0x7800 ) | ( VU->code & 0x7ff );
_addISIMMtoIT(VU, imm, info); _addISIMMtoIT(VU, imm, info);
@ -320,42 +323,42 @@ void recVUMI_IADDIU(VURegs *VU, int info)
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_IADD( VURegs *VU, int info ) void recVUMI_IADD( VURegs *VU, int info )
{ {
int fdreg, fsreg = -1, ftreg = -1; int idreg, isreg = -1, itreg = -1;
if ( _Fd_ == 0 ) return; if ( _Id_ == 0 ) return;
//Console::WriteLn("recVUMI_IADD"); //Console::WriteLn("recVUMI_IADD");
if ( ( _Ft_ == 0 ) && ( _Fs_ == 0 ) ) { if ( ( _It_ == 0 ) && ( _Is_ == 0 ) ) {
fdreg = ALLOCVI(_Fd_, MODE_WRITE); idreg = ALLOCVI(_Id_, MODE_WRITE);
XOR32RtoR(fdreg, fdreg); XOR32RtoR(idreg, idreg);
return; return;
} }
ADD_VI_NEEDED(_Fs_); ADD_VI_NEEDED(_Is_);
ADD_VI_NEEDED(_Ft_); ADD_VI_NEEDED(_It_);
fdreg = ALLOCVI(_Fd_, MODE_WRITE); idreg = ALLOCVI(_Id_, MODE_WRITE);
if ( _Fs_ == 0 ) if ( _Is_ == 0 )
{ {
if( (ftreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Ft_, MODE_READ)) >= 0 ) { if( (itreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _It_, MODE_READ)) >= 0 ) {
if( fdreg != ftreg ) MOV32RtoR(fdreg, ftreg); if( idreg != itreg ) MOV32RtoR(idreg, itreg);
} }
else MOVZX32M16toR(fdreg, VU_VI_ADDR(_Ft_, 1)); else MOVZX32M16toR(idreg, VU_VI_ADDR(_It_, 1));
} }
else if ( _Ft_ == 0 ) else if ( _It_ == 0 )
{ {
if( (fsreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Fs_, MODE_READ)) >= 0 ) { if( (isreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Is_, MODE_READ)) >= 0 ) {
if( fdreg != fsreg ) MOV32RtoR(fdreg, fsreg); if( idreg != isreg ) MOV32RtoR(idreg, isreg);
} }
else MOVZX32M16toR(fdreg, VU_VI_ADDR(_Fs_, 1)); else MOVZX32M16toR(idreg, VU_VI_ADDR(_Is_, 1));
} }
else { else {
//ADD_VI_NEEDED(_Ft_); //ADD_VI_NEEDED(_It_);
fsreg = ALLOCVI(_Fs_, MODE_READ); isreg = ALLOCVI(_Is_, MODE_READ);
ftreg = ALLOCVI(_Ft_, MODE_READ); itreg = ALLOCVI(_It_, MODE_READ);
if( fdreg == fsreg ) ADD32RtoR(fdreg, ftreg); if( idreg == isreg ) ADD32RtoR(idreg, itreg);
else if( fdreg == ftreg ) ADD32RtoR(fdreg, fsreg); else if( idreg == itreg ) ADD32RtoR(idreg, isreg);
else LEA32RRtoR(fdreg, fsreg, ftreg); else LEA32RRtoR(idreg, isreg, itreg);
MOVZX32R16toR(fdreg, fdreg); // needed since don't know if fdreg's upper bits are 0 MOVZX32R16toR(idreg, idreg); // needed since don't know if idreg's upper bits are 0
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -366,27 +369,27 @@ void recVUMI_IADD( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_IAND( VURegs *VU, int info ) void recVUMI_IAND( VURegs *VU, int info )
{ {
int fdreg, fsreg = -1, ftreg = -1; int idreg, isreg = -1, itreg = -1;
if ( _Fd_ == 0 ) return; if ( _Id_ == 0 ) return;
//Console::WriteLn("recVUMI_IAND"); //Console::WriteLn("recVUMI_IAND");
if ( ( _Fs_ == 0 ) || ( _Ft_ == 0 ) ) { if ( ( _Is_ == 0 ) || ( _It_ == 0 ) ) {
fdreg = ALLOCVI(_Fd_, MODE_WRITE); idreg = ALLOCVI(_Id_, MODE_WRITE);
XOR32RtoR(fdreg, fdreg); XOR32RtoR(idreg, idreg);
return; return;
} }
ADD_VI_NEEDED(_Fs_); ADD_VI_NEEDED(_Is_);
ADD_VI_NEEDED(_Ft_); ADD_VI_NEEDED(_It_);
fdreg = ALLOCVI(_Fd_, MODE_WRITE); idreg = ALLOCVI(_Id_, MODE_WRITE);
fsreg = ALLOCVI(_Fs_, MODE_READ); isreg = ALLOCVI(_Is_, MODE_READ);
ftreg = ALLOCVI(_Ft_, MODE_READ); itreg = ALLOCVI(_It_, MODE_READ);
if( fdreg == fsreg ) AND16RtoR(fdreg, ftreg); if( idreg == isreg ) AND16RtoR(idreg, itreg);
else if( fdreg == ftreg ) AND16RtoR(fdreg, fsreg); else if( idreg == itreg ) AND16RtoR(idreg, isreg);
else { else {
MOV32RtoR(fdreg, ftreg); MOV32RtoR(idreg, itreg);
AND32RtoR(fdreg, fsreg); AND32RtoR(idreg, isreg);
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -397,43 +400,43 @@ void recVUMI_IAND( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_IOR( VURegs *VU, int info ) void recVUMI_IOR( VURegs *VU, int info )
{ {
int fdreg, fsreg = -1, ftreg = -1; int idreg, isreg = -1, itreg = -1;
if ( _Fd_ == 0 ) return; if ( _Id_ == 0 ) return;
//Console::WriteLn("recVUMI_IOR"); //Console::WriteLn("recVUMI_IOR");
if ( ( _Ft_ == 0 ) && ( _Fs_ == 0 ) ) { if ( ( _It_ == 0 ) && ( _Is_ == 0 ) ) {
fdreg = ALLOCVI(_Fd_, MODE_WRITE); idreg = ALLOCVI(_Id_, MODE_WRITE);
XOR32RtoR(fdreg, fdreg); XOR32RtoR(idreg, idreg);
return; return;
} }
ADD_VI_NEEDED(_Fs_); ADD_VI_NEEDED(_Is_);
ADD_VI_NEEDED(_Ft_); ADD_VI_NEEDED(_It_);
fdreg = ALLOCVI(_Fd_, MODE_WRITE); idreg = ALLOCVI(_Id_, MODE_WRITE);
if ( _Fs_ == 0 ) if ( _Is_ == 0 )
{ {
if( (ftreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Ft_, MODE_READ)) >= 0 ) { if( (itreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _It_, MODE_READ)) >= 0 ) {
if( fdreg != ftreg ) MOV32RtoR(fdreg, ftreg); if( idreg != itreg ) MOV32RtoR(idreg, itreg);
} }
else MOVZX32M16toR(fdreg, VU_VI_ADDR(_Ft_, 1)); else MOVZX32M16toR(idreg, VU_VI_ADDR(_It_, 1));
} }
else if ( _Ft_ == 0 ) else if ( _It_ == 0 )
{ {
if( (fsreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Fs_, MODE_READ)) >= 0 ) { if( (isreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Is_, MODE_READ)) >= 0 ) {
if( fdreg != fsreg ) MOV32RtoR(fdreg, fsreg); if( idreg != isreg ) MOV32RtoR(idreg, isreg);
} }
else MOVZX32M16toR(fdreg, VU_VI_ADDR(_Fs_, 1)); else MOVZX32M16toR(idreg, VU_VI_ADDR(_Is_, 1));
} }
else else
{ {
fsreg = ALLOCVI(_Fs_, MODE_READ); isreg = ALLOCVI(_Is_, MODE_READ);
ftreg = ALLOCVI(_Ft_, MODE_READ); itreg = ALLOCVI(_It_, MODE_READ);
if( fdreg == fsreg ) OR16RtoR(fdreg, ftreg); if( idreg == isreg ) OR16RtoR(idreg, itreg);
else if( fdreg == ftreg ) OR16RtoR(fdreg, fsreg); else if( idreg == itreg ) OR16RtoR(idreg, isreg);
else { else {
MOV32RtoR(fdreg, fsreg); MOV32RtoR(idreg, isreg);
OR32RtoR(fdreg, ftreg); OR32RtoR(idreg, itreg);
} }
} }
} }
@ -445,47 +448,47 @@ void recVUMI_IOR( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_ISUB( VURegs *VU, int info ) void recVUMI_ISUB( VURegs *VU, int info )
{ {
int fdreg, fsreg = -1, ftreg = -1; int idreg, isreg = -1, itreg = -1;
if ( _Fd_ == 0 ) return; if ( _Id_ == 0 ) return;
//Console::WriteLn("recVUMI_ISUB"); //Console::WriteLn("recVUMI_ISUB");
if ( ( _Ft_ == 0 ) && ( _Fs_ == 0 ) ) { if ( ( _It_ == 0 ) && ( _Is_ == 0 ) ) {
fdreg = ALLOCVI(_Fd_, MODE_WRITE); idreg = ALLOCVI(_Id_, MODE_WRITE);
XOR32RtoR(fdreg, fdreg); XOR32RtoR(idreg, idreg);
return; return;
} }
ADD_VI_NEEDED(_Fs_); ADD_VI_NEEDED(_Is_);
ADD_VI_NEEDED(_Ft_); ADD_VI_NEEDED(_It_);
fdreg = ALLOCVI(_Fd_, MODE_WRITE); idreg = ALLOCVI(_Id_, MODE_WRITE);
if ( _Fs_ == 0 ) if ( _Is_ == 0 )
{ {
if( (ftreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Ft_, MODE_READ)) >= 0 ) { if( (itreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _It_, MODE_READ)) >= 0 ) {
if( fdreg != ftreg ) MOV32RtoR(fdreg, ftreg); if( idreg != itreg ) MOV32RtoR(idreg, itreg);
} }
else MOVZX32M16toR(fdreg, VU_VI_ADDR(_Ft_, 1)); else MOVZX32M16toR(idreg, VU_VI_ADDR(_It_, 1));
NEG16R(fdreg); NEG16R(idreg);
} }
else if ( _Ft_ == 0 ) else if ( _It_ == 0 )
{ {
if( (fsreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Fs_, MODE_READ)) >= 0 ) { if( (isreg = _checkX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Is_, MODE_READ)) >= 0 ) {
if( fdreg != fsreg ) MOV32RtoR(fdreg, fsreg); if( idreg != isreg ) MOV32RtoR(idreg, isreg);
} }
else MOVZX32M16toR(fdreg, VU_VI_ADDR(_Fs_, 1)); else MOVZX32M16toR(idreg, VU_VI_ADDR(_Is_, 1));
} }
else else
{ {
fsreg = ALLOCVI(_Fs_, MODE_READ); isreg = ALLOCVI(_Is_, MODE_READ);
ftreg = ALLOCVI(_Ft_, MODE_READ); itreg = ALLOCVI(_It_, MODE_READ);
if( fdreg == fsreg ) SUB16RtoR(fdreg, ftreg); if( idreg == isreg ) SUB16RtoR(idreg, itreg);
else if( fdreg == ftreg ) { else if( idreg == itreg ) {
SUB16RtoR(fdreg, fsreg); SUB16RtoR(idreg, isreg);
NEG16R(fdreg); NEG16R(idreg);
} }
else { else {
MOV32RtoR(fdreg, fsreg); MOV32RtoR(idreg, isreg);
SUB16RtoR(fdreg, ftreg); SUB16RtoR(idreg, itreg);
} }
} }
} }
@ -498,7 +501,7 @@ void recVUMI_ISUBIU( VURegs *VU, int info )
{ {
s16 imm; s16 imm;
if ( _Ft_ == 0 ) return; if ( _It_ == 0 ) return;
//Console::WriteLn("recVUMI_ISUBIU"); //Console::WriteLn("recVUMI_ISUBIU");
imm = ( ( VU->code >> 10 ) & 0x7800 ) | ( VU->code & 0x7ff ); imm = ( ( VU->code >> 10 ) & 0x7800 ) | ( VU->code & 0x7ff );
imm = -imm; imm = -imm;
@ -531,23 +534,23 @@ void recVUMI_MFIR( VURegs *VU, int info )
{ {
if ( (_Ft_ == 0) || (_X_Y_Z_W == 0) ) return; if ( (_Ft_ == 0) || (_X_Y_Z_W == 0) ) return;
//Console::WriteLn("recVUMI_MFIR"); //Console::WriteLn("recVUMI_MFIR");
_deleteX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Fs_, 1); _deleteX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Is_, 1);
if( _XYZW_SS ) { if( _XYZW_SS ) {
SSE2_MOVD_M32_to_XMM(EEREC_TEMP, VU_VI_ADDR(_Fs_, 1)-2); SSE2_MOVD_M32_to_XMM(EEREC_TEMP, VU_VI_ADDR(_Is_, 1)-2);
_vuFlipRegSS(VU, EEREC_T); _vuFlipRegSS(VU, EEREC_T);
SSE2_PSRAD_I8_to_XMM(EEREC_TEMP, 16); SSE2_PSRAD_I8_to_XMM(EEREC_TEMP, 16);
SSE_MOVSS_XMM_to_XMM(EEREC_T, EEREC_TEMP); SSE_MOVSS_XMM_to_XMM(EEREC_T, EEREC_TEMP);
_vuFlipRegSS(VU, EEREC_T); _vuFlipRegSS(VU, EEREC_T);
} }
else if (_X_Y_Z_W != 0xf) { else if (_X_Y_Z_W != 0xf) {
SSE2_MOVD_M32_to_XMM(EEREC_TEMP, VU_VI_ADDR(_Fs_, 1)-2); SSE2_MOVD_M32_to_XMM(EEREC_TEMP, VU_VI_ADDR(_Is_, 1)-2);
SSE2_PSRAD_I8_to_XMM(EEREC_TEMP, 16); SSE2_PSRAD_I8_to_XMM(EEREC_TEMP, 16);
SSE_SHUFPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP, 0); SSE_SHUFPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP, 0);
VU_MERGE_REGS(EEREC_T, EEREC_TEMP); VU_MERGE_REGS(EEREC_T, EEREC_TEMP);
} }
else { else {
SSE2_MOVD_M32_to_XMM(EEREC_T, VU_VI_ADDR(_Fs_, 1)-2); SSE2_MOVD_M32_to_XMM(EEREC_T, VU_VI_ADDR(_Is_, 1)-2);
SSE2_PSRAD_I8_to_XMM(EEREC_T, 16); SSE2_PSRAD_I8_to_XMM(EEREC_T, 16);
SSE_SHUFPS_XMM_to_XMM(EEREC_T, EEREC_T, 0); SSE_SHUFPS_XMM_to_XMM(EEREC_T, EEREC_T, 0);
} }
@ -560,19 +563,19 @@ void recVUMI_MFIR( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_MTIR( VURegs *VU, int info ) void recVUMI_MTIR( VURegs *VU, int info )
{ {
if ( _Ft_ == 0 ) return; if ( _It_ == 0 ) return;
//Console::WriteLn("recVUMI_MTIR"); //Console::WriteLn("recVUMI_MTIR");
_deleteX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _Ft_, 2); _deleteX86reg(X86TYPE_VI|((VU==&VU1)?X86TYPE_VU1:0), _It_, 2);
if( _Fsf_ == 0 ) { if( _Fsf_ == 0 ) {
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(_Ft_, 0), EEREC_S); SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(_It_, 0), EEREC_S);
} }
else { else {
_unpackVFSS_xyzw(EEREC_TEMP, EEREC_S, _Fsf_); _unpackVFSS_xyzw(EEREC_TEMP, EEREC_S, _Fsf_);
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(_Ft_, 0), EEREC_TEMP); SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(_It_, 0), EEREC_TEMP);
} }
AND32ItoM(VU_VI_ADDR(_Ft_, 0), 0xffff); AND32ItoM(VU_VI_ADDR(_It_, 0), 0xffff);
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -723,12 +726,12 @@ void recVUMI_LQ(VURegs *VU, int info)
if ( _Ft_ == 0 ) return; if ( _Ft_ == 0 ) return;
//Console::WriteLn("recVUMI_LQ"); //Console::WriteLn("recVUMI_LQ");
imm = (VU->code & 0x400) ? (VU->code & 0x3ff) | 0xfc00 : (VU->code & 0x3ff); imm = (VU->code & 0x400) ? (VU->code & 0x3ff) | 0xfc00 : (VU->code & 0x3ff);
if (_Fs_ == 0) { if (_Is_ == 0) {
_loadEAX(VU, -1, (uptr)GET_VU_MEM(VU, (u32)imm*16), info); _loadEAX(VU, -1, (uptr)GET_VU_MEM(VU, (u32)imm*16), info);
} }
else { else {
int fsreg = ALLOCVI(_Fs_, MODE_READ); int isreg = ALLOCVI(_Is_, MODE_READ);
_loadEAX(VU, recVUTransformAddr(fsreg, VU, _Fs_, imm), (uptr)VU->Mem, info); _loadEAX(VU, recVUTransformAddr(isreg, VU, _Is_, imm), (uptr)VU->Mem, info);
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -739,17 +742,17 @@ void recVUMI_LQ(VURegs *VU, int info)
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_LQD( VURegs *VU, int info ) void recVUMI_LQD( VURegs *VU, int info )
{ {
int fsreg; int isreg;
//Console::WriteLn("recVUMI_LQD"); //Console::WriteLn("recVUMI_LQD");
if ( _Fs_ != 0 ) { if ( _Is_ != 0 ) {
fsreg = ALLOCVI(_Fs_, MODE_READ|MODE_WRITE); isreg = ALLOCVI(_Is_, MODE_READ|MODE_WRITE);
SUB16ItoR( fsreg, 1 ); SUB16ItoR( isreg, 1 );
} }
if ( _Ft_ == 0 ) return; if ( _Ft_ == 0 ) return;
if ( _Fs_ == 0 ) _loadEAX(VU, -1, (uptr)VU->Mem, info); if ( _Is_ == 0 ) _loadEAX(VU, -1, (uptr)VU->Mem, info);
else _loadEAX(VU, recVUTransformAddr(fsreg, VU, _Fs_, 0), (uptr)VU->Mem, info); else _loadEAX(VU, recVUTransformAddr(isreg, VU, _Is_, 0), (uptr)VU->Mem, info);
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -759,27 +762,27 @@ void recVUMI_LQD( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_LQI(VURegs *VU, int info) void recVUMI_LQI(VURegs *VU, int info)
{ {
int fsreg; int isreg;
//Console::WriteLn("recVUMI_LQI"); //Console::WriteLn("recVUMI_LQI");
if ( _Ft_ == 0 ) { if ( _Ft_ == 0 ) {
if( _Fs_ != 0 ) { if( _Is_ != 0 ) {
if( (fsreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_WRITE|MODE_READ)) >= 0 ) { if( (isreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_WRITE|MODE_READ)) >= 0 ) {
ADD16ItoR(fsreg, 1); ADD16ItoR(isreg, 1);
} }
else { else {
ADD16ItoM( VU_VI_ADDR( _Fs_, 0 ), 1 ); ADD16ItoM( VU_VI_ADDR( _Is_, 0 ), 1 );
} }
} }
return; return;
} }
if (_Fs_ == 0) { if (_Is_ == 0) {
_loadEAX(VU, -1, (uptr)VU->Mem, info); _loadEAX(VU, -1, (uptr)VU->Mem, info);
} }
else { else {
fsreg = ALLOCVI(_Fs_, MODE_READ|MODE_WRITE); isreg = ALLOCVI(_Is_, MODE_READ|MODE_WRITE);
_loadEAX(VU, recVUTransformAddr(fsreg, VU, _Fs_, 0), (uptr)VU->Mem, info); _loadEAX(VU, recVUTransformAddr(isreg, VU, _Is_, 0), (uptr)VU->Mem, info);
ADD16ItoR( fsreg, 1 ); ADD16ItoR( isreg, 1 );
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -948,10 +951,10 @@ void recVUMI_SQ(VURegs *VU, int info)
s16 imm; s16 imm;
//Console::WriteLn("recVUMI_SQ"); //Console::WriteLn("recVUMI_SQ");
imm = ( VU->code & 0x400) ? ( VU->code & 0x3ff) | 0xfc00 : ( VU->code & 0x3ff); imm = ( VU->code & 0x400) ? ( VU->code & 0x3ff) | 0xfc00 : ( VU->code & 0x3ff);
if ( _Ft_ == 0 ) _saveEAX(VU, -1, (uptr)GET_VU_MEM(VU, (int)imm * 16), info); if ( _It_ == 0 ) _saveEAX(VU, -1, (uptr)GET_VU_MEM(VU, (int)imm * 16), info);
else { else {
int ftreg = ALLOCVI(_Ft_, MODE_READ); int itreg = ALLOCVI(_It_, MODE_READ);
_saveEAX(VU, recVUTransformAddr(ftreg, VU, _Ft_, imm), (uptr)VU->Mem, info); _saveEAX(VU, recVUTransformAddr(itreg, VU, _It_, imm), (uptr)VU->Mem, info);
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -963,11 +966,11 @@ void recVUMI_SQ(VURegs *VU, int info)
void recVUMI_SQD(VURegs *VU, int info) void recVUMI_SQD(VURegs *VU, int info)
{ {
//Console::WriteLn("recVUMI_SQD"); //Console::WriteLn("recVUMI_SQD");
if (_Ft_ == 0) _saveEAX(VU, -1, (uptr)VU->Mem, info); if (_It_ == 0) _saveEAX(VU, -1, (uptr)VU->Mem, info);
else { else {
int ftreg = ALLOCVI(_Ft_, MODE_READ|MODE_WRITE); int itreg = ALLOCVI(_It_, MODE_READ|MODE_WRITE);
SUB16ItoR( ftreg, 1 ); SUB16ItoR( itreg, 1 );
_saveEAX(VU, recVUTransformAddr(ftreg, VU, _Ft_, 0), (uptr)VU->Mem, info); _saveEAX(VU, recVUTransformAddr(itreg, VU, _It_, 0), (uptr)VU->Mem, info);
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -979,11 +982,11 @@ void recVUMI_SQD(VURegs *VU, int info)
void recVUMI_SQI(VURegs *VU, int info) void recVUMI_SQI(VURegs *VU, int info)
{ {
//Console::WriteLn("recVUMI_SQI"); //Console::WriteLn("recVUMI_SQI");
if (_Ft_ == 0) _saveEAX(VU, -1, (uptr)VU->Mem, info); if (_It_ == 0) _saveEAX(VU, -1, (uptr)VU->Mem, info);
else { else {
int ftreg = ALLOCVI(_Ft_, MODE_READ|MODE_WRITE); int itreg = ALLOCVI(_It_, MODE_READ|MODE_WRITE);
_saveEAX(VU, recVUTransformAddr(ftreg, VU, _Ft_, 0), (uptr)VU->Mem, info); _saveEAX(VU, recVUTransformAddr(itreg, VU, _It_, 0), (uptr)VU->Mem, info);
ADD16ItoR( ftreg, 1 ); ADD16ItoR( itreg, 1 );
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -994,10 +997,10 @@ void recVUMI_SQI(VURegs *VU, int info)
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_ILW(VURegs *VU, int info) void recVUMI_ILW(VURegs *VU, int info)
{ {
int ftreg; int itreg;
s16 imm, off; s16 imm, off;
if ( ( _Ft_ == 0 ) || ( _X_Y_Z_W == 0 ) ) return; if ( ( _It_ == 0 ) || ( _X_Y_Z_W == 0 ) ) return;
//Console::WriteLn("recVUMI_ILW"); //Console::WriteLn("recVUMI_ILW");
imm = ( VU->code & 0x400) ? ( VU->code & 0x3ff) | 0xfc00 : ( VU->code & 0x3ff); imm = ( VU->code & 0x400) ? ( VU->code & 0x3ff) | 0xfc00 : ( VU->code & 0x3ff);
if (_X) off = 0; if (_X) off = 0;
@ -1005,15 +1008,15 @@ void recVUMI_ILW(VURegs *VU, int info)
else if (_Z) off = 8; else if (_Z) off = 8;
else if (_W) off = 12; else if (_W) off = 12;
ADD_VI_NEEDED(_Fs_); ADD_VI_NEEDED(_Is_);
ftreg = ALLOCVI(_Ft_, MODE_WRITE); itreg = ALLOCVI(_It_, MODE_WRITE);
if ( _Fs_ == 0 ) { if ( _Is_ == 0 ) {
MOVZX32M16toR( ftreg, (uptr)GET_VU_MEM(VU, (int)imm * 16 + off) ); MOVZX32M16toR( itreg, (uptr)GET_VU_MEM(VU, (int)imm * 16 + off) );
} }
else { else {
int fsreg = ALLOCVI(_Fs_, MODE_READ); int isreg = ALLOCVI(_Is_, MODE_READ);
MOV32RmtoR(ftreg, recVUTransformAddr(fsreg, VU, _Fs_, imm), (uptr)VU->Mem + off); MOV32RmtoR(itreg, recVUTransformAddr(isreg, VU, _Is_, imm), (uptr)VU->Mem + off);
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1028,28 +1031,28 @@ void recVUMI_ISW( VURegs *VU, int info )
//Console::WriteLn("recVUMI_ISW"); //Console::WriteLn("recVUMI_ISW");
imm = ( VU->code & 0x400) ? ( VU->code & 0x3ff) | 0xfc00 : ( VU->code & 0x3ff); imm = ( VU->code & 0x400) ? ( VU->code & 0x3ff) | 0xfc00 : ( VU->code & 0x3ff);
if (_Fs_ == 0) { if (_Is_ == 0) {
uptr off = (uptr)GET_VU_MEM(VU, (int)imm * 16); uptr off = (uptr)GET_VU_MEM(VU, (int)imm * 16);
int ftreg = ALLOCVI(_Ft_, MODE_READ); int itreg = ALLOCVI(_It_, MODE_READ);
if (_X) MOV32RtoM(off, ftreg); if (_X) MOV32RtoM(off, itreg);
if (_Y) MOV32RtoM(off+4, ftreg); if (_Y) MOV32RtoM(off+4, itreg);
if (_Z) MOV32RtoM(off+8, ftreg); if (_Z) MOV32RtoM(off+8, itreg);
if (_W) MOV32RtoM(off+12, ftreg); if (_W) MOV32RtoM(off+12, itreg);
} }
else { else {
int x86reg, fsreg, ftreg; int x86reg, isreg, itreg;
ADD_VI_NEEDED(_Ft_); ADD_VI_NEEDED(_It_);
fsreg = ALLOCVI(_Fs_, MODE_READ); isreg = ALLOCVI(_Is_, MODE_READ);
ftreg = ALLOCVI(_Ft_, MODE_READ); itreg = ALLOCVI(_It_, MODE_READ);
x86reg = recVUTransformAddr(fsreg, VU, _Fs_, imm); x86reg = recVUTransformAddr(isreg, VU, _Is_, imm);
if (_X) MOV32RtoRm(x86reg, ftreg, (uptr)VU->Mem); if (_X) MOV32RtoRm(x86reg, itreg, (uptr)VU->Mem);
if (_Y) MOV32RtoRm(x86reg, ftreg, (uptr)VU->Mem+4); if (_Y) MOV32RtoRm(x86reg, itreg, (uptr)VU->Mem+4);
if (_Z) MOV32RtoRm(x86reg, ftreg, (uptr)VU->Mem+8); if (_Z) MOV32RtoRm(x86reg, itreg, (uptr)VU->Mem+8);
if (_W) MOV32RtoRm(x86reg, ftreg, (uptr)VU->Mem+12); if (_W) MOV32RtoRm(x86reg, itreg, (uptr)VU->Mem+12);
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1060,24 +1063,24 @@ void recVUMI_ISW( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_ILWR( VURegs *VU, int info ) void recVUMI_ILWR( VURegs *VU, int info )
{ {
int off, ftreg; int off, itreg;
if ( ( _Ft_ == 0 ) || ( _X_Y_Z_W == 0 ) ) return; if ( ( _It_ == 0 ) || ( _X_Y_Z_W == 0 ) ) return;
//Console::WriteLn("recVUMI_ILWR"); //Console::WriteLn("recVUMI_ILWR");
if (_X) off = 0; if (_X) off = 0;
else if (_Y) off = 4; else if (_Y) off = 4;
else if (_Z) off = 8; else if (_Z) off = 8;
else if (_W) off = 12; else if (_W) off = 12;
ADD_VI_NEEDED(_Fs_); ADD_VI_NEEDED(_Is_);
ftreg = ALLOCVI(_Ft_, MODE_WRITE); itreg = ALLOCVI(_It_, MODE_WRITE);
if ( _Fs_ == 0 ) { if ( _Is_ == 0 ) {
MOVZX32M16toR( ftreg, (uptr)VU->Mem + off ); MOVZX32M16toR( itreg, (uptr)VU->Mem + off );
} }
else { else {
int fsreg = ALLOCVI(_Fs_, MODE_READ); int isreg = ALLOCVI(_Is_, MODE_READ);
MOVZX32Rm16toR(ftreg, recVUTransformAddr(fsreg, VU, _Fs_, 0), (uptr)VU->Mem + off); MOVZX32Rm16toR(itreg, recVUTransformAddr(isreg, VU, _Is_, 0), (uptr)VU->Mem + off);
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1088,26 +1091,26 @@ void recVUMI_ILWR( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_ISWR( VURegs *VU, int info ) void recVUMI_ISWR( VURegs *VU, int info )
{ {
int ftreg; int itreg;
//Console::WriteLn("recVUMI_ISWR"); //Console::WriteLn("recVUMI_ISWR");
ADD_VI_NEEDED(_Fs_); ADD_VI_NEEDED(_Is_);
ftreg = ALLOCVI(_Ft_, MODE_READ); itreg = ALLOCVI(_It_, MODE_READ);
if (_Fs_ == 0) { if (_Is_ == 0) {
if (_X) MOV32RtoM((uptr)VU->Mem, ftreg); if (_X) MOV32RtoM((uptr)VU->Mem, itreg);
if (_Y) MOV32RtoM((uptr)VU->Mem+4, ftreg); if (_Y) MOV32RtoM((uptr)VU->Mem+4, itreg);
if (_Z) MOV32RtoM((uptr)VU->Mem+8, ftreg); if (_Z) MOV32RtoM((uptr)VU->Mem+8, itreg);
if (_W) MOV32RtoM((uptr)VU->Mem+12, ftreg); if (_W) MOV32RtoM((uptr)VU->Mem+12, itreg);
} }
else { else {
int x86reg; int x86reg;
int fsreg = ALLOCVI(_Fs_, MODE_READ); int isreg = ALLOCVI(_Is_, MODE_READ);
x86reg = recVUTransformAddr(fsreg, VU, _Fs_, 0); x86reg = recVUTransformAddr(isreg, VU, _Is_, 0);
if (_X) MOV32RtoRm(x86reg, ftreg, (uptr)VU->Mem); if (_X) MOV32RtoRm(x86reg, itreg, (uptr)VU->Mem);
if (_Y) MOV32RtoRm(x86reg, ftreg, (uptr)VU->Mem+4); if (_Y) MOV32RtoRm(x86reg, itreg, (uptr)VU->Mem+4);
if (_Z) MOV32RtoRm(x86reg, ftreg, (uptr)VU->Mem+8); if (_Z) MOV32RtoRm(x86reg, itreg, (uptr)VU->Mem+8);
if (_W) MOV32RtoRm(x86reg, ftreg, (uptr)VU->Mem+12); if (_W) MOV32RtoRm(x86reg, itreg, (uptr)VU->Mem+12);
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1262,15 +1265,15 @@ void recVUMI_WAITQ( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_FSAND( VURegs *VU, int info ) void recVUMI_FSAND( VURegs *VU, int info )
{ {
int ftreg; int itreg;
u16 imm; u16 imm;
//Console::WriteLn("recVUMI_FSAND"); //Console::WriteLn("recVUMI_FSAND");
imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff); imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff);
if(_Ft_ == 0) return; if(_It_ == 0) return;
ftreg = ALLOCVI(_Ft_, MODE_WRITE); itreg = ALLOCVI(_It_, MODE_WRITE);
MOV32MtoR( ftreg, VU_VI_ADDR(REG_STATUS_FLAG, 1) ); MOV32MtoR( itreg, VU_VI_ADDR(REG_STATUS_FLAG, 1) );
AND32ItoR( ftreg, imm ); AND32ItoR( itreg, imm );
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1280,18 +1283,18 @@ void recVUMI_FSAND( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_FSEQ( VURegs *VU, int info ) void recVUMI_FSEQ( VURegs *VU, int info )
{ {
int ftreg; int itreg;
u16 imm; u16 imm;
if ( _Ft_ == 0 ) return; if ( _It_ == 0 ) return;
//Console::WriteLn("recVUMI_FSEQ"); //Console::WriteLn("recVUMI_FSEQ");
imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff); imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff);
ftreg = ALLOCVI(_Ft_, MODE_WRITE|MODE_8BITREG); itreg = ALLOCVI(_It_, MODE_WRITE|MODE_8BITREG);
MOVZX32M16toR( EAX, VU_VI_ADDR(REG_STATUS_FLAG, 1) ); MOVZX32M16toR( EAX, VU_VI_ADDR(REG_STATUS_FLAG, 1) );
XOR32RtoR(ftreg, ftreg); XOR32RtoR(itreg, itreg);
CMP16ItoR(EAX, imm); CMP16ItoR(EAX, imm);
SETE8R(ftreg); SETE8R(itreg);
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1301,16 +1304,16 @@ void recVUMI_FSEQ( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_FSOR( VURegs *VU, int info ) void recVUMI_FSOR( VURegs *VU, int info )
{ {
int ftreg; int itreg;
u32 imm; u32 imm;
if(_Ft_ == 0) return; if(_It_ == 0) return;
//Console::WriteLn("recVUMI_FSOR"); //Console::WriteLn("recVUMI_FSOR");
imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff); imm = (((VU->code >> 21 ) & 0x1) << 11) | (VU->code & 0x7ff);
ftreg = ALLOCVI(_Ft_, MODE_WRITE); itreg = ALLOCVI(_It_, MODE_WRITE);
MOVZX32M16toR( ftreg, VU_VI_ADDR(REG_STATUS_FLAG, 1) ); MOVZX32M16toR( itreg, VU_VI_ADDR(REG_STATUS_FLAG, 1) );
OR32ItoR( ftreg, imm ); OR32ItoR( itreg, imm );
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1346,18 +1349,18 @@ void recVUMI_FSSET(VURegs *VU, int info)
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_FMAND( VURegs *VU, int info ) void recVUMI_FMAND( VURegs *VU, int info )
{ {
int fsreg, ftreg; int isreg, itreg;
if ( _Ft_ == 0 ) return; if ( _It_ == 0 ) return;
//Console::WriteLn("recVUMI_FMAND"); //Console::WriteLn("recVUMI_FMAND");
fsreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_READ); isreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_READ);
ftreg = ALLOCVI(_Ft_, MODE_WRITE);//|MODE_8BITREG); itreg = ALLOCVI(_It_, MODE_WRITE);//|MODE_8BITREG);
if( fsreg >= 0 ) { if( isreg >= 0 ) {
if( ftreg != fsreg ) MOV32RtoR(ftreg, fsreg); if( itreg != isreg ) MOV32RtoR(itreg, isreg);
} }
else MOVZX32M16toR(ftreg, VU_VI_ADDR(_Fs_, 1)); else MOVZX32M16toR(itreg, VU_VI_ADDR(_Is_, 1));
AND16MtoR( ftreg, VU_VI_ADDR(REG_MAC_FLAG, 1)); AND16MtoR( itreg, VU_VI_ADDR(REG_MAC_FLAG, 1));
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1367,25 +1370,25 @@ void recVUMI_FMAND( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_FMEQ( VURegs *VU, int info ) void recVUMI_FMEQ( VURegs *VU, int info )
{ {
int ftreg, fsreg; int itreg, isreg;
if ( _Ft_ == 0 ) return; if ( _It_ == 0 ) return;
//Console::WriteLn("recVUMI_FMEQ"); //Console::WriteLn("recVUMI_FMEQ");
if( _Ft_ == _Fs_ ) { if( _It_ == _Is_ ) {
ftreg = ALLOCVI(_Ft_, MODE_WRITE|MODE_READ);//|MODE_8BITREG itreg = ALLOCVI(_It_, MODE_WRITE|MODE_READ);//|MODE_8BITREG
CMP16MtoR(ftreg, VU_VI_ADDR(REG_MAC_FLAG, 1)); CMP16MtoR(itreg, VU_VI_ADDR(REG_MAC_FLAG, 1));
SETE8R(EAX); SETE8R(EAX);
MOVZX32R8toR(ftreg, EAX); MOVZX32R8toR(itreg, EAX);
} }
else { else {
ADD_VI_NEEDED(_Fs_); ADD_VI_NEEDED(_Is_);
ftreg = ALLOCVI(_Ft_, MODE_WRITE|MODE_8BITREG); itreg = ALLOCVI(_It_, MODE_WRITE|MODE_8BITREG);
fsreg = ALLOCVI(_Fs_, MODE_READ); isreg = ALLOCVI(_Is_, MODE_READ);
XOR32RtoR(ftreg, ftreg); XOR32RtoR(itreg, itreg);
CMP16MtoR(fsreg, VU_VI_ADDR(REG_MAC_FLAG, 1)); CMP16MtoR(isreg, VU_VI_ADDR(REG_MAC_FLAG, 1));
SETE8R(ftreg); SETE8R(itreg);
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1396,27 +1399,27 @@ void recVUMI_FMEQ( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_FMOR( VURegs *VU, int info ) void recVUMI_FMOR( VURegs *VU, int info )
{ {
int fsreg, ftreg; int isreg, itreg;
if ( _Ft_ == 0 ) return; if ( _It_ == 0 ) return;
//Console::WriteLn("recVUMI_FMOR"); //Console::WriteLn("recVUMI_FMOR");
if( _Fs_ == 0 ) { if( _Is_ == 0 ) {
ftreg = ALLOCVI(_Ft_, MODE_WRITE);//|MODE_8BITREG); itreg = ALLOCVI(_It_, MODE_WRITE);//|MODE_8BITREG);
MOVZX32M16toR( ftreg, VU_VI_ADDR(REG_MAC_FLAG, 1) ); MOVZX32M16toR( itreg, VU_VI_ADDR(REG_MAC_FLAG, 1) );
} }
else if( _Ft_ == _Fs_ ) { else if( _It_ == _Is_ ) {
ftreg = ALLOCVI(_Ft_, MODE_WRITE|MODE_READ);//|MODE_8BITREG); itreg = ALLOCVI(_It_, MODE_WRITE|MODE_READ);//|MODE_8BITREG);
OR16MtoR( ftreg, VU_VI_ADDR(REG_MAC_FLAG, 1) ); OR16MtoR( itreg, VU_VI_ADDR(REG_MAC_FLAG, 1) );
} }
else { else {
fsreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_READ); isreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_READ);
ftreg = ALLOCVI(_Ft_, MODE_WRITE); itreg = ALLOCVI(_It_, MODE_WRITE);
MOVZX32M16toR( ftreg, VU_VI_ADDR(REG_MAC_FLAG, 1) ); MOVZX32M16toR( itreg, VU_VI_ADDR(REG_MAC_FLAG, 1) );
if( fsreg >= 0 ) if( isreg >= 0 )
OR16RtoR( ftreg, fsreg ); OR16RtoR( itreg, isreg );
else else
OR16MtoR( ftreg, VU_VI_ADDR(_Fs_, 1) ); OR16MtoR( itreg, VU_VI_ADDR(_Is_, 1) );
} }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1427,13 +1430,13 @@ void recVUMI_FMOR( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_FCAND( VURegs *VU, int info ) void recVUMI_FCAND( VURegs *VU, int info )
{ {
int ftreg = ALLOCVI(1, MODE_WRITE|MODE_8BITREG); int itreg = ALLOCVI(1, MODE_WRITE|MODE_8BITREG);
//Console::WriteLn("recVUMI_FCAND"); //Console::WriteLn("recVUMI_FCAND");
MOV32MtoR( EAX, VU_VI_ADDR(REG_CLIP_FLAG, 1) ); MOV32MtoR( EAX, VU_VI_ADDR(REG_CLIP_FLAG, 1) );
XOR32RtoR( ftreg, ftreg ); XOR32RtoR( itreg, itreg );
AND32ItoR( EAX, VU->code & 0xFFFFFF ); AND32ItoR( EAX, VU->code & 0xFFFFFF );
SETNZ8R(ftreg); SETNZ8R(itreg);
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1443,14 +1446,14 @@ void recVUMI_FCAND( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_FCEQ( VURegs *VU, int info ) void recVUMI_FCEQ( VURegs *VU, int info )
{ {
int ftreg = ALLOCVI(1, MODE_WRITE|MODE_8BITREG); int itreg = ALLOCVI(1, MODE_WRITE|MODE_8BITREG);
//Console::WriteLn("recVUMI_FCEQ"); //Console::WriteLn("recVUMI_FCEQ");
MOV32MtoR( EAX, VU_VI_ADDR(REG_CLIP_FLAG, 1) ); MOV32MtoR( EAX, VU_VI_ADDR(REG_CLIP_FLAG, 1) );
AND32ItoR( EAX, 0xffffff ); AND32ItoR( EAX, 0xffffff );
XOR32RtoR( ftreg, ftreg ); XOR32RtoR( itreg, itreg );
CMP32ItoR( EAX, VU->code&0xffffff ); CMP32ItoR( EAX, VU->code&0xffffff );
SETE8R(ftreg); SETE8R(itreg);
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1460,14 +1463,14 @@ void recVUMI_FCEQ( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_FCOR( VURegs *VU, int info ) void recVUMI_FCOR( VURegs *VU, int info )
{ {
int ftreg; int itreg;
//Console::WriteLn("recVUMI_FCOR"); //Console::WriteLn("recVUMI_FCOR");
ftreg = ALLOCVI(1, MODE_WRITE); itreg = ALLOCVI(1, MODE_WRITE);
MOV32MtoR( ftreg, VU_VI_ADDR(REG_CLIP_FLAG, 1) ); MOV32MtoR( itreg, VU_VI_ADDR(REG_CLIP_FLAG, 1) );
OR32ItoR ( ftreg, VU->code ); OR32ItoR ( itreg, VU->code );
AND32ItoR( ftreg, 0xffffff ); AND32ItoR( itreg, 0xffffff );
ADD32ItoR( ftreg, 1 ); // If 24 1's will make 25th bit 1, else 0 ADD32ItoR( itreg, 1 ); // If 24 1's will make 25th bit 1, else 0
SHR32ItoR( ftreg, 24 ); // Get the 25th bit (also clears the rest of the garbage in the reg) SHR32ItoR( itreg, 24 ); // Get the 25th bit (also clears the rest of the garbage in the reg)
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1492,13 +1495,13 @@ void recVUMI_FCSET( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_FCGET( VURegs *VU, int info ) void recVUMI_FCGET( VURegs *VU, int info )
{ {
int ftreg; int itreg;
if(_Ft_ == 0) return; if(_It_ == 0) return;
//Console::WriteLn("recVUMI_FCGET"); //Console::WriteLn("recVUMI_FCGET");
ftreg = ALLOCVI(_Ft_, MODE_WRITE); itreg = ALLOCVI(_It_, MODE_WRITE);
MOV32MtoR(ftreg, VU_VI_ADDR(REG_CLIP_FLAG, 1)); MOV32MtoR(itreg, VU_VI_ADDR(REG_CLIP_FLAG, 1));
AND32ItoR(ftreg, 0x0fff); AND32ItoR(itreg, 0x0fff);
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1944,11 +1947,11 @@ void recVUMI_EEXP( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_XITOP( VURegs *VU, int info ) void recVUMI_XITOP( VURegs *VU, int info )
{ {
int ftreg; int itreg;
if (_Ft_ == 0) return; if (_It_ == 0) return;
//Console::WriteLn("recVUMI_XITOP"); //Console::WriteLn("recVUMI_XITOP");
ftreg = ALLOCVI(_Ft_, MODE_WRITE); itreg = ALLOCVI(_It_, MODE_WRITE);
MOVZX32M16toR( ftreg, (uptr)&VU->vifRegs->itop ); MOVZX32M16toR( itreg, (uptr)&VU->vifRegs->itop );
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1958,11 +1961,11 @@ void recVUMI_XITOP( VURegs *VU, int info )
//------------------------------------------------------------------ //------------------------------------------------------------------
void recVUMI_XTOP( VURegs *VU, int info ) void recVUMI_XTOP( VURegs *VU, int info )
{ {
int ftreg; int itreg;
if ( _Ft_ == 0 ) return; if ( _It_ == 0 ) return;
//Console::WriteLn("recVUMI_XTOP"); //Console::WriteLn("recVUMI_XTOP");
ftreg = ALLOCVI(_Ft_, MODE_WRITE); itreg = ALLOCVI(_It_, MODE_WRITE);
MOVZX32M16toR( ftreg, (uptr)&VU->vifRegs->top ); MOVZX32M16toR( itreg, (uptr)&VU->vifRegs->top );
} }
//------------------------------------------------------------------ //------------------------------------------------------------------

169
pcsx2/x86/iVUzerorec.cpp
View File

@ -71,6 +71,9 @@ extern void iDumpVU1Registers();
#define _Ft_ ((VU->code >> 16) & 0x1F) // The rt part of the instruction register #define _Ft_ ((VU->code >> 16) & 0x1F) // The rt part of the instruction register
#define _Fs_ ((VU->code >> 11) & 0x1F) // The rd part of the instruction register #define _Fs_ ((VU->code >> 11) & 0x1F) // The rd part of the instruction register
#define _Fd_ ((VU->code >> 6) & 0x1F) // The sa part of the instruction register #define _Fd_ ((VU->code >> 6) & 0x1F) // The sa part of the instruction register
#define _It_ (_Ft_ & 15)
#define _Is_ (_Fs_ & 15)
#define _Id_ (_Fd_ & 15)
static const u32 QWaitTimes[] = { 6, 12 }; static const u32 QWaitTimes[] = { 6, 12 };
static const u32 PWaitTimes[] = { 53, 43, 28, 23, 17, 11, 10 }; static const u32 PWaitTimes[] = { 53, 43, 28, 23, 17, 11, 10 };
@ -3600,92 +3603,92 @@ void recVUMI_BranchHandle()
// supervu specific insts // supervu specific insts
void recVUMI_IBQ_prep() void recVUMI_IBQ_prep()
{ {
int fsreg, ftreg; int isreg, itreg;
if( _Fs_ == 0 ) { if( _Is_ == 0 ) {
#ifdef SUPERVU_VIBRANCHDELAY #ifdef SUPERVU_VIBRANCHDELAY
if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Ft_ ) { if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _It_ ) {
ftreg = -1; itreg = -1;
} }
else else
#endif #endif
{ {
ftreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Ft_, MODE_READ); itreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _It_, MODE_READ);
} }
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE); s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
if( ftreg >= 0 ) { if( itreg >= 0 ) {
CMP16ItoR( ftreg, 0 ); CMP16ItoR(itreg, 0);
} }
else CMP16ItoM(SuperVUGetVIAddr(_Ft_, 1), 0); else CMP16ItoM(SuperVUGetVIAddr(_It_, 1), 0);
} }
else if( _Ft_ == 0 ) { else if( _It_ == 0 ) {
#ifdef SUPERVU_VIBRANCHDELAY #ifdef SUPERVU_VIBRANCHDELAY
if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Fs_ ) { if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Is_ ) {
fsreg = -1; isreg = -1;
} }
else else
#endif #endif
{ {
fsreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_READ); isreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_READ);
} }
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE); s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
if( fsreg >= 0 ) { if( isreg >= 0 ) {
CMP16ItoR( fsreg, 0 ); CMP16RtoR(isreg, 0);
} }
else CMP16ItoM(SuperVUGetVIAddr(_Fs_, 1), 0); else CMP16ItoM(SuperVUGetVIAddr(_Is_, 1), 0);
} }
else { else {
_addNeededX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Ft_); _addNeededX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _It_);
#ifdef SUPERVU_VIBRANCHDELAY #ifdef SUPERVU_VIBRANCHDELAY
if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Fs_ ) { if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Is_ ) {
fsreg = -1; isreg = -1;
} }
else else
#endif #endif
{ {
fsreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_READ); isreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_READ);
} }
#ifdef SUPERVU_VIBRANCHDELAY #ifdef SUPERVU_VIBRANCHDELAY
if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Ft_ ) { if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _It_ ) {
ftreg = -1; itreg = -1;
if( fsreg <= 0 ) { if( isreg <= 0 ) {
// allocate fsreg // allocate fsreg
if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Fs_ ) { if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Is_ ) {
fsreg = _allocX86reg(-1, X86TYPE_TEMP, 0, MODE_READ|MODE_WRITE); isreg = _allocX86reg(-1, X86TYPE_TEMP, 0, MODE_READ|MODE_WRITE);
MOV32MtoR(fsreg, SuperVUGetVIAddr(_Fs_, 1)); MOV32MtoR(isreg, SuperVUGetVIAddr(_Is_, 1));
} }
else else
fsreg = _allocX86reg(-1, X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_READ); isreg = _allocX86reg(-1, X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_READ);
} }
} }
else else
#endif #endif
{ {
ftreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Ft_, MODE_READ); itreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _It_, MODE_READ);
} }
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE); s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
if( fsreg >= 0 ) { if( isreg >= 0 ) {
if( ftreg >= 0 ) { if( itreg >= 0 ) {
CMP16RtoR( fsreg, ftreg ); CMP16RtoR( isreg, itreg );
} }
else CMP16MtoR(fsreg, SuperVUGetVIAddr(_Ft_, 1)); else CMP16MtoR(isreg, SuperVUGetVIAddr(_It_, 1));
} }
else if( ftreg >= 0 ) { else if( itreg >= 0 ) {
CMP16MtoR(ftreg, SuperVUGetVIAddr(_Fs_, 1)); CMP16MtoR(itreg, SuperVUGetVIAddr(_Is_, 1));
} }
else { else {
fsreg = _allocX86reg(-1, X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_READ); isreg = _allocX86reg(-1, X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_READ);
CMP16MtoR(fsreg, SuperVUGetVIAddr(_Ft_, 1)); CMP16MtoR(isreg, SuperVUGetVIAddr(_It_, 1));
} }
} }
} }
@ -3699,25 +3702,25 @@ void recVUMI_IBEQ( VURegs* vuu, s32 info )
void recVUMI_IBGEZ( VURegs* vuu, s32 info ) void recVUMI_IBGEZ( VURegs* vuu, s32 info )
{ {
int fsreg; int isreg;
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE); s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
#ifdef SUPERVU_VIBRANCHDELAY #ifdef SUPERVU_VIBRANCHDELAY
if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Fs_ ) { if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Is_ ) {
fsreg = -1; isreg = -1;
} }
else else
#endif #endif
{ {
fsreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_READ); isreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_READ);
} }
if( fsreg >= 0 ) { if( isreg >= 0 ) {
OR16RtoR(fsreg, fsreg); TEST16RtoR(isreg, isreg);
j8Ptr[ 0 ] = JS8( 0 ); j8Ptr[ 0 ] = JS8( 0 );
} }
else { else {
CMP16ItoM( SuperVUGetVIAddr(_Fs_, 1), 0x0 ); CMP16ItoM( SuperVUGetVIAddr(_Is_, 1), 0x0 );
j8Ptr[ 0 ] = JL8( 0 ); j8Ptr[ 0 ] = JL8( 0 );
} }
@ -3726,25 +3729,25 @@ void recVUMI_IBGEZ( VURegs* vuu, s32 info )
void recVUMI_IBGTZ( VURegs* vuu, s32 info ) void recVUMI_IBGTZ( VURegs* vuu, s32 info )
{ {
int fsreg; int isreg;
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE); s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
#ifdef SUPERVU_VIBRANCHDELAY #ifdef SUPERVU_VIBRANCHDELAY
if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Fs_ ) { if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Is_ ) {
fsreg = -1; isreg = -1;
} }
else else
#endif #endif
{ {
fsreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_READ); isreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_READ);
} }
if( fsreg >= 0 ) { if( isreg >= 0 ) {
CMP16ItoR(fsreg, 0); CMP16ItoR(isreg, 0);
j8Ptr[ 0 ] = JLE8( 0 ); j8Ptr[ 0 ] = JLE8( 0 );
} }
else { else {
CMP16ItoM( SuperVUGetVIAddr(_Fs_, 1), 0x0 ); CMP16ItoM( SuperVUGetVIAddr(_Is_, 1), 0x0 );
j8Ptr[ 0 ] = JLE8( 0 ); j8Ptr[ 0 ] = JLE8( 0 );
} }
recVUMI_BranchHandle(); recVUMI_BranchHandle();
@ -3752,25 +3755,25 @@ void recVUMI_IBGTZ( VURegs* vuu, s32 info )
void recVUMI_IBLEZ( VURegs* vuu, s32 info ) void recVUMI_IBLEZ( VURegs* vuu, s32 info )
{ {
int fsreg; int isreg;
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE); s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
#ifdef SUPERVU_VIBRANCHDELAY #ifdef SUPERVU_VIBRANCHDELAY
if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Fs_ ) { if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Is_ ) {
fsreg = -1; isreg = -1;
} }
else else
#endif #endif
{ {
fsreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_READ); isreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_READ);
} }
if( fsreg >= 0 ) { if( isreg >= 0 ) {
CMP16ItoR(fsreg, 0); CMP16ItoR(isreg, 0);
j8Ptr[ 0 ] = JG8( 0 ); j8Ptr[ 0 ] = JG8( 0 );
} }
else { else {
CMP16ItoM( SuperVUGetVIAddr(_Fs_, 1), 0x0 ); CMP16ItoM( SuperVUGetVIAddr(_Is_, 1), 0x0 );
j8Ptr[ 0 ] = JG8( 0 ); j8Ptr[ 0 ] = JG8( 0 );
} }
recVUMI_BranchHandle(); recVUMI_BranchHandle();
@ -3778,25 +3781,25 @@ void recVUMI_IBLEZ( VURegs* vuu, s32 info )
void recVUMI_IBLTZ( VURegs* vuu, s32 info ) void recVUMI_IBLTZ( VURegs* vuu, s32 info )
{ {
int fsreg; int isreg;
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE); s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
#ifdef SUPERVU_VIBRANCHDELAY #ifdef SUPERVU_VIBRANCHDELAY
if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Fs_ ) { if( s_pCurInst->vicached >= 0 && s_pCurInst->vicached == _Is_ ) {
fsreg = -1; isreg = -1;
} }
else else
#endif #endif
{ {
fsreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Fs_, MODE_READ); isreg = _checkX86reg(X86TYPE_VI|(VU==&VU1?X86TYPE_VU1:0), _Is_, MODE_READ);
} }
if( fsreg >= 0 ) { if( isreg >= 0 ) {
OR16RtoR(fsreg, fsreg); TEST16RtoR(isreg, isreg);
j8Ptr[ 0 ] = JNS8( 0 ); j8Ptr[ 0 ] = JNS8( 0 );
} }
else { else {
CMP16ItoM( SuperVUGetVIAddr(_Fs_, 1), 0x0 ); CMP16ItoM( SuperVUGetVIAddr(_Is_, 1), 0x0 );
j8Ptr[ 0 ] = JGE8( 0 ); j8Ptr[ 0 ] = JGE8( 0 );
} }
recVUMI_BranchHandle(); recVUMI_BranchHandle();
@ -3842,9 +3845,9 @@ void recVUMI_BAL( VURegs* vuu, s32 info )
SuperVUTestVU0Condition(0); SuperVUTestVU0Condition(0);
} }
if ( _Ft_ ) { if ( _It_ ) {
_deleteX86reg(X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Ft_, 2); _deleteX86reg(X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _It_, 2);
MOV16ItoM( SuperVUGetVIAddr(_Ft_, 0), (pc+8)>>3 ); MOV16ItoM( SuperVUGetVIAddr(_It_, 0), (pc+8)>>3 );
} }
if( s_pCurBlock->blocks.size() > 1 ) { if( s_pCurBlock->blocks.size() > 1 ) {
@ -3859,8 +3862,8 @@ void recVUMI_BAL( VURegs* vuu, s32 info )
void recVUMI_JR( VURegs* vuu, s32 info ) void recVUMI_JR( VURegs* vuu, s32 info )
{ {
int fsreg = _allocX86reg(-1, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Fs_, MODE_READ); int isreg = _allocX86reg(-1, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Is_, MODE_READ);
LEA32RStoR(EAX, fsreg, 3); LEA32RStoR(EAX, isreg, 3);
//Mask the address to something valid //Mask the address to something valid
if(vuu == &VU0) if(vuu == &VU0)
@ -3879,10 +3882,10 @@ void recVUMI_JR( VURegs* vuu, s32 info )
void recVUMI_JALR( VURegs* vuu, s32 info ) void recVUMI_JALR( VURegs* vuu, s32 info )
{ {
_addNeededX86reg(X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Ft_); _addNeededX86reg(X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _It_);
int fsreg = _allocX86reg(-1, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Fs_, MODE_READ); int isreg = _allocX86reg(-1, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Is_, MODE_READ);
LEA32RStoR(EAX, fsreg, 3); LEA32RStoR(EAX, isreg, 3);
//Mask the address to something valid //Mask the address to something valid
if(vuu == &VU0) if(vuu == &VU0)
@ -3890,9 +3893,9 @@ void recVUMI_JALR( VURegs* vuu, s32 info )
else else
AND32ItoR(EAX, 0x3fff); AND32ItoR(EAX, 0x3fff);
if ( _Ft_ ) { if ( _It_ ) {
_deleteX86reg(X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Ft_, 2); _deleteX86reg(X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _It_, 2);
MOV16ItoM( SuperVUGetVIAddr(_Ft_, 0), (pc+8)>>3 ); MOV16ItoM( SuperVUGetVIAddr(_It_, 0), (pc+8)>>3 );
} }
if( (s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 ) MOV32RtoM(SuperVUGetVIAddr(REG_TPC, 0), EAX); if( (s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 ) MOV32RtoM(SuperVUGetVIAddr(REG_TPC, 0), EAX);
@ -3957,15 +3960,15 @@ void recVUMI_XGKICK( VURegs *VU, int info )
recVUMI_XGKICK_(VU); recVUMI_XGKICK_(VU);
} }
int fsreg = _allocX86reg(X86ARG2, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Fs_, MODE_READ); int isreg = _allocX86reg(X86ARG2, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Is_, MODE_READ);
_freeX86reg(fsreg); // flush _freeX86reg(isreg); // flush
x86regs[fsreg].inuse = 1; x86regs[isreg].inuse = 1;
x86regs[fsreg].type = X86TYPE_VITEMP; x86regs[isreg].type = X86TYPE_VITEMP;
x86regs[fsreg].needed = 1; x86regs[isreg].needed = 1;
x86regs[fsreg].mode = MODE_WRITE|MODE_READ; x86regs[isreg].mode = MODE_WRITE|MODE_READ;
SHL32ItoR(fsreg, 4); SHL32ItoR(isreg, 4);
AND32ItoR(fsreg, 0x3fff); AND32ItoR(isreg, 0x3fff);
s_XGKICKReg = fsreg; s_XGKICKReg = isreg;
if( !SUPERVU_XGKICKDELAY || pc == s_pCurBlock->endpc ) { if( !SUPERVU_XGKICKDELAY || pc == s_pCurBlock->endpc ) {
recVUMI_XGKICK_(VU); recVUMI_XGKICK_(VU);